A Critical-Conduction-Mode Bridgeless Interleaved Boost Power Factor Correction

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1 A CriticalConductionMode Bridgeless Interleaved Boost Power Factor Correction Its Control Scheme Based on Commonly Available Controller PEDS2009 E. Firmansyah, S. Abe, M. Shoyama Dept. of Electrical and Electronic Systems Engineering Graduate School of ISEE, Kyushu University Fukuoka, Japan S. Tomioka SPS R&D Division TDKLambda Corporation Fukuoka, Japan Abstract This paper describes about how to utilize the industry standard critical conduction mode (CRM) boost interleaved power factor correction (PFC) control IC in a bridgeless environment. The proposed control technique is based on control signal diversion. It makes the bridgeless CRM boost interleaved PFC control signal looks like a conventional bridgedcrm boost interleaved PFC to the control IC. The presented solution has proven for its simplicity and its feasibility. In this paper, the control theory, considerations, and experiment data will be thoroughly presented. Keywordscriticalconductionmode (CRM); bridgeless; interleaved; boost;power factor correction; control scheme. T. Ninomiya Energy Electronics Laboratory Faculty of Engineering, Nagasaki University Nagasaki, Japan I. INTRODUCTION The bridgeless boost PFC was born in order to maximize converter's efficiency. In that circuit, the number of semiconductor used in the line current path is reduced [1]. It lessens the energy loss that usually occurs inside bridged PFC circuit. In other side, criticalconductionmode (CRM) interleaved boost powerfactorcorrection (PFC) has started to gain widespread acceptance. This topology is characterized by simple control scheme, zerocurrentswitch (ZCS) during switch turnon transition, and to some degree it also possible to have zerovoltageswitch (ZVS) turnon transition. Moreover, the interleaved technique reduces the input current ripple. Therefore, its wave shape is quite similar to the infamous continuousconductionmode (CCM) boost converter [2]. Those ZCS, ZVS, and lowripple input current of [2] not only make the converter efficiency increase but also reduce the conducted EMI. Other than that, those good characters can be achieved by smaller inductor, reasonable size capacitor, and lessideal switches and diodes. Therefore, it is reasonable to combine both technique the bridgeless and the CRM interleaved boost PFC to a new topology and expecting that those good characters be also inherited. Fig. 1. The proposed CRM bridgeless interleaved boost PFC. However, industry standard IC for the new topology has not yet been available. Therefore, a proprietary control circuit should be created. The control circuit could be based on analog, digital, or mixed analogdigital circuit. However, this new control circuit should faces for several drawbacks those are commonly found in a proprietary circuit; high cost, not yet well proven, and lack of well protection circuit. This paper explains about the control scheme of a bridgeless CRM interleaved boost PFC based on a wellproven, commonly available, and low cost control IC that is normally targeted for conventional CRM boost PFC. The theoretical background about how to use the IC in bridgeless environment and some real circuit performance reports will be thoroughly described. II. THE CRM BRIDGELESS INTERLEAVED PFC Fig. 1 shows the proposed converter. The circuit is based on totempole dualboost PFC rectifier [1]. This topology has been chosen the base circuit as it gives least component number and simpler implementation circuit while operated under interleaved scheme. 109

2 Fig. 3. Illustration of CRM boost PFC input current waveform. (a) (b) Fig. 2. Switch operation during (a) positive and (b) negative phase of V i. Moreover, the topology is only suitable for discontinuous conduction mode (DCM) and CRM operation. The operating condition limitation is caused by slow reverse recovery characteristics of the switches body diode. It is also mentioned in [3] that the base topology is less susceptible from commonmode noise problem that is normally occurs in basic bridgeless circuit [4]. The proposed converter consists of two inductors and four switches. Those components create two legs with L 1, S 1, and S 2 form leg 1 while L 2, S 3, and S 4 form leg 2. The legs operate under interleaved scheme to reduce the input current ripple. Two line frequency diodes (D 1 and D 2 ) are also implemented in this scheme, similar to the original topology in [1]. However, they carry continuous current due to interleaved operation nature of this proposed scheme instead of pulsating and discontinuous one. A. Basic operating principle Switches on Fig. 1 are grouped into positivephase group (S 2 and S 4 ) and negativephase group (S 1 and S 3 ). The positivephase group operates as boostswitches during positive phase of input voltage V i. During this period, bodydiodes of the negativephase group act as the catch diodes. In this phase, return current is delivered by D 2. The converter operation during this stage is illustrated by Fig. 2. (a). When V i is in its negative phase, the opposite condition occurs. Through out this time, negativephase group operates as the boost switches and the positivephase group body diodes work as the catch diodes. Return current is handled by D 1. Fig. 2 (b) depicts this condition. B. The interleave scheme Leg 1 (S 1 and S 2 ) and leg 2 (S 3 and S 4 ) form complete functional block of a boost converter. The control circuit orchestrated operation of both legs to be 180 degrees out of phase. In other word, those boost converters are under interleaved operation. As D 1 and D 2 carry the sum current of interleaved leg 1 and leg 2, it contains relatively small amount of ripple. Otherwise, the ripple current will be significant as normally happens in conventional CRM boost PFC. C. The critical conduction mode operation Fig. 3 illustrates the inductor current i L condition related to the programmed input current i i in a CRM boost PFC converter. The figure shows that i L is switched very fast between zero to two times i i in order to be proportional to V i hence gives good power factor. i i can be calculated by (1). It is apparent from the equation that t on should be kept constant at least for one cycle of V i in order to make i i proportional to V i. i 1 1 ii = Vi t 2 on (1) L L ( V V ) i o = toff (2) L t off can be determined based on (2) when i L equal to zero. t off varies as a function of phase θ as its value is determined by V i (θ). Equation (1) should be multiplied by two in order to determine the i i for an interleaved boost PFC converter. That is because the referred converter consists of two inductors that carry the same amount of current with 180 degrees out of phase. 110

3 C S1 v S1=0 C S3 v S3 =0 C D1 v D1=0 V i L 1 L 2 C R L V L C S2 C S4 v S2=V L C D2 v S4=V L v D2=V L Fig. 6. The circuit configuration during phase transition from () to (). Fig. 4. Keywaveforms of a boost converter working under CRM. Fig. 4 describe an interesting phenomenon occurs in a CRM boost converter. Resonant condition between input inductor and the switch parasitic capacitance occurs during t d. At certain time and conditions, this may completely discharge the parasitic capacitance of the switch. When considered properly, it is possible for the switch to turnon under ZVS condition. This results in higher converter efficiency. D. The voltage ringing problem around zerocrossing point Every time V i crossing the zero point toward a new phase, the proposed converter enters an idle condition. Its waveforms during idle and some period after that is shown in Fig. 5. The circuit configuration at that time is shown in Fig. 6. Fig. 6 illustrates the circuit condition during () to () phase transition. It is shown here that during idle time, parasitic capacitance of the switches and diodes dominate the converter state. Those capacitances are charged to certain value depend on the former operating condition whether positive or negative phase. Phase detected VDS1 (250 V/div) VDS2 (250 V/div) Vi (50 V/div) 1 st PWM signal Oscillate VL1 (250 V/div) Phase (20 V/div) VGS2 (20 V/div) Careful attention should be made on the capacitances of the two diodes. During () to () phase transition, for example, the parasitic capacitance of diode 2 (C D2 ) is charged up to V L while voltages of C D1 is nearly zero. When the first PWM signal occurs, C D2 will be discharged through the input inductance and V i. Here, discharging process is under resonant condition among the input inductance and the parallelconnected parasitic capacitance of diodes. It should be noted that at this moment, V i is still very small and is in phase to the charge stored inside C D1. This creates current pulse and excites quite disturbing voltage and current oscillation as shown in Fig. 5. The oscillating voltage and currents might result in several problems like: 1. momentarily wrong phase detection that result in shoot trough of the V L to the V i. It gives significant penalty to the converter efficiency and even to the destruction of the converter, 2. increasing the cusp distortion around zerocrossing point that result in higher input current THD, 3. significantly, increase the converter s conducted EMI. Those list figure out that the ringing should be addressed properly in order to achieve good performance of the proposed converter. III. CONTROL SCHEME A. The Conventional Control IC A conventional CRM interleaved boost PFC control circuit needs to monitor at least two kinds of input in order to maintain its operation: (1) output voltage V L and (2) zerocrossing instant time of current in each inductor [5, 6]. The controller may need additional auxiliary input in order to improve its performance. However, those two basic inputs are mandatory. Fig. 7 illustrates the block diagram of the referred controller. VD1 (250 V/div) VD2 (250 V/div) Idle 50 us/div ii (2 A/div) Oscillate Fig. 5. The proposed topology keywaveforms during phase transition. Fig. 7. Conventional CRM interleaved boost PFC block diagram. 111

4 blanking V i t I i Fig. 10. Blanking mechanism inside the phase detector circuit to avoid wrong phase detection due to noise. Fig. 8. The proposed control scheme for the CRM bridgeless interleaved boost PFC converter. B. Required Control Operation for the Propossed Converter The proposed converter possesses two differences to the conventional CRM interleaved boost PFC those are: (1) L 1 and L 2 now located in ac side instead of dc side and (2) switches group operation should be synchronized to the input line voltage. Additional circuits should be added to the conventional control IC therefore it could be used to control the proposed converter. Those additional circuits are: 1) Phase detector circuit This circuit generates [Ph. ] signal when the input voltage V i is positive and generates [Ph. ] when V i is negative. Those signals are used as references to other extracircuits in order to maintain proper control operation. The block diagram of the phase detector circuit is shown in Fig. 9. In that block diagram, two nonretrigerable astables are used as blanking mechanism to avoid wrong phase detection during voltage ringing period around zerocrossing point of V i. Fig. 10 illustrates the aforementioned blanking mechanism inside phase detection circuit. During blanking period, output of the phase detector circuit is maintained stable irrespective to the actual V i condition. With this mechanism, wrong phase detection caused by input voltage ringing around zerocrossing point can be avoided. 2) Zerocurrent signal diverter circuit In the proposed topology, L 1 and L 2 are positioned in ac side instead of dc side like in a conventional CRM interleaved PFC circuit. Positioned in ac side means the zerocurrent signal generated by the sense windings will change its polarity every time V i changes its phase. Controller of a conventional CRM interleaved boost converter normally relies on certain logic condition to determine the occurrence of zerocrossing point of current in L 1 and L 2. In order to make the controller sense the same environment, two kinds of adaptations are required; (1) change the sense winding from single winding into centertapped winding and (2) implement a signal diverter circuit. Implementation of the above scheme is depicted in Fig. 11. In that circuit, the positive side of the sense coil will be connected to the zerocurrent detector circuit of the control IC when [Ph. ] signal is active. Otherwise, negative sense coil will be connected to it when [Ph. ] signal is active. 3) PWM signal diverter The upper and lower switch group of the proposed converter operation should be synchronized with the phase of V i. It means during positive phase of V i, PWM signal should be used to control the lower switch group and during negative phase of V i, it should be connected to high side switch group. L 1 L1 Sense L1 Sense V cc Ph. Ph. Ph. L1 Sense Ph. Fig. 11. Zerocurrent signal diverter circuit. Fig. 9. Phase detector block diagram. Fig. 12. PWM signal diverter. 112

5 (a) Fig. 14. i i harmonic measurement during P o = 99.1 W V i = 100 V rms. (b) Fig. 13. (a) Efficiency and (b) power factor comparison among conventional and the bridgeless CRM interleaved boost converter. Implementation of this PWM signal diverter is straight forward and can be seen in Fig. 12. The circuit is based on two AND gate. The PWM signal is diverted to PWM when [Ph. ] signal is generated otherwise it will be diverted to PWMwhen [Ph. ] signal is generated. IV. EXPERIMENTAL RESULT A prototype of the CRM bridgeless interleaved boost converter that is controlled by this proposed control technique has been built. Its specification can be seen in Table I. A conventional CRM interleaved boost PFC with similar specification also has been built for comparison purpose. Efficiency and power factor comparison among conventional and bridgeless CRM interleaved boost converter can be seen in Fig. 13. (a) and (b) respectively. Depicted in those figures that due to the problem stated in part V, efficiency and PF performance of the proposed converter are still below the conventional CRM interleaved type. However, the overall performance is still good while considered that the result is taken by cheaper and smaller component compared to the conventional CCM boost PFC. TABLE I THE CONVERTERS LIST OF PARAMETERS Target power 300 W Switches MOSFET SPP11N60S5 Inductors 340 uh Capacitors 200 uf Output Voltages 390 V The harmonic content of the new converter, even though slightly high due to apparent cusp distortion around zerocrossing point of V i, is still considered save for IEC class D equipment. This evident can be seen in Fig. 14. It is also showed there that the proposed converter contain quite significant third harmonic current. Fig. 15 describe about current condition inside i L1 and i i. It is clear that even though i L1 contains fast change current signal, it becomes smoother while combined with the i L2 and results for i i. This is the merit of an interleaved boost technique. Evident of ZCS and ZVS switching condition can be found in Fig. 16. This occurrence makes the reverse recovery problem that normally gives significant impact to the converter performance become less evident. 1 ms/div V i =50 V/div i L1 =1 A/div i i =1 A/div Fig. 15. Comparison of i L1 to the i i that shown superior performance of interleaved technique. 113

6 V GS =5 V/div V DS =100 V/div ZVS PEDS2009 This control method is simple and does not alter any characters of formerly wellproven control scheme. This makes the proposed control technique ready for direct application to the new PFC circuit. It is evident that the new control scheme is success in making the new topology implementable. It is shown here that the new PFC topology, at recent stage, be able to pass the IEC class D standard while also performing reasonable efficiency even though some practical problems exist. Further developments towards better results are still widely open and promising. This new topology is a good candidate towards low to middle power PFC target. 1 us/div i L1 =1 A/div MOSFET body diode reverse recovery ZCS Fig. 16. Illustration of ZCS and ZCS switching condition occurs inside the CRM bridgeless interleaved boost PFC converter. V. CONCLUSION A control technique based on conventionally available IC for a CRM bridgeless interleaved PFC has been presented. Its basic principle, underlying equations, control scheme, problems, and experimental results have been shown thoroughly. REFERENCES [1] L. Huber, Yungtaek Jang, M.M. Jovanovic, Performance Evaluation of Bridgeless PFC Boost Rectifiers, IEEE Transactions on Power Electronics Volume 23, Issue 3, May 2008 Page(s): [2] Michael O Loughlin, An Interleaving PFC PreRegulator for High Power Converters, SEM1700, 2006/2007 Texas Instruments Power Supply Design Seminar. [3] Y. Jang and M M. Jovanovic, A Bridgeless PFC Boost Rectifier with Optimized Magnetic Utilization, in IEEE Trans. on Power Electronics, Vol. 24, No. 1. Jan. 2009, pp [4] D.M. Mitchell, ACDC converter having an improved power factor U.S. Patent , Oct. 25, [5] Texas Instruments, UCC28060 datasheet, Rev. Nov [6] Renesas, R2A20112SP/DD datasheet, Rev 2.0, Nov 12,

works must be obtained from the IEE

works must be obtained from the IEE NAOSITE: Nagasaki University's Ac Title Author(s) A criticalconductionmode bridgele correction Firmansyah, E.; Tomioka, S.; Abe, S Citation INTEEC 2009, pp.15; 2009 Issue Date 200910 UR Right http://hdl.handle.net/10069/23229

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