Simulation of Improved Dynamic Response in Active Power Factor Correction Converters

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1 Simulation of Improved Dynamic Response in Active Power Factor Correction Converters Matada Mahesh 1 and A K Panda 2 Abstract This paper introduces a novel method in improving the dynamic response of active power factor correction (APFC) converter for power supplies. Regarding power factor correction converters as highly non-linear plants with inherence parameter uncertainties, the deleterious effect due to large disturbances in line voltage is tackled by two sided latched pulse width modulation (PWM) technique with sophisticated feedback control loops. The objective is to improve the dynamic response of the APFC converter with the primary priority of achieving nearly unity input power factor. The performance of the power factor correction converter for variable input voltage is observed by simulating in PSIM. Simulation results, which are presented for dc output voltage of 400V, 100W average current mode controlled APFC converter, show significantly improved step-input voltage transient responses. Key words: Pulse width modulation, power factor correction, dynamic response, average current mode control. 1. Introduction The advanced technologies demand the use of power electronic converters in industrial, commercial and residential applications which resulted in an unappeasable growth of non-linear loads. The non-linear nature of these converters draw excessive peak input currents, causing a high level of harmonics, and both the input power factor & total harmonic distortion (THD) are poor. Generally, APFC systems are designed at high frequency converters that are controlled by two feedback loops. Voltage loop is the outer loop which regulates the output voltage with slow-response and the inner loop that shapes the input current, is a much faster loop. The main disadvantage in the APFC converters is the poor output voltage dynamics. This is because of the presence of the low-pass filter placed in the voltage feedback circuit [Fernandez, Sebastian, Villegas, Hernando, and D G Lamar (2005), Rathi, Bhiwapurkar and Mohan (2003), Prodic (2007)]. Most APFC converters always use closed-loop negative feed-back systems with PWM technique to achieve objectives for line and load regulation. Most PWM controllers use a clock-edge to set one edge of the PWM signal and feed-back to set the other edge of the PWM signal. But, one edge available for control remains unused. This direct duty cycle control has disadvantages like slow response to sudden input changes, poor audio susceptibility and poor open loop line regulation [Dixon (1986)]. In both current mode and voltage mode control, PWM [L H Dixon (1986), Ridley (1990), Mohan, Undeland and Robbins 1 Research Scholar, matadamaheshu@gmail.com 2 Professor Electrical Engineering Department, NIT, Rourkela

2 Figure 1. Two sided latched PWM schematicc for APFC ac-dc converter. (1995)] is restricted that it usess one of two edges available for control. Controller with hysteresis based of power converters makes use of both edges but the switching frequency is allowed to vary and control scheme is sensitive to commutation noises [Zhou, Ridley and Lee (1990), Yang and Wang (1999), Rossetto, Spiazzi and Tenti (1994)]. Variation in the switching frequency makes it difficult to filter the ripple components in the input and output waveforms of the converters [Midya and Haddadd (2000)]. Therefore, it is essential to have constant switching frequency to obtain nearly unity power factor in power supplies to increase the efficiency of the electrical power grid and to meet the specifications of International standards. Employing two sided PWM technique improves the dynamic response of the power factor correction converter & it is most suitable for high frequency applications. Employing two sided PWM to APFC converter is not known to be present in the literature of all references mentioned above and including [Suryawanshi, Ramteke, Thakre and Borghate (2008)]. 2. Operation of two sided PWM The two sided latched PWM [Midya and Haddadd (2000)] proposed scheme for APFC ac-dc converter is shown in Fig. 1 whichh achieves modulation of both edges while maintaining fully latched operation. In this PWM scheme two comparators are used instead of one to set and to reset the switch. One comparator is used for the comparison between the -offset feedback signal (Sign-0.5) and ramp to set the switch while another comparison between an +offset feed-back signal (sign+0.5) and ramp is used to reset the switch. The ramp is not a saw-tooth, whichh is hard to generate at high frequencies, but a triangular ramp wave with equal rising and falling slopes. The ramp is used to stabilize the duty ratio of the switch and to set the switching frequency. The ramp amplitude is chosen to meet the equal ramp slope criteria for optimal current mode control. Fig. 1 shows a sensor-less current mode control implementation, in an inner current mode control of APFC ac-dcc converter.

3 3. Time Domain Analysis Fig. 2 shows the timing diagram of the signals in this proposed PWM scheme for APFC ac-dc converter. Theree is a triangular ramp with equal rising and falling slopes. This ramp is compared to the feedback signal with an appropriate offset. The resulting pulse width modulation signal is shown below. Note that the delay between consecutive rising and falling edges are T sw. The ramp slope is chosen to be equal to the feedback signal at duty ratio of half. This is a design choice and depends on the nominal duty ratio. Assuming the continuous conduction mode of operation and using the switch set and reset criteria, the following analysis is made [Midya, K Haddad (2000), Midya and Krein (1995)]. During the n th switching cycle, the crossing point of the sign+0.5 current feedback and rising ramp signals causes the switch transition to occur at time t sw = (2n+ +Dr(n))T sw. Therefore, the nominal duty ratio is given by Dn = Dr (n) +Dl (n). Where Dr (n) is the duty ratio provided from the control loop by rising ramp only in the n th cycle and Dl (n) is the duty ratio provided from the control loop by falling ramp in the n th cycle. Figure 2. Timing diagram. The magnitudes of two signals at transition are given by Sign1 (t sw w) = Dr (n) T sw Sign2 (t sw w) = Dl (n) T sw m ramp m ramp Where m ramp = V(pk) ramp/t sw. (slope of ramp). The signal Sign is obtained as the integral of the difference of the I ref and the actual boost inductor current waveform. The gain of the integral is obtained using the equal slope criteria when the reference is the half the input voltage.

4 4. Control Circuit Considerations Average current mode control method is employed to achieve high power factor. The objective of the control is to make the input converter current as sinusoidal as possible and to obtain the proper output voltage regulation Current Loop Compensator The objective of this loop is to track a reference waveform (I ref ) whose frequency is twice the line frequency. This reference signal has a high dv/dt around the zero crossings of the line. Therefore the loop needs gain at frequencies corresponding to the higher order Fourier coefficients needed to recreate the referencee waveform. This implies high bandwidth for the current loop. In this case, a 10 khz bandwidth is considered which is usually adequate for line frequency of 50 Hz to 60 Hz. In order to design a compensator loop properly, the model of the converterr is needed. The transfer function of the exact model of boost PFC is ω.. ω.. ω. ω, 1 (1) Where ω, The simplified current loop transferr function is given by G s V.R SENSE.L.V SE (2) Where VSE is the triangular voltage peak to peak. The current loop error amplifier is shown in Fig. 3 and its transfer function is SR C R C P C Z R C.C CC (3) Figure 3. Current loop error amplifier.

5 4.2 Voltage Loop Compensator: There are some trade-offs inherent in the voltage loop design that are particular to PFC applications. The fundamental requirement of power balance, on the line frequency time scale requires that the voltage loop s bandwidth must be less than the half the line frequency. Otherwise, the voltage loop will distort the line current in order to regulate the output voltage. 10Hz is considered in this case. The proportional integrator is considered which suits for PFC applications. The feedback loop PI compensator is shown in Fig. 4 & its transfer function is given by,. (4) Figure 4. g m (trans-conductance) amplifier configuration. 5. Simulation Results Simulations were carried out on the APFC converter, together with the compensators and two sided PWM. PSIM simulator was employed for the proposed APFC converter considering ideal devices & components. The parameters are reported in Table 1. The schematic entry of 1-phase APFC converter into the simulator is shown in Fig. 5 Table 1. Converter Parameters. 85 V rms 270 V rms (Universal Input voltage) =2.4 mh L boost V 0 = 400 V f s = 1000 khz C 0 = 160 μf 100 W (Output Power)

6 Figure 5. APFC circuit and control simulation block diagram in PSIM. In Fig. 6, the output voltage behavior for input variation from 150 V rms to 220 V rms is reported: a comparison between two sided PWM approach and regular PWM approach reveals that settling time is improved by 1 ms in the two sided PWM scheme compared to regularr PWM scheme. We are continuing research on this issue for further improving the settling time & will be reported later. Note also that the overshoot peak near the input change in novel approach is reducedd by an amount of 10% that of regular PWM technique. Steady state performance is very satisfactory (PF>0.98). 102 ms (a) 103 ms (b) Figure 6. Output volta age behaviors at input voltage change (150 Vrms to 220 Vrms) (a) Two sidedd PWM APFC (b) Regular PWM APFC converter

7 6. Conclusion A two sided PWM in APFC ac-dc converter has been described. Timing diagram of two sided PWM & control circuit considerations have been described. The two sided PWM technique in APFC improves the dynamic response by 1% compared to regular PWM technique. The whole system has been tested by means of simulation using Power-Sim Power Electronics & Drives simulation package. Fast regulated dc voltage on constant power load is observed. References: [1] A Fernandez, J Sebastian, P Villegas, Marta M Hernando, and D G Lamar. Dynamic Limits of a Power-Factor Pre-Regulator. IEEE Transactions: Ind. Appl., vol. 52, no. 1, 2005, [2] M Rathi, N Bhiwapurkar and N Mohan. Dual Voltage Controller Based Power Factor Correction Circuit for Faster Dynamics and Zero Steady State Error. In Proc. 29 th annual IEEE conference: Industrial Electronics Society, 2003, [3] A Prodic, Compensator Design and Stability Assessment For Fast Voltage Loops of Power Factor Correction Rectifiers. IEEE Transactions: Power Electronics, vol. 22, no. 5, 2007, [4] L H Dixon. Closing the Feedback Loop. In Unitrode Power Supply Design Seminar Manual: 1986, C1-1 to C1-7. [5] R B Ridley. A new, Continuous-Time Model for Current-Mode Control. IEEE Transactions: Power Electronics, Vol.6, 1990, [6] Mohan, Undeland, and Robbins. Power Electronics Converters, Applications & Design, John Wiley & sons Publishers, [7] C Zhou, R B Ridley and F C Lee. Design and Analysis of a Hysteretic Boost Power factor Correction Circuit. In Proc. 21 st annual IEEE conference: power electronics specialist conference.1990, [8] X Yang and Z Wang. Research on Quasi-Constant Frequency Hysteresis PWM Current Mode Control. In Proc. International conference on PEDS: 1999, [9] L Rossetto, G Spiazzi, and P Tenti. Control Techniques for Power Factor Correction Converters. In Proc. PEMC: 1994, [10] P Midya, K Haddad. Two Sided Latched Pulse Width Modulation Control. In Proc. 31 st annual IEEE conference: power electronics specialist conference, 2000, [11] Midya P and Krein P T. Closed-Loop Noise Properties of Pulse-Width Modulated Power Converters. In Proc. 26 th annual IEEE conference: Power Electronics Specialists Conference, 1995, [12] H M Suryawanshi, M R Ramteke, K L Thakre and V B Borghate. Unity- Power-Factor Operation of Three-Phase AC-DC Soft Switched Converter Based on Boost Active Clamp Topology in Modular Approach. IEEE Transactions: Power Electronics, Vol.23, No.1, Jan-2008.

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