A Novel Bridgeless Single-Stage Half-Bridge AC/DC Converter

Transcription

1 A Novel Bridgeless Single-Stage Half-Bridge AC/DC Converter Woo-Young Choi 1, Wen-Song Yu, and Jih-Sheng (Jason) Lai Virginia Polytechnic Institute and State University Future Energy Electronics Center 106 Plantation Road, Blacksburg, VA, 24061, USA 1 Abstract This paper proposes a new bridgeless single-stage half-bridge ac-dc converter. The proposed converter integrates the operation of the bridgeless power factor correction (PFC) boost rectifier and the asymmetrical pulse-width modulation (APWM) half-bridge dc-dc converter. The proposed converter provides high power factor and direct power conversion from the line voltage to an isolated dc output voltage without using the fullbridge diode rectifier. Conduction losses are lowered with a simple circuit structure. Switching losses are also reduced by achieving zero-voltage switching (ZVS) of the power switches. The effectiveness of the proposed converter is verified on a 250 W (48 V/5.2 A) experimental prototype. I. INTRODUCTION The research for single-stage ac-dc converters has been an active research topic for power factor correction (PFC) circuits in the power electronics. A number of single-stage PFC ac-dc converters have been introduced in the literature. Among them, discontinuous-conduction-mode (DCM) single-stage PFC acdc converters are widely used for their simple and efficient structures [1]-[8]. Generally, two power stages of the PFC circuit and dc-dc converter are simplified by sharing a common switch [1]-[4] or a pair of switches [5]-[8]. Most single-stage PFC ac-dc converters use single-switch dc-dc converter topologies such as flyback [1], [2] and forward converters [3], [4]. However, the single-stage single-switch acdc converters operate under hard-switching condition. The voltage stresses of switching devices and power conversion efficiency have not been optimized yet. The practical use of the single-stage single-switch ac-dc converters has been limited for low-power applications with power levels lower than 80 W. Single-stage soft-switching ac-dc converters have been developed to improve the performance of single-stage PFC acdc converters [5]-[8]. Single-stage soft-switching ac-dc converters based on the half-bridge converter topology are attractive because they provide low component count and zero-voltage switching (ZVS) operation of the power switches [5], [6]. Similar efforts have been put in optimizing and improving the performance of the converter by using activeclamping techniques [7], [8]. The majority of these development efforts have been focused on reducing switching power losses on the power conversion efficiency. However, so far no single-stage ac-dc converter without using the fullbridge diode rectifier has been reported. The single-stage acdc converters still use the full-bridge diode rectifier, which causes high conduction losses. The full-bridge diode rectifier suffers from significant conduction losses especially at low line voltage. Thus, a bridgeless single-stage ac-dc converter should be studied to reduce conduction losses and component counts. This paper proposes a new bridgeless single-stage halfbridge ac-dc converter. The proposed converter integrates the operation of the bridgeless PFC boost rectifier [9]-[12] and the asymmetrical pulse-width modulation (APWM) half-bridge dc-dc converter [13]. The proposed converter provides high power factor and direct power conversion from the line voltage to an isolated dc output voltage without using the full-bridge diode rectifier. By allowing the boost inductor to operate in DCM, PFC and fast output voltage regulation are performed simultaneously by the APWM control of power switches. Conduction losses are lowered by essentially eliminating the full-bridge diode rectifier. Switching losses are also reduced by achieving zero-voltage switching (ZVS) of the power switches. Thus, the proposed approach not only reduces the number of circuit components, but also makes it possible to increase power efficiency of single-stage PFC ac-dc converter. The performance of the proposed converter is evaluated by the experimental results based on a 250 W (48 V/5.2 A) converter prototype. The proposed converter achieves a high-efficiency of 93 % with almost unity power factor at 90 V rms line voltage. Fig. 1. Circuit diagram of the proposed converter /10/$ IEEE 42

2 Fig. 2. Operating modes of the proposed converter in a positive half-line cycle. II. OPERATION PRINCIPLE Fig. 1 shows a circuit diagram of the proposed converter. The bridgeless PFC boost rectifier consists of the boost inductor L b, dc-link capacitor C d, and switching devices D 1, D 2, S 1, and S 2. D 1 and D 2 are slow-recovery diodes. S 1 and S 2 are MOSFETs with output capacitors C S1 and C S2 (C S = C S1 = C S2 ), respectively. D S1 and D S2 are body diodes of S 1 and S 2, respectively. The APWM half-bridge dc-dc converter consists of the dc-link capacitor C d, S 1 and S 2, blocking capacitor C b, transformer T, output diodes D o1 and D o2, output filter inductor L o, and output capacitor C o. By sharing C d, S 1 and S 2, the proposed converter integrates the operation of the bridgeless PFC boost rectifier and the APWM half-bridge dc-dc converter. S 1 and S 2 are controlled asymmetrically. By allowing the boost inductor to operate in DCM, PFC and fast output voltage regulation are performed simultaneously by the APWM control of power switches. For both positive and negative half-line cycle of v i, the proposed converter has symmetric operation. In the positive half-line cycle, S 1 is controlled with duty ratio D. Then, the conduction times of the switches S 1 and S 2 are DT s and (1 D)T s, respectively. When S 1 is turned on, the input current i i flows through L b, D 1, and S 1. When S 1 is turned off, the input current i i flows through L b, D 1, C d, S 2, and D S2. In the negative half-line cycle, S 2 is controlled with duty ratio D. Then, the conduction times of the switches S 1 and S 2 are (1 D)T s and DT s, respectively. When S 2 is turned on, the input current i i flows through S 1, D 1, and L b. When S 2 is turned off, the input current i i flows through S 1, D S1, C d, D 1, and L b. The transformer T has the magnetizing inductor L m and leakage inductor L lk with the turns ratio of 1 : n. 43

3 Fig. 2 shows the operating modes of the proposed converter during T s for the positive half-line cycle. Only the operation principle for the positive half-line cycle is described in this section. Due to the symmetric operation, the operation principle for the negative half-line cycle is not described here. The capacitors C d and C o are large enough so that the voltages V d and V o are assumed to be constant. v i is considered constant during one switching period T s (= f s ). Mode 1 [t 0, t 1 ]: At t = t 0, S 1 is turned on. The input current i i flows through L b, D 1, and S 1. The boost inductor L b stores energy from the line voltage. The voltage across L m is V d V b. The primary current i p increases as Vd -Vb ip ( t) = ip ( t0 ) + ( t - t 0 ). (1) L The transformer T transfers energy to the output through the output diode D o1. The switch current i S1 is the sum of boost inductor current i Lb and the primary current i p. Mode 2 [t 1, t 2 ]: At t = t 1, S 1 is turned off. As the primary current i p charges C S1 and discharges C S2, the voltage V S2 across S 2 decreases from V d to zero. Since the time interval in this mode is negligible compared to T s, the primary current i p and boost inductor current i Lb are considered to be constant. When the voltage V S2 across S 2 is zero, the primary current i p begins to flow the body diode D S2 of S 2. Mode 3 [t 2, t 3 ]: At t = t 2, S 2 is turned on. ZVS of S 2 is achieved because the voltage V S2 across S 2 is zero. The input current i i flows through L b, D 1, C d, S 2, and D S2. The energy stored in the boost inductor L b is released to the dc-link capacitor C d. The voltage across L m is V b. The primary current i p decreases as Vb ip ( t) = ip ( t2 )- ( t - t 2 ). (2) L The transformer T transfers energy to the output through the output diode D o2. The switch current i S2 is the sum of boost inductor current i Lb and the primary current i p as Mode 4 [t 3, t 4 ]: At t = t 3, the boost inductor current i Lb is zero. From the volt-second balance on the boost inductor L b, we have the following relation as v i DT s m m ( Vd - vi ) DTs =. (3) By simplifying (3), we have the time interval T s during this mode as vi DTs D Ts = (4) V - v ( ). d Mode 5 [t 4, t 5 ]: At t = t 4, S 2 is turned off. As the primary current i p charges C S2 and discharges C S1, the voltage V S1 across S 1 decreases from V d to zero. Since the time interval in this mode is negligible compared to T s, the primary current i p and boost inductor current i Lb are considered to be constant. When the voltage V S1 across S 1 is zero, the primary current i p begins to flow the body diode D S1 of S 1. Mode 6 [t 5, t 6 ]: At t = t 5, the voltage V S1 across S 1 is zero. The primary current i p begins to flow the body diode D S1 of S 1. ZVS of S 1 can be achieved when S 1 is turned on again. In a positive half-line cycle, from the volt-second balance on L m during T s, the voltage V b across blocking capacitor C b is expressed as i V b = DV d. (5) Using (5), from the volt-second balance on L o during T s, we have the relation between the dc-link voltage and the output voltage in a positive half-line cycle as Vo = nd( 1 - D). (6) V d III. EXPERIMENTAL RESULTS A 250 W converter prototype was built and tested under the universal line voltage. The proposed converter has the following parameters as line voltage v i = 90 V rms, output voltage V o = 48 V, switching frequency f s = 50 khz, boost inductor L b = 100 μh, blocking capacitor C b = 1 μf, dc-link capacitor C d = 440 μf, output capacitor C o = 680 μf, magnetizing inductor L m = 100 μh, output filter inductor L o = 30 μh. For switching devices, power switches S 1 = S 2 = 20N60C3, D 1 = D 2 = SFR305PT, and D o1 = D o2 = MBR20100 are used. The controller is implemented by using a single-chip microcontroller, Microchip dspic30f3011. Output voltage is measured by using 10-bit analog-to-digital (A/D) converter in the microcontroller. The circuit design was simulated using PSIM 6.0; the schematic circuit is shown in Fig. 3. Fig. 4 shows the simulation results when the proposed converter supplies 250 W output power. Fig. 4(a) shows the line voltage v i, boost inductor current i Lb, and dc-link voltage V d at v i = 90 V rms. Fig. 4(b) shows the voltage and current waveforms of power switches S 1 and S 2, respectively. Fig. 5 shows the experimental results when the proposed converter supplies 250 W output power. Fig. 5(a) shows the line current i i at v i = 90 V rms. Fig. 5(b) shows the primary current i p and voltage V S1 of the switch S 1 at v i = 90 V rms. The proposed bridgeless single-stage ac-dc converter provides high power factor and direct power conversion from the line voltage to an isolated dc output voltage without the suing full-bridge diode rectifier. Fig. 3. Circuit diagram of the simulation circuit. 44

4 (a) (a) (b) Fig. 4. Simulation results. The proposed converter achieves a high-efficiency of 93 % with almost unity power factor at 90 V rms line voltage. Compared to the previous approaches (single-stage design [7] and two-stage design [10]), the proposed approach increase the power efficiency and reduce component counts by lowering conduction losses and by eliminating the full-bridge diode rectifier in the single-stage PFC ac-dc converters. More detailed efficiency comparison, experimental waveforms and circuit design guideline will be discussed in further work. (b) Fig. 5. Experimental results. The performance of the proposed converter was evaluated by the experimental results based on a 250 W (48 V/5.2 A) converter prototype. The proposed converter achieves a highefficiency of 93 % with almost unity power factor at 90 V rms line voltage. IV. CONCLUSION In this paper, a new bridgeless single-stage half-bridge ac-dc converter has been proposed. As a new bridgeless single-stage PFC ac-dc power conversion scheme, the proposed converter integrates the operation of the bridgeless PFC boost rectifier and the APWM half-bridge dc-dc converter. Without using any full-bridge diode rectifier, the proposed converter achieves high power factor and direct power conversion from the line voltage to an isolated dc output voltage. The proposed converter has the following features for the single-stage PFC ac-dc converter as 1. Low conduction losses by essentially eliminating the fullbridge diode rectifier; 2. Reduced component counts by integrating two power conversion stages; 3. Low switching losses by the ZVS operation of power switches; V. REFERENCES [1] J. Y. Lee, Single-stage AC/DC converter with input current dead-zone control for wide input voltage ranges, IEEE Transactions on Industrial Electronics, Vol. 54, No. 2, pp , Apr [2] S. Luo, W. Qiu, W. Wu, and I. Batarseh, Flyboost power factor correction cell and a new family of single-stage AC/DC converters, IEEE Transactions on Power Electronics, Vol. 20, No. 1, pp , Jan [3] C. Qiao and K. M. Smedley, A topology survey of single-stage power factor corrector with a boost type input current shaper, IEEE Transactions on Power Electronics, Vol. 16, No. 3, pp , May [4] H. E. Tacca, Power factor correction using merged flyback-forward converters, IEEE Transactions on Power Electronics, Vol. 15, No. 4, pp , Jul [5] R. T. Chen, Y. Y. Chen, and Y. R. Yang, Single-stage asymmetrical half-bridge regulator with ripple reduction technique, IEEE Transactions on Power Electronics, Vol. 23, No. 3, pp , May [6] T. Shimizu, K. Wada, and N. Nakamura, A novel single-stage halfbridge AC-DC converter with high power factor, IEEE Transactions on Industrial Electronics, Vol. 48, No. 6, pp , Dec

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