Using SP6652 For a Positive to Negative Buck Boost Converter

Transcription

1 Solved by APPCATON NOTE ANP9 TM Usg SP665 For a Positive to Negative Buck Boost Converter ntroduction The SP665 is an tegrated FET synchronous PWM buck regulator ideal for low put voltage applications. Although most standard circuits will use this device for simple synchronous step down conversion, this device is also capable of performg a buck-boost topology for a positive voltage to negative voltage converter. n this application note we will show how to implement the SP665 the negative buck boost topology as well as simple design steps that are needed for proper component selection. Prciple of Operation The simplified form of a buck boost regulator is shown below Figure 1. The basic prciple of operation relies on the prciple of energy storage the ductor. When the switch S is conductg, diode D becomes reverse biased; thus all of the current goes to ductor which will ramp up learly until switch S is turned off. At this pot the ductor reverses the polarity, thereby forward biasg the diode D and the energy stored the ductor will be transferred to the load as well as the put capacitor C. _ Switch S D - + C + C Figure 1 Page 1

2 One advantage of usg the SP665 is the tegration of the synchronous FET to the device, thus elimatg the need for the free wheelg diode D. This helps reduce the part count as well as crease the efficiency of the overall circuit. Below Figure is the switch configuration of the SP665 showg how the synchronous switch Sync_FET replaces the free wheelg diode D. _ Ma_Fet Sy nc_fet - + C_N + C_OUT Design Considerations Figure 1 D1 1 MBR uH COUT uf OUT(-) R 68.6K RF.1K RZ 1.5K U1 SP665 PGND X 10 SGND PN 9 FB SN 8 COMP SYNC 7 SD MODE 6 RN 10.0 N = 3.3 CN uf CC 0.1uF CN.uF Figure 3 Page

3 Figure 3 shows a typical configuration for a positive to negative voltage converter usg the SP665 cludg all supportg components needed for operation. One thg to note is that the GND of the SP665 is connected to the of the converter. Because of this connection to GND there are some further considerations that will be addressed this application note. Also remember to connect any polarized components the proper orientation as not to damage them sce GND of the circuit on the put is more positive than. Component Selection The next section will deal with proper component selection for this type of application. nductor Selection The duty cycle is calculated as follows. ( Rdson ) + sync D = (1) + + Rdson ) ( Rdson ) ( sync ma Where Rdson sync is the switch resistance of the synchronous FET Rdson ma is the ma switch resistance is the average nductor current is the load current. The average ductor current = () 1 D One thg to notice ab the set of formulae is that the duty cycle sets the amount of. This creates a problem sce the current is not fixed this converter configuration and can significantly vary with the duty cycle. A good assumption the case of the SP665 is to take the maximum current that the ductor could see, which is approximately 1.3A, set by the current limit of the device, and use this number as the startg pot for ductor selection for max. Page 3

4 t is also recommended to use equation 3 for duty cycle calculation as a good startg pot. D = (3) + The ductor can be defed as: D = (4) f Δ By substitutg the duty cycle Equation 1 to the ductor equation 4 you get the followg result: ( + ( Rdsonsync )) = (5) f Δ ( + + ( Rdson ) ( Rdson )) o ut s ync ma The typical choice for Δ is 0 to 40 percent of ( + ) although the larger the ductor value the smaller the put voltage ripple of the converter with the same amount of put ESR. Current ripple can also considerably affect the current limit some devices; this will be discussed further this document. n most designs it is acceptable to use equation 4 for calculatg the ductor value. Formula 5 is just a detailed equation that can be used as well to calculate ductance with switch losses cluded. Output Capacitor selection The desired put capacitor is chosen maly for its ESR characteristics which dictate the amount of put voltage ripple Δ the put of the converter will have. Page 4

5 The followg formula calculates the amount of Equivalent Series Resistance (ESR) needed for a desired put voltage ripple. The ESR needs to be able to susta a ripple current of the ductor peak current sce the load sees a square pulse of current every cycle durg when the ductor discharges. ESR Δ = (6) peak There is also a need for a mimum put capacitance. This will ensure that the entire put voltage ripple is ESR related and not due to voltage drop due to lack of capacitance. nput capacitor selection C D oad = (7) f Δ The put capacitor is selected maly for its ESR characteristics which gives the put capacitor a high value of Root Mean Square (RMS) current ratg. The RMS of the put current is approximated by the followg formula. RMS = D (1 D) (8) 1 D C Device Ratgs and considerations for the SP665 There are several considerations that need to be addressed when choosg an C, One is the maximum voltage under which the C will be expected to operate; two is the current limit; and three is the maximum power dissipation of the device. Due to the C ground beg tied to the put voltage of the system, the maximum voltage that the C sees is: = + max (9) This tends to limit the total voltage range of. Page 5

6 The other consideration is the current limit of the device. n the SP665 the ternal current limit sensed across the PMOS Ma_FET of the device. The current limit has a typical value of 1.3A with the mimum value of 1.A. Durg the design process a the mimum value for current limit needs to be used to assure that the device does not go to current limit before full load is achieved. The peak current seen across the PMOS FET is also the peak ductor current peak which can be determed as follows: peak Δ = + (10) This translates to peak Δ = + + (11) Because has a duty cycle relationship to -- makg the effective peak current the ductor equal to + plus the peak ripple -- there are times that this part will not be able to deliver the full put current of 1A as listed the part description over the whole possible range of put and put voltages. The followg graph gives put current verses duty cycle with some compensation for switch losses which affect the duty cycle. Max put current at 3.3 vs Current Series1 Figure 4 t might also be noted that because the current limit is fixed, it might be advantageous to use a smaller ductor value to get higher ripple current to limit the current designs where the needed amount of put current is small. This will sacrifice some total efficiency of the system due to larger peak currents, but it Page 6

7 will limit the total amount of put current to a more reasonable level durg fault conditions. The last consideration is the total power dissipation of the C. There are two components to the total power P total dissipation of the C. The first component is the power dissipated by the control logic of the c. The second component is the power dissipation of the actual switches. The followg formula combes the two components for total power dissipation: P total ( Rdson D) + ( Rdson D) = + 1 c ma sync (1) For the SP665 application Rdson ma and Rdson sync are both equal. The P total is an important first check to see if the Sp665 can handle the total power dissipation over a wide temperature range with causg the C to shut down due to the Thermal shutdown limit. t is important to note that this is only the first step and the temperature of the C needs to be taken to verify the theoretical values sce there can be a large variation thermal performance due to lay and airflow conditions. Efficiency The efficiency of the system can be given by: P η = 100 (13) P The efficiency of the converter switches only is given by: Rdson ma η converter _ switches = (14) + oad Rdsonsync One thg to note that this negative buck boost configuration, the duty cycle will have an effect on the efficiency of the converter more so than a buck configuration. Another major loss the circuit that contributes to the total efficiency of the system is the ductor resistance loss. n the end it is always better to measure the put and put power to get the best results for efficiency. Page 7

8 Design Example The followg is a design example with the SP665 for a 3.3 to mA regulator. A good startg pot is to take Δ to be.3 of 1.8 D = From Equation mA = 1.35 D=.35 From Equation =769mA Δ =. 4 Δ = 30mA The Rdson of the FETs was taken from the data sheet. D = (4) f Δ = 3.58 µh calculated, 4.µH was chosen rated at 1.5A Output Capacitor ESR Calculation Mimum Capacitance.0 ESR = From Equation A ESR is 36mΩ C.5A.35 = 1.4MHz. 0 From Equation 7 C =6.5µF Page 8

9 Sce you need ab 10-uF to get the proper ESR, the mimum capacitance requirement will be fulfilled due to ESR requirements. The nput capacitor RMS current ratg 500mA RMS =.35 (1.35) From Equation RMS=.370 A Total power dissipation of the C (.769 A.6Ω.35) + (.769.6Ω ( 1.35)) P total = 1mA A From Equation 1 P total =.355W PCB ay Special care needs to be taken when layg the Prted Circuit Board for the SP665. The put and put capacitors need to be as close as possible to the converter ps. There are also two grounds present on this C. For the positive to negative converter, these grounds were tied together and the put capacitor was placed right at the put ps of the C to GND to get best performance. f no special care is taken with lay noise, jitter can be present on the switch node with very little put current drawn by the load. Test Data for above circuit design. Efficiency of the Buck boost converter for 3.3 to 1.8 Page 9

10 Efficiency at 3.3 and 1.8 Efficiency Efficiency Typical wave forms for the SP665 Channel 1 Switch node Channel is nductor Current was 500mA Current settg is 500mA/Div Page 10

11 Channel 1 Switch node Channel is nductor Current was 50mA Current settg is 00mA/Div Startup characteristics of the SP665 Page 11

12 Channel ripple Channel 1 Switch Node 500mA Page 1

13 For further assistance: WWW Support page: ive Technical Chat: Sipex Application Notes: Solved by TM Sipex Corporation Headquarters and Sales Office 33 Sh Hillview Drive Milpitas, CA95035 tel: (408) fax: (408) Sipex Corporation reserves the right to make changes to any products described here. Sipex does not assume any liability arisg of the application or use of any product or circuit described here; neither does it convey any license under its patent rights nor the rights of others. Page 13