Matched FET Cascode Pair: Design of Non-Linear Circuits without DC Biasing Supply

Transcription

1 Matched FET Cascode air: Design of Non-Lear Circuits with DC Biasg Supply Rohan Sehgal, Nihit Bajaj and Raj Senani Abstract - In this brief, a novel low voltage basic cell, coed as the Matched FET Cascode air, has been proposed. The approach exploits the non-lear characteristics of transistors the triode region. The cell requires complimentary put signals, with the gate voltages of the FETs actg as the control signals. Several non-lear circuits designed with the help of DC biasg, are described and a set of measured and simulation results of both - the JFET and MOSFET implementations, are shown to demonstrate the design flexibility of the approach. Index Terms-Analog Circuits, Circuit Topology, FET Circuits, Nonlear Circuits I. INTRODUCTION Durg the last few years, designers have strived for circuit architectures which employ reduced power supply voltages. This trend has been supported by device downscalg, which implies a reduction of the chip area and thus results higher packg density tegrated circuits. The reduction of power supply voltage offers an additional advantage, decrease of power consumption tegrated circuits. This is an important issue not only battery-operated circuits, but also very large-scale tegrated circuits, where heat dissipation is not a negligible factor anymore. Circuit operation at reduced voltages is a common practice adopted to reduce power consumption. However, at low voltages, the circuit performance degrades along with bandwidth and voltage swgs. This generates a need for adoption of alternative design techniques to suit the low voltage environments. All these factors have spurred on a new direction analog design, namely low voltage circuit design [1]. Several circuit techniques and architectures have been proposed to reduce the supply voltage requirements analog and mixed-signal circuits, among them: foldg, subthreshold operation of mosfets, bulk-driven, level shifters, floatg gate techniques, flipped voltage followers and current mode processg. The use of these techniques along with aggressive scalg, have led to the reduction of supply voltages to 0.5 []. The holy grail of low voltage analog circuit design is to realize circuits which can/could operate with any DC biasg supply. Such circuits should be able to derive their biasg requirements solely from the put supply. A few such circuits have been troduced by Ciubotaru [3-8]. Buildg upon these foundations, the authors take a significant step towards the design of such circuits, by troducg the Matched FET Cascode pair. The FET cascode pair is a novel two-transistor block, designed for operation with sub-1 put voltage signals. It has been employed to design several non-lear circuits with usg DC Biasg supply, as discussed the next few sections of the brief. II. DESIGN CONSIDERATIONS There are several difficulties that restrict the design and application of circuits with DC biasg LSI circuit design. Such circuits, apart from beg very difficult to design, face serious performance issues. Firstly, there is no amplification possible, as the only power provided to the circuit origates from the put signal itself. Also the dynamic range of the circuit is limited by the put voltage swg. As the biasg for all the transistors is derived from the put voltage, a large put swg might change the region of operation of a particular transistor, alterg the behavior of the entire circuit. This restricts the put signal range, thereby reducg the doma of non-lear circuits which can be effectively realized by such circuits. III. MATCHED FET CASCODE AIR The proposed analog cell is shown fig. 1. It consists of a matched pair of symmetrical n-channel JFETs connected a cascode. is kept small, so that the transistors work triode region. Applyg the current equations- I = I A D1 DSS 1 + B + + ID1 = IDSS 1 Now, I = I I D1 D Fig. 1 Matched FET Cascode air Topology

2 ( ) ( ) = k A + B + A B (1) I where k = DSS In the above circuit, A and B are referred to as control puts. By manipulatg the values at these puts, several non-lear circuits have been designed. The square-law circuit [3] can be easily deduced from the matched cascode JFET pair, by makg A = B = i n eqn. (1). Assumg I 0, + + = 0 Sce is appreciably < this configuration, << is a reasonable approximation, which leads to the followg simplification () (3) Similarly, by puttg A = B = OUT, an vertg square-law can be obtaed [5], havg put as By makg A = B =, another important function can be derived from this structure absolute-value circuit [4], shown fig.. On replacg these values (), + = 0 or = -1/ (5) (4) effect. It is known that for a p-n junction to be effectively forward biased, the bias voltage across the junction should exceed a particular value, called the cut- voltage. This is because the current is negligibly small for voltage smaller than cut voltage, 0.5 case of Si, owg to the exponential relationship between voltage and current [9]. Exploitg this effect, the cascode pair usg MOSFET can be made to work by simply groundg the body termals, provided the put swg is limited to ±0.5. Though the above configuration is simple and easy to implement, its performance is quite error-prone and the put swg has been effectively halved. Two more blocks are discussed below, which use extra circuitry to resolve these issues. The first MOSFET implementation is shown fig 3. The body connection is switched through usg somethg similar to pass-transistor logic. In the circuit shown, all transistors used are n-channel depletion MOSFETs, with M1 and M havg TH = -1 and M3, M4, M5 and M6 havg zero threshold voltage. As switches from positive to negative, the dra and source termals of M1 and M terchange. M3, M4, M5 and M6 beg zero threshold devices, go to cutoff and triode regions accordgly, resultg substrate remag contact with the source termal through the put swg. I. MATCHED FET CASCODE AIR Despite the similarity between JFETs and MOSFETs, the same topology when implemented n-channel depletion type MOSFETs, gives a much poorer performance due to the body Fig. 3 MOSFET Implementation of Cascode air (1) Zero-threshold devices can be fabricated by addg an extra maskg and ion-implantation step to the basic NMOS process, so that even at G = 0, a channel between the source and the dra exists. In this case, to deplete the channel, negative voltage has to be applied. MOSFETs with zero-threshold voltage can also be obtaed by usg two-put FGMOS transistors [10]. Fig. Absolute alue Circuit [4]

3 = (9) N It may be noted that as the number of puts crease, the approximation made becomes less reliable and the error creases. Fig. 4 MOSFET Implementation of Cascode air () Another implementation can be derived from the fact that for most circuits comprisg of n-channel MOSFETs, the body termals are connected to the most negative supply available the circuit. This ensures that the source-body junction remas reverse biased condition through the operation of the MOSFET. However, this cannot be accomplished the proposed cell as ranges from -1 to +1. To overcome this problem, an vertg modulus circuit, described the previous section, is used to generate -, which acts as the most negative pot and is, thus, used to bias the substrate termals of all the MOSFETs. As shown fig. 4, the lower MOSFET is replaced by two identical MOSFETs connected parallel, so as to obta a unity transfer ratio. Any external voltage supply can be avoided by usg zero-threshold devices. Fig. 5 Mean Square Circuit (b) Difference-of-Squares Circuit A difference-of-squares circuit basically computes the difference between the square of two voltage signals. It can be used for various applications, like R.M.S.-to-D.C. conversion [11], etc. The circuit, shown fig. 6, uses two JFET squarers of opposite polarity.. DESIGN OF NONLINEAR CIRCUITS The FET Cascode pair can be used as a fundamental buildg block analog circuit design. Several non-lear functions have been realized by Ciubotaru [3-8], such as squarer, cuber, four-quadrant multiplier, etc. It can be seen that all these circuits are based on the proposed FET cascode pair. In this section, circuits realizg a few more common non-lear functions are discussed (a) Mean Square Circuit A two-put mean square circuit, shown fig. 5, has been designed by employg two matched FET cascode pairs, Q1-Q and Q3-Q4. It can be shown that both the pairs are operatg as squarers. As shown fig. 5 - I d1 + I d3 = I d + I d4 (6) On puttg their respective expressions and simplifyg, the put voltage is obtaed as 4 = + ( 1 + ) (7) If 1 + >>, then 1 = + 4 (8) For an N-put mean square circuit, (8) can be generalized as - Fig. 6 Difference of Squares Circuit It can be seen that, ( 1 )/4 (10) ( 1 + )( 1 - )/4 (11) If 1 = c + d and = c - d, then = c d / (1) where c = Common voltage = ( 1 + )/ d = Differential voltage = ( 1 - )/ (c) oltage Controlled Resistor Fig. 7 shows a voltage controllable resistor, constructed

4 Fig. 7 Lear Resistor usg two matched JFET cascode pairs, Q1-Q and Q3-Q4. For pair Q1-Q, the control puts are A = B = C and for Q3-Q4, the control puts are A = + C ; B = - C Followg a similar procedure for analysis, the current I is obtaed as I = K ( C - ) (13) and R = /I = 1/[K( C - )] (14) The equation (13) shows that the put voltage, and put current, I have a lear relationship and the equivalent put resistance is dependent on C, the control voltage and, the pch off voltage of the transistors. Hence, it can be used as a voltage controllable one-port active resistor. I. FUNCTION GENERATION USING MACLAURIN S SERIES In [3,5-6], square-law, cube-law and 4 th -power law have been realized usg the cascode pair. Usg a combation of these circuits, circuits realizg other functions can also be designed with the help of Maclaur Series. The Maclaur series expansion for exponential circuits is given as [11] x e 3 4 x x x = 1 + x for < x < (15) 6 4 The exponential law can be suitably implemented with the transfer function as k TH = k 1 TH e 1 where k 1 and k are constants. (16) Usg Maclaur series expansion, the above equation can be written as 3 k 1 k 1 k = k 1 TH TH TH 6 TH ( k ) ( k ) (17) Or = k 1 ( k ) (18) TH 6 TH Sce is less than 1, a reasonably accurate value for can be obtaed by considerg only the first four terms, that is, till n=3. For k 1 =k =1, = T and considerg the first few series terms, an error of only 1.89% is obtaed. Equation (18) may be obtaed by combg the square-law and cube-law blocks along with the put voltage. In fact, if T can be provided the circuit, a purely exponential relationship between put-put voltages can be obtaed! Similarly, other functions such as hyperbolic, susoidal, etc can be realized by combg the square law and cube law puts. A possible way of summg these blocks is to use a multiple-put floatg gate MOSFET. All the voltages provided to the multiple gates of the MOSFET, are capacitively coupled ratios proportional to the dimensions of the multiple gates. The summed put can be obtaed by usg a differential amplifier. II. RESULTS The JFET circuits described the previous sections were verified by usg BF45C n-channel JFETs. The measured parameters of the JFETs were IDSS = 1mA and =-. The DC characteristics were measured and verified usg a load RL = 10KΩ. The MOSFET implementation of the previously discussed circuits was verified with the help of SICE simulations carried on 1.5 μm CMOS technology. The DC transfer characteristics for some of the circuits have been given below. III. CONCLUSION A novel two-transistor analog cell, Matched FET Cascode air, has been proposed for low voltage operation. Usg this Fig. 8 MOSFET Squarer (1) Ideal Response () Circuit Response

5 cell as the basic buildg block, a number of non-lear analog circuits have been designed, which are essentially voltage-mode nature and work well for sub-1 volt range. These circuits have a significant advantage that they do not require any DC biasg supply; the biasg for all the FETs used beg derived from the put signal voltage itself. Usg the nth power circuits based on the analog cell, a number of functions frequently used analog computg can be generated through Maclaur s series expansion. The JFET and MOSFET Implementations of proposed circuits have been verified usg BF45C n-channel JFETs and through SICE simulations on 1.5μm CMOS technology, respectively. REFERENCES [1] S. Yan and E. Sanchez Sencio, Low oltage Analog circuit Design Techniques: A Tutorial, IEICE Transactions on Fundamentals, vol E83-A, February, 000 []. Kget, S. Chatterjee and Y. Tsividis, Ultra-Low oltage Analog Design Techniques for Nanoscale CMOS Technologies, roc. EDSSC, pp. 9-14, December 005 [3] A.A. Ciubotaru, Square-law circuit usg junction field-effect transistors, Electronics Letters, 1997, ol. 33, No. 7, pp [4], Absolute-alue Circuit Usg Junction Field-Effect Transistors, IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal rocessg, ol. 50, No. 8, Aug 003, pp [5], Cube-law circuit usg junction field-effect transistors, Electronics Letters, 1998, ol. 34, No. 1, pp [6], 4th power-law circuits usg junction field-effect transistors, Electronics Letters, 1999, ol. 35, No. 6, pp [7], 5 th power-law circuits usg junction field-effect transistors, Electronics Letters, 000, ol. 36, No. 17, pp [8], Four-quadrant multiplier usg junction field effect transistors, Electronics Letters, 1997, ol. 33, No. 15, pp [9] A.S. Sedra and K.C. Smith, Microelectronic Cir cuits. New York: Oxford University ress, 004 [10] J. Ramirez-Angulo, S.C. Choi, and G.G. Altamirano, Low voltage Circuit Buildg blocks usg Multiple Input Floatg Gate Transistors, IEEE Trans. on Circuits and Systems-I, vol. 4, pp November [11] B. Gilbert, Novel Technique for R.M.S.-D.C. Conversion based on Difference of Squares, Electronics Letters, 1975, ol. 11, No. 8, pp [1] E. Kreyszig, Advanced Engeerg Mathematics. New York: John Wiley & sons, m 00m 0-00m -400m -800m -600m -400m -00m 0 00m 400m 600m 800m (J:d) - (M:d) _1 Fig. 10 MOSFET Difference of Squares Circuit Fig. 11 MOSFET Lear Resistor 50m 00m Fig. 1 MOSFET Exponential Law Circuit (1) Ideal Response () Circuit Response 150m 100m 50m 0-800m -600m -400m -00m 0 00m 400m 600m 800m (R:) _1 Fig. 9 MOSFET Mean Square Circuit