3 ppm Ultra Wide Range Curvature Compensated Bandgap Reference

Transcription

1 1 3 ppm Ultra Wide Range Curvature Compensated Bandgap Reference Xiangyong Zhou Abstract In this report a current mode bandgap with a temperature coefficient of 3 ppm for the range from -117 C to 144 C is presented. 2nd order curvature compensation is used by using a third BJT with a temperature constant current and a second error amplifier to get a nonlinear temperature coefficient current in extra to enhance the accuracy. The required minimum supply voltage is 1.3V for 3ppm and 1.2V for 10ppm TC. The circuit has a line regulation of 0.86mV/V, PSRR of -57dB at 100Hz and -56dB at 1kHz. The bandgap core dissipates 22uA current and the error amplifier dissipates 3uA each. The process used is tsmc 0.18µm. The chip area is estimated as 280 µm 260 µm. Process variation and mismatch as well as amplifier offset voltage effects are simulated. A resistor trimming circuit of 4 bits is made to compensate for the variation and mismatch to as much as ±5%. I. INTRODUCTION Temperature independent reference voltage are in need in many circuit applications such as LDO reference voltage, ADC reference voltage, and memories. To achieve a temperature independent voltage, usually a proportional-to-absolutetemperature (PTAT) voltage and a complementary-to-absolutetemperature (CTAT) voltage are summed with weighting factors to cancel their temperature coefficient (TC) so that to get a first order temperature independent voltage reference. As the Vbe voltage has less variation than the threshold voltage and mobility of MOSFETs BJT based voltage references are more popular than those based on MOSFET Vgs voltages. However standard CMOS only have access to the lateral pnp BJT with the collector fixed to the P-substrate as a tradeoff. Bipolar Junction Transistors (BJT) are used to generate the PTAT voltage by using the Vbe as PTAT voltage and Vbe as CTAT voltage. An error amplifier is often used to force two voltages equal as in the following figure. If a more flexible output voltage is required, then current mode bandgap reference can be used which consists of a PTAT current and a CTAT current. Two MOSFET operating in subthreshold can provide similar characteristics by using two Vgs but with more variation. The weighted sum of PTAT and CTAT current is a temperature independent current which goes through a resistor to be converted back to voltage. However, the limit for the first order cancellation is typically around 20ppm to 100ppm. (author?) [5] To achieve better temperature coefficient, higher order cancellation techniques are needed. II. BACKGROUND AND PREVIOUS WORK For the traditional voltage mode bandgap in Figure 1, V REF = V BE + V BE Figure 1. Figure 2. Conventional Voltage Mode Bandgap Conventional Current Mode Bandgap The MOSFETs have the same sizing so that they are forced to have the same current. The polarity of the error amplifier is chosen so that the right hand negative feedback loop has a larger gain than the right hand positive feedback loop. LG = A amp g m,p MOS (R O,P MOS (R 1 + g m,q2 )) g m,q1 LG + = A amp g m,p MOS (R O,P MOS (R 2 +g m,q1 )) R 2 + g m,q1 Since g m,q1, g m,q2 R O,P MOS, R 1, R 2, it s easy to know LG DC,Negative > LG DC,positive.

2 2 For the traditional current mode bandgap in Figure 2, I REF = V BE + V BE R1 R2 The MOSFETs have the same sizing so that they are forced to have the same current. The polarity of the error amplifier is chosen so that the left hand negative feedback loop has a larger gain than the right hand positive feedback loop. LG = A amp g m,p MOS (R O,P MOS R 3 (R 1 + g m,q2 )) LG + = A amp g m,p MOS (R O,P MOS R 2 g m,q1 ) Since g m,q1, g m,q2 R O,P MOS, R 1, R 2, it s easy to know LG DC,Negative > LG DC,positive. Many higher order cancellation techniques are developed to achieve better cancellation, such as quadratic temperature cancellation, exponential temperature cancellation, piecewise linear curvature correction. Among these techniques, a 2nd order curvature cancellation by a third BJT with a first order temperature constant current is often used. This technique requires one additional BJT branch and one additional error amplifier, and the resultant temperature coefficient can be as low as around 2ppm. In (author?) [2] even a fourth BJT is used to further extend the compensation range. However, no significant improvement of accuracy can be seen from this work as the TC is 3.9 ppm in the best case. The bandgap uses cascode structure to improve PSRR but it also limits the minimum supply voltage. In (author?) [1] MOSFET ratio is used to cancel the two BJT temperature coefficient. The output node implements a super source follower which can even drive resistive load. However, only first order cancellation accuracy can be acheived using this structure and MOSFET mismatch is also more difficult to control than resistor mismatch which can be trimmed easily using binary weighted resistor string with MOSFET switches. III. PROPOSED CIRCUIT STRUCTURE Figure 4. Error Amplifier Schematic Error Amplifier 1, BJT Q1, Q2, Resistor R1, and MOSFET M1, M2, M3, M4 make a PTAT current generator whereas Resistor R2 and MOSFET M6, M7 make a CTAT current generator. Hence the total current through BJT Q3 is a temperature constant current with a weighted sum of the PTAT and CTAT current. The error correction current through R3 is the 2nd order compensation current. The overall output current through R4 is then I OUT = I P T AT + I CT AT I 2ndOrder which is a 2nd order temperature independent current. This current is then converted to a temperature independent voltage by R4. For an analysis of the 2nd order cancellation, the following equations are used. V BE,Q1 = V G0 (1 T T r ) + V BE0 ( T T r ) (n 1)( K bt q for V BE wth a PTAT current and V BE,Q3 = V G0 (1 T T r ) + V BE0 ( T T r ) n( K bt q for V BE with constant current. Hence ) ln( T T r ) ) ln( T T r ) V BE,Q1 V BE,Q3 = V T ln( T T r ) = V NL Figure 3. Proposed Bandgap Reference The proposed bandgap reference uses only three BJTs to save power while also make the design complexity lower. Self- Cascode structure is used in the bandgap core circuit to save supply voltage headroom. The error amplifier also uses selfcascode structure to enhence DC gain while keeping supply voltage low. the nonlinear voltage can be used to cancel the 2nd order curvature difference. The overall output voltage is then V REF = V BE R4 R1 + V BE,Q1 R4 R2 V NL R4 R3 IV. DESIGN PROCEDURE AND COMPONENT SIZING 1) To determine proper current of the left two BJTs, ideal VCCS and ideal OpAmp (VCVS) are used to get the temperature coefficients of the Vbe, Vbe and I P T AT through the BJTs.

3 3 Component Value/Sizing R1 30kΩ R kΩ R3 97.1kΩ R4 125kΩ M1,M3,M7,M8,M9,M12,M13 80µm / 12µm M2,M4,M6,M10,M11,M14,M15 230µm / 6µm Q1 1 Q2 20 Q3 2 Table I BANDGAP CORE SIZING The wide temperature range makes the circuit suitable for even extreme cases like space exploration, continental shelf exploration or some weaponary application. Component Value/Sizing R1 30kΩ C1 300fF M1 12µm / 2µm M2,M3 6µm / 2µm M4,M5 3µm / 2µm M6 30µm / 2µm M7 15µm / 2µm M8 150µm / 2µm M9 75µm / 2µm Table II ERROR AMPLIFIER SIZING Figure 5. 3 ppm Output Voltage 2) I CT AT is obtained by the formula I CT AT = V be R2. R1 and R2 are chosen so as to compensate the TC to the first order. 3) I P T AT and I CT AT are summed to get I Const flowing through Q3. V NL is obtained as V NL = V be,q1 V be,q3 and I NL is then defined as I NL = V NL R3. 4) TCs of I CT AT and I NL are compared and R3 is chosen to compensate the TCs of the two currents to the second order. 5) Do optimization in cadence on R2 and R3 to get the minimum voltage variation. 6) Set R OUT to a proper value so that V OUT equal the average value of V be,q1 to get a minimum V DS variation. 7) PMOS sizes are chosen based on I CT AT, I P T AT and I Const. 8) Design the error amplifier to have sufficient gain for good PSRR. As tsmc 0.18µm technology exhibts short channel effects, square law calculatioin cannot be used in actual BJT and MOSFET sizing. Iterations have to be done to optimize the circuit performance. But the above analysis can still serve as a guideline to fix the sizes of transistors. Table I shows the value of the resistors and sizes of the MOSFET transistors of the bandgap core circuit. Table II shows the value of the resistors and sizes of the MOSFET transistors of the error amplifier. V. SIMULATION RESULTS Figure 5 shows the output voltage of the bandgap reference vs. temperature. A temperature coefficient as low as 3 ppm is acheived over the temperature range from -117 C to 144 C. The absolute voltage variation of the nominal case is approximately only 1mV, sufficient for most applications. As shown in Figure 6, the minimum supply voltage required for this bandgap is only 1.3V and the output voltage is 820mV. A line regulation of 0.86mV/V is acheived. Figure 6. Supply Voltage Requirement The output noise of the BGR is shown in Figure 7. The total integrated output noise is 0.9mV. The layout of the bandgap is shown in Figure 8. Due to the lack of BJT technology file, the layout is only for estimating the chip area. In the bandgap the PMOS and resistors occupy an area of 280µm 260 µm. The power supply rejection of the bandgap reference is shown in Figure 9. The PSR at 100Hz is -57dB and at 1kHz is -56dB. The main contributor of the PSR is the error amplifier gain. The frequency response of the error amplifier is also shown in Figure 10 for a comparison. Table III gives a comparison of this bandgap reference with some other published works. It can be seen that the

4 4 Parameters This Work Becker_Gomez [1] P.K.T Mok [7] De Vita et al. [3] De Vita et al. [4] Technolgy 0.18µm CMOS 0.18µm CMOS 0.6µm CMOS 0.35µm CMOS 0.35µm CMOS Supply Voltage 1.3V~4V 1.1V~1.8V 0.98V~1.5V 0.9V~4V 1.5V~4.3V Current Dissipation 28uA <14uA <18uA 0.055uA 0.11uA Output Voltage 820mV 1.012V 603mV 891mV 670mV TC (ppm/ C) Hz -56dB -75dB -44dB -59dB -47dB Table III COMPARISON TO PUBLISHED VOLTAGE REFERENCES Figure 7. Bandgap Output Noise Figure 9. Power Supply Rejection Figure 10. Error Amplifier Frequency Response performance of this bandgap reference is comparable with these published works. Figure 8. Bandgap Chip Area Estimation VI. PROCESS VARIATION AND RESISTOR TRIMMING Although the resistors in the circuit exhibits process variation which can make the actual circuit inaccurate when fabricated, resistor trimming can still be done after fabrication to compensate for resistor variation and mismatches. Assuming a process variation of 10%, Figure 11 shows that global process variation makes the worst case TC of 9 ppm, which is often

5 5 within the tolerance. However a mismatch between different resistors of 5% can make the TC as bad as 64 ppm as shown in Figure 12, which can be untolerable. As a result, a trimming circuit with 4 bits input to cover a range of 5% compensation is used to make the target resistor approach its nominal value to within 0.3% as in Figure 13. The trimming is only used for two resistors R 1 and R 2 for mismatch compensation, which are two most sensitive resistors. The variation of R 1 and R 2 is 5% by using trimming as shown in Table IV. Resistor R 1 R 2 Trimming Range 163KΩ ~ 178KΩ 28.67KΩ ~ 31.31KΩ Table IV RESISTOR TRIMMING RANGE Figure 13. Resistor Trimming The effect of error amplifier input offset as large as 10mV is also simulated as shown in Figure 14 and Figure 15. The relative variation is still within tolerance but the absolute value can exhibit significant change. As a consequence, resistor trimming has to be used for the output resistor or for the following circuit stages that uses this bandgap output. Figure 14. Input Offset Voltage Effects of Error Amplifier 1 Figure 11. Resistor Global Variation Figure 15. Input Offset Voltage Effects of Error Amplifier 2 Figure 12. Resistor Mismatch CONCLUSION A bandgap reference of Vref 820mV with TC of 3ppm over -117 C to 144 C is presented. The circuit uses tsmc 0.18µm technology and can virtually be fabricated using any standard CMOS technology as it uses only substrate PNP BJTs as reference generators. The process variations and mismatches

6 6 of resistors are compensated using trimming circuitry. Error Amplifier input offset effects are shown to affect the relative voltage variation only negligably but induces DC offset at the output voltage. Trimming of the output resistor is required if the following stage needs an absolute voltage reference. The minimum supply voltage required is 1.3V and the circuit dissipates 28uA current. The chip area is estimated as 280 µm 260 µm. REFERENCES [1] Adriana Becker-Gomez et al. "A Low Supply-Voltage CMOS Sub-Bandgap Reference". IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, July [2] Charalambos M. Andreou et al. "A Novel Wide- Temperature-Range, 3.9 ppm/ C CMOS Bandgap Reference Circuit". IEEE JOURNAL OF SOLID-STATE CIRCUITS, February [3] G. De Vita et al. "An Ultra-low Power Temperature Compensated Voltage Reference Generator". Procedings IEEE Custom Integrated Circuits Conference, pages , [4] G. De Vita et al. "a Sub-1-v, 10 ppm/ C, Nanopower Voltage Reference Generator". IEEE JOURNAL OF SOLID- STATE CIRCUITS, pages , [5] Jianghua Chen et al. "A Curvature Compensated CMOS Bandgap Voltage Reference for High Precision Applications". 7th International Conference on ASIC Procedings, October [6] Luca Magnelli et al. "A 2.6nW, 0.45V Temperature- Compensated Subthreshold CMOS Voltage Reference". IEEE JOURNAL OF SOLID-STATE CIRCUITS, February [7] P.K.T Mok et al. "A sub-1v 15 ppm/ C CMOS Bandgap Voltage Reference Without Requiring Low Shreshold Voltage Devices". IEEE JOURNAL OF SOLID-STATE CIR- CUITS, April 2002.