Beta Multiplier and Bandgap Reference Design

Transcription

1 ECE 4430 Project -1 Beta Multiplier and Bandgap Reference Design Aneesh PravinKulkarni Fall 2014 I have neither given nor received any unauthorized assistance on this project

2 Beta Multiplier - Design Procedure Given: V ref = 1.5V, I ref = 20uA, TSMC 0.18um process, VDD = 2.5V If we use the usual cascodetopology and take Vref= VGS1, then even if we assume zero overdrive, we get VDD min = V thn + V thp + V ref = = 2.25 V. This value is quite high as compared to the nominal value of VDD that is 2.5V. Hence we take Vreffrom the gate of the upper NMOS, that is V ref = V GS1 + V GS2. Also, let V GS1 = V GS2 = V GS, then V GS = V ref /2 = 0.75V. Now V GS = 0.75V and I D = 20uA gives (W/L) 1 = On plotting the ID v/s VDS characteristics we find that actually the required (W/L) is If we take L 1 = 2*L min = 0.36 um, then W 1 = 0.50 um. In order to reduce the power consumption, we make the size of the upper left PMOS K times that of the upper right PMOS. Hence the current in the right branch is 1/K times that in the left branch. The size of the two bottom NMOS s is the same, but difference in the currents causes a difference in their VGS which is dropped across R. R = 2*(K-sqrt(K))/(Beta1(VGS-Vthn)). Putting values, we get R = kohms. This is tuned further in simulations. The W/L ratios of the MOS transistors are made large to reduce VDD min. At the same time, the L of each of these transistors should be large to reduce the sensitivity to VDD. For the startup, both transistors are long so as to reduce the current drawn by the startup, as well as to increase VDD max. Finally, TCR is chosen from Baker Table 4.1 so as to minimize sensitivity to temperature. The best choice is TCR = 3800ppm.

3 Beta Multiplier Circuit Diagram

4 Beta Multiplier Temperature Sweep and Temperature Coefficient Temperature Sweep from -20 to 100 C: Vrefchanges by 70mV over 120C Irefchanges by 4uA over 120C Temperature Coefficient: TC(Vref) = 380 ppm/c TC(Iref) = 680 ppm/c

5 Beta Multiplier Supply Sweep and Supply Sensitivity VDD min = 2.0V, VDD max = 4.5V Sensitivity to VDD: S(Vref, VDD) = 800ppm at 2.5V S(Iref, VDD) = 3640 ppm

6 Beta Multiplier Start up delay and PSRR Pulse of 2.5V applied to VDD at 0 sec. Observed start up delay = 0.8s For frequency sweep from 1 Hz to 100 MHz: Best PSRR = dB (At low frequencies upto 500Hz) Worst PSRR = -3.7 db (At 100 MHz)

7 Beta Multiplier Summary Parameter Target Actual (Simulated Value) Supply (V) Vref (V) Max Supply Sensitivity (ppm) within ±10% of VDD Max Temp Sensitivity ppm/C = 9980ppm Max Power consumption (uw) Iref (ua) Iref(uA) with VTHn= 10% and VTHp= 10% , Iref(uA) with R= 10% around nominal value Iref(uA) with VDD = 10% around nominal value Vref(mV) with VTHn= 10% and DVTHp= 10% - -78, Vref(mV) with R= 10% around nominal value - 66 Vref(mV) with VDD = 10% around nominal value - 1 Min/Max Supply Voltage that the circuit is still working - 2.0, 4.45 TCIref(ppm/C) and TCVref(ppm/C) - 680, 380 Resistor Value (Ohm) and TCR1-93.6k, 3800ppm/C

8 Bandgap Reference- Design Procedure Given: V ref = 1.5V, I ref = 20uA, TSMC 0.18um process, VDD = 2.5V If we use the usual cascodetopology, the value of Vrefis fixed to around 1.2 V. Therefore, we modify the topology to include an extra resistor branch to generate PTAT + CTAT current, which is then mirrored and passed through a resistor (N*R). Since the value of N is variable, we have control over Vref. In order to reduce power consumption, we make size of M3T and M4T equal to 1/P times size of M1. Let P = 10. So the current through M3T and M4T is only 2uA. For this topology, the current through M3T and M4T is I = {n*v T *ln(k)/r} + V D /(L*R). And, I ref = P*I and V ref = N*R*I ref Using above equations, and taking K =8, the value of L which gives dvref/dt= 0 is L = Substituting this value in the expression for I gives R = kohms Now, N = V ref /(R*I ref ) gives N = 12.5 Hence the calculated values of resistors are R = kohms; LR = kohms; NR = kohms. These values are tuned in simulations to get TC(Vref) = 0. The W/L ratios of the MOS transistors are made large to reduce VDD min. At the same time, the L of each of these transistors should be large to reduce the sensitivity to VDD. For the startup, both transistors are long so as to reduce the current drawn by the startup, as well as to increase VDD max. Finally, TCR s are chosen from Baker Table 4.1 so as to minimize sensitivity to temperature.

9 Bandgap Reference Circuit Diagram

10 Beta Multiplier Temperature Sweep and Temperature Coefficient Temperature Coefficient: TC(Vref) = 2.63 ppm/c TC(Iref) = ppm/c

11 Beta Multiplier Supply Sweep and Supply Sensitivity VDD min = 2.0V, VDD max = 3.75V Sensitivity to VDD: S(Vref, VDD) = 640*2.5 =1589ppm at 2.5V S(Iref, VDD) = 640*2.5= 1600 ppm at 2.5V

12 Beta Multiplier Start up delay and PSRR Pulse of 2.5V applied to VDD at 0 sec. Observed start up delay = 1s For frequency sweep from 1 Hz to 100 MHz: Best PSRR = dB (At low frequencies upto 500Hz) Worst PSRR = db (At 100 MHz)

13 Beta Multiplier Summary Parameter Target Actual (Simulated Value) Supply (V) Vref (V) Max Supply Sensitivity (ppm) within ±10% of VDD Max Temp Sensitivity ppm/C = 68.4ppm Max Power consumption (uw) Iref(uA) Iref(uA) with VTHn= 10% and VTHp= 10% , * Changing only R1 Iref(uA) with R1*= 10% around nominal value Iref(uA) with VDD = 10% around nominal value Vref(mV) with VTHn= 10% and VTHp= 10% , 2 Vref(mV) with R1*= 10% around nominal value - 60 Vref(mV) with VDD = 10% around nominal value - 1 Min/Max Supply Voltage that the circuit is still working - 2.0V, 3.75V TCIref(ppm/C) and TCVref(ppm/C) , 2.63 Resistor Value (Ohm) and TCR k, 3300ppm/C 552k, 3800 ppm/c 552k, 3800ppm/C

14 Design Challenges Since Vref= 1.5V which is a significant fraction of VDD (2.5V), this leaves a small headroom for all the upper transistors in the cascode. incethis is a 180nm process, short channel effects cannot be neglected. Also, the value of the output resistance of the transistors is lower. This makes the Vrefand Irefmore sensitive to supply voltage variations. To counteract this, we need to increase the L of the transistors. However, the W/L ratio also needs to be large to keep Vdd,minat a reasonable value. In effect this requires an increase in the W as well as L. In the beta multiplier, for the given specifications, we would need a TCR of over 5000 ppm to get TC(Vref) = 0. However, this is not available to us in Baker P88. Therefore, we reduce the VGS1 and take Vreffrom the gate of the upper transistor. (This also reduces the VDD,min) Now the TCR required is 4300 ppm, which is a better match to the available 3800 ppm. In the beta multiplier, the power consumption can be further reduced by increasing the value of K (that is decreasing the current through the right branch further). But this increases the resistor value beyond 150kohms. The value of VDD,maxcan be increased further but this requires the sourcing transistor in the start up to be very long.