Versatile Sub-BandGap Reference IP Core

Transcription

1 Versatile Sub-BandGap Reference IP Core Tomáš Urban, Ondřej Šubrt, Pravoslav Martinek Department of Circuit Theory Faculty of Electrical Engineering CTU Prague Technická 2, Prague, Czech Republic ASICentrum Novodvorská 994, Prague, Czech Republic Prague, Czech Republic Abstract A step-by-step design procedure of sub-bandgap voltage reference (BGR) is proposed. The procedure shows on example structure main design steps of crucial parameters verified later by a simulation. The block is meant to be fabricated in 0.35µm CMOS process with analog options. The main features of the concept are the sub-bandgap output voltage of 0.7V, low supply voltage from 1.3V, low power consumption under 10µA, versatility, high working temperature range from 50 to 95 C. The versatility of the block is supported by a temperature slope trimming, extended start-up and self testing. The IP block is compact, ready to adjust, layout and integrate. The features of the design also allow the in circuit tuning. This example circuit shows the use of the design algorithm including the optimization suggestions which lead to a complex design. Index Terms BGR, bandgap reference, design procedure, design algorithm, low-power, low-voltage I. INTRODUCTION The bandgap references are most common voltage referencing circuits used both in ASICs or in commercially wide spread integrated circuits. With reasonable complexity it offers sufficient accuracy and operating range wide enough to be implemented in analog, mixed-signal and memory applications. Each application requires different values of output voltage has different supply voltage, noise requirements, PSRR value etc. Therefore each application requires at least slightly different topology or just different configuration. This work comes after a deep literature study in the BGR field mostly through the IEEE journals etc. (more details in [2]). Since the first publication of a BGR not much development have been done. In 1999 H. Banba et al. in [1] presented a circuit allowing low voltage sub-bandgap operation. Since then a lot of different designs have been presented mostly only modifying Banba s principle, extending it with several types of compensation, additional circuitry etc. The recent attempts to achieve better device to device variation were described e.g. in [3] or the theory was analyzed in [4]. The paper [3] considers injecting the compensation current into the BGR core. The current has similar generation principle and therefore it compensates the process variation. The most of the published papers treat a specific circuit topology and focus on some particular parameter such as accuracy, noise or low-voltage operation. Some papers focus on low-voltage operation optimization beginning with [1] to such designs at the edge of minimal supply voltage of 0.6V in [5] where very low-voltage OTA is presented. Nowadays the low-voltage operation is essential property. In our article, we deal with a novel step-by-step design procedure which allows an efficient streamlining of our proposed sub-bandgap reference circuit design. Thus the verified circuit is not focused on any specific parameter but it is universal and the mathematical expressions may be used the way to achieve desired optimum for assigned property. The symbolic mathematical circuit analysis of the given topology (made in Maple with the Syrup library) yields in descriptive equations of the main parameters. It uses the equations from the analysis to derive the boundaries for transistor aspect ratios, values of the other integrated passive components and the after-simulation recommendations come out as well. The proposed design flow was carefully verified by full-transistor circuit design and simulations done in Mentor Graphics IC Studio and Eldo software in concrete 0.35um IC design process. In Section II a basic principles of BGRs are explained. Following Section III describes the concrete design which was verified in Section V. The Section IV aimed to sum the design process of the BGR step-by-step. II. THE PRINCIPLE The desired output of all bandgap reference circuits is a voltage equal or proportional to the energy gap in band model of silicon. Taking the first order effects in device models of PN junctions into account a compensation of the forward voltage on a PN junction and weighted thermal voltage (V T = kt/q) gives a voltage with no thermal dependence. The device theory has proven that a forward voltage on a PN junction is a simple CTAT generator with some higher order effects. To generate PTAT voltage a weighted V T is used. V T is generated as a difference voltage between two PN junctions with different current densities. If the ratio between the current densities of the junctions is N then the difference voltage is given by: V F = V T ln N. The generation of the reference voltage is illustrated in Fig. 1. The V F term is process independent if the current ratio is maintained. The sources of inaccuracies are higher order terms in V F (T ), the weighting resistors, and the summing non-ideality /10/$ IEEE 393

2 Fig. 1. The BGR principle The conventional BGR circuit uses the common voltage and resistor network to produce CTAT and PTAT voltage. The conceptual schematic is in Fig. 2. As can be seen the parasitic PNP BJTs are used as PN junctions. The reference voltage is then given by: V REF = V BE1 + R 2V T R 3 ln NR 1 R 2 (1) It assumes R 1 = R 2 and V BE1 is voltage across the first (smaller) junction. As can be seen the core produces current and the output voltage is determined by the resistor R 4. When more detailed look on device theory is applied it can be derived that the current is proportional to the bandgap energy of the silicon. Besides the very low-voltage operation the structure according to Fig. 3 has several disadvantages too. The matching in the current mirror introduces some error and the drain-source impedances of MP 11,12,13 determine the PSRR properties together with the OPAMP. In the conventional BGR only the OPAMP determines the PSRR of the circuit. III. PROPOSED DESIGN CONCEPT In this Section, we develop a block-level design concept suitable for incorporation into application-specific ICs in the form of a full-custom IP core. First, the considered design must be described. The IP block consists of several sub-blocks shown in Fig. 4. The basic principle of the BGR is obtained with the BGR core and the OPAMP block. The other blocks provide the circuit with extra features and secures the right start-up and the bias point for the core. Fig. 2. The conventional BGR circuit The schematic proposed by H. Banba in [1] uses common current instead of voltage and therefore it allows a low-voltage operation. The schematic is in Fig. 3. The theoretical minimal supply voltage is given as V DDmin = V BEmax + V DSsatmin, where V DSsatmin is a minimal saturation voltage of MP 11. Fig. 3. The low-voltage BGR circuit The design in Fig. 3 has naturally limited accuracy without any compensation. The value of the output voltage varies with the process and with the temperature although the first order thermal coefficients are canceled. The reference voltage is given by equation 2. V REF = R 4 ( VBE1 R 2 + V ) T ln N R 3 (2) Fig. 4. Block schematic of the complete IP block The core has exactly identical topology as in Fig. 3. As CTAT and PTAT generators it uses parasitic vertical PNP BJTs available in CMOS process. The current of the current mirror partly determines the current consumption of the circuit so it was chosen sufficiently low around 300nA. More on the correct forward current consideration later. The BGR core is also equipped with trimmable resistors R 1,2 and R 4. All these resistors are composed of 16-step resistor ladder. This allows adjusting the value of all three resistors thus the temperature slope of the output voltage with a 4-bit word. This is to compensate possible process variations or to compensate the temperature coefficient of the output buffer. The OPAMP is basic two-stage with NMOSTs at the input with the Miller compensation. The OPAMP is externally biased. The bias voltage is provided by a current source known as Vittoz loop presented by E. Vittoz in [6]. Although this type of current source is PTAT, it naturally compensates the process variation. The variation of the biasing current of the OPAMP has only minor effect on the output voltage thus it is not a complication. To ensure the proper biasing of all circuits after powering it up, the start-up circuit is utilized. The startup circuit is basic monostable multivibrator where the time constant depends just on RC constant. The second part of the startup circuit is similar monostable multivibrator which creates an enable signal for the self check circuit. The startup circuit is depicted in Fig. 5 The self-check circuit 394

3 Fig. 5. The startup circuit acknowledges the outer circuitry whether the BGR started correctly or not. It also determines the start-up time of the BGR. The high voltage level on the V BGR OK output signs the circuit is up and has correct output voltage. The schematic 6 shows the principle of the BGR check circuit. It compares Fig. 6. BGR check circuit the reference voltage with a voltage across a PN diode. Since the circuit works as a simple comparator with finite gain the voltage across the diode must be lower than V REF at all times. IV. STEP-BY-STEP DESIGN PROCEDURE This Section describes the main asset of our contribution, building-up a thorough design procedure for the BGR block design. A. Specifications and Requirements The beginning of the design process requires the parameters specification. The parameters which specify the BGR circuit are: Required output voltage V REF Temperature range (T min, T max ) and the default temperature (T 0 ) Supply voltage range (V DDmin, V DDmax ) The V REF variation either with a process or with a temperature (σv REF ) Power supply rejection ratio (P SRR) Supply current (I DD ) Startup time (t start ) Trimming range (a bits and ( V REF / T ) min,max ) Chip area The extraordinary case is the value of N the ratio between the areas of the BJTs. This parameter has to be estimated or chosen. It influences the chip area and the accuracy too B. BGR Core with an Ideal OPAMP Model a) Design: The current of the MP 11,12,13 in Fig. 3 I BGR must be estimated first. The good estimate is one tenth of the maximal supply current. To minimize the effect of higher orders in the PN junction temperature characteristic, the forward current should be at the high edge of the logarithmic region. This can be found in [7]. When the saturation current density (J S ) is known from the model the area of the BJTs can be calculated. A P N = 0.1I DD max J S (3) By substitution of device parameters X T I and V BE (T 0 ) at I 0 to the equation: V BE (T ) = V G0 + (V BE (T 0 ) V G0 ) T ( ) ( T 0 ) (4) T IC X TI V T ln + V T ln T 0 I C0 and developing it into Taylor series around T 0 the temperature coefficient ( V BE / T ) is known. The values of the resistors are then: R 3 = V T ln N (5a) I f T V f / T R 2 = R 1 = R 3 (5b) V T ln N Now the aspect ratio of the mirroring transistors (MP 11,12,13 ) can be calculated. The maximal aspect ratio of those should be: S 11max = 2I BGR K P VDS 2 (6) Where K P = µ P C ox and V DS = V DDmax V BE (T min ). b) After simulation recommendations: Resistors R 1,2 and R 3 adjust the temperature curvature. According to the principle the increase of R 3 causes tilting the slope of the curve at T 0 to negative values, increase of R 1,2 causes tilting the slope more to positive values and vice versa. Adjusting of R 4 causes proportional increase or decrease of the output voltage at T 0. C. OPAMP with an Ideal Current Source as a Biasing c) Design: An universal design rules can be applied and in case of not meeting any of the requirements it could be easily modified without any larger effect on the BGR core function. None of the transistors in the OPAMP should have minimal allowed W and L. To keep the phase margin of the Fig. 7. The Miller OPAMP schematic OPAMP on reasonable value 60 the compensation capacitor has according to [8] value of C GS11 where C GS11 is a gate-source capacitance of MP 11. The tail current estimate 395

4 should be I D5 = I tail = (2V REF C C ) /t start. Then the aspect ratios of MP 3,4 can be estimated as: W 3,4 I tail = L 3,4 K P (V DD V T H3 (max) + V T H1 (max)) 2 (7) The NMOSTs MN 1,2 are not strictly defined. They are supposed to be wide in order to have large gain while not having minimal value of L in order to have good matching properties. They might be in strong or weak inversion, depending on a drain current and W/L ratio. These can be set to have the aspect ratio of about 10 and L = 5L min and after the simulations of offset voltage and gain these might be adjusted. The minimal aspect ratio of MN 5 can be estimated as: W 5 2I tail = L 5 K N (V CMmin V T H1 (min) + V GST1 ) 2 (8) where K N = µ N C ox. There is no reason to push higher current through the second stage (transistors MP 6 and MN 7 ) because it is not required to have specific gain or to be able to drive huge load. So for the first iteration the aspect ratio of MN 7 should be kept the same as MN 5. The aspect ratio of MP 6 is set by a fact that both MP 1 1 and MP 6 have to be saturated and correctly biased even in the worst case. Using similar equations like before the minimal aspect ratio of MP 6 can be expressed as: W 6 L 6 = 2I tail K P (V T H11(min) + 2I BGR S 11K P ) 2 (9) d) After simulation recommendations: Too large offset voltage can be reduced by increasing the area of MN 1,2 and MP 3,4 while maintaining the same W/L. The stability can be increased by moving the dominant pole closer to the frequency axis origin by increasing the Miller capacitor. The expressions for the poles could be found in [8]. Bad PSRR might be caused by too short transistors MP 3,4 in the high side current mirror or MP 6 in the second stage. Insufficient gain can be increased by increasing the aspect ratios of the differential pair or the MP 6 in the second stage. D. Vittoz Loop Started with Piecewise Linear Voltage Source e) Design: The ciruit is well described in [6]. The main point of the design is to choose dimensions to have reasonable value of R 1 and acceptable loop gain to stabilize whole circuit. It is reasonable to have S 2 = S 4 = S 6 and about S 3 = 10S 1. The value of the resistor is then R 1 = (V T ln 10) /I V L. The thermal coefficient determines the thermal behavior of the current source. The transistors MN 1,3 have to operate in the weak inversion region. Assuming maximal overdrive voltage for weak inversion V GST = 0 then the minimal aspect ratio of MN 1 thus MN 3 is: W 1 L 1 = I V L 2nK N (10) The transistors MP 2,4,6 are rather to be with the aspect ratio of about 0.1 or lower to isolate the supply rail from the output by a high output impedance and prevent the propagation of power supply distortion to the output. To avoid high current peaks during the startup, the transistor MN 5 should be very long, cascoded or connected with another resistor in series. f) After simulation recommendations: High current peaks during the startup can be reduced by decreasing the aspect ratio of MN 5 or adding a resistor in series. Otherwise the circuit is very universal and will work with various resistors and aspect ratios. E. Start-up Circuit The time constant τ 1 = R 1 C 1 is first run estimate of the delay of the start pulse but the delay depends on the threshold voltage of the Schmitt trigger. This block should be designed by trial and error method. It does not have many levels of freedom so it is possible to set the correct values of R 1,2 and C 1,2 within a few simulation runs. F. Output Buffer g) Design: The output buffer has the same topology as the OPAMP in Fig.7 and it is connected with 100% negative feedback as an unity gain amplifier. It works in static mode with very narrow range of voltages, so it could be designed very tightly. The design procedure is very similar to the one in IV-C. The OPAMP will work designed the same way as the BGR core OPAMP. The thing is to optimize it for the load and mainly for the PSRR. The compensation capacitor connected between the gate of MP 6 and the ground can be also estimated experimentally. There are no requirements for AC operation so the capacitor can almost be as big as the chip area allows. h) After simulation recommendations: For good PSRR the transistors MP 3,4 should be long as much as possible for the correct bias point. The gain does not have to be high so it might be useful to set the gain of both of the stages the same to exploit the property of the power supply distortion cancellation ([2]). For better (lower) offset voltage the products W 1,2 L 1,2 and W 3,4 L 3,4 might be increased. For higher possible output sink current through MP 6 and MN 7 should be increased by increasing the width of those transistors while maintaining the middle of the operating region at V REF. The compensation capacitor creates and sets the position of the dominant pole and also grounds possible AC distortion present at the gate of MP 6 so for poor stability or to improve PSRR this capacitor can be increased. G. BGR Check Circuit i) Design: The presumption for proper operation is that the reference voltage produced by a PN diode, in this case, must be lower than V REF of about tens of millivolts. Therefore the diode has to have large area and/or very small forward current. There are no strict requirements for the transistors the NMOST pair works as a differential pair which should have some gain thus the aspect ratio could be around 10. The high side PMOST mirror works as a load for the differential pair but since there is no external current biasing the aspect ratio should be very small in order to dissipate as less power as 396

5 possible. The reasonable value for W 1 /L 1 is about 0.1. The transistor pairs MN 2,3 and MP 1,2 in Fig. 6 have the same aspect ratio. The bias voltage is derived from the Vittoz loop circuit. j) After simulation recommendations: When insufficient voltage difference between the V REF and the voltage of the diode is encountered the gain can be increased by increasing the aspect ratio of MN 3,4. High current consumed by the circuit can be fixed with prolonging MP 1,2. Longer transistors in the PMOST mirror also increase the load thus the loop gain. H. Trimming the Temperature Slope k) Design: Expression for the value of the R 0 from Fig. 8 will be: I. Technology limits The circuit was designed in standard industrial CMOS process utilizing available models for the devices. As it is usual more attention is focused on modeling the MOS transistors and the parasitic BJTs are on the background. There were no process variations for BJTs available in given design kit. The devices swept all over the corners were the MOSTs and the resistors. The clue leading to better precision in mismatch among BJTs is to enlarge their junction areas. Unfortunately this applies unwanted increase of the bias current too. V. VERIFICATION RESULTS The example of the verification results is in Fig. 9 and 10. The basic numerical values are in Tab. I. R 10 = R 1min = V BE T 1 V REFmin R 4 T The one step resistor in the R 1 ladder will be: V BE T R 3 (11) R 1X = R 1 max R 10 N (12) where N is the number of the steps of the resistor ladder. The value of R 40 will be calculated likewise: R 40 = R 4min = The value of one step in R 4 is: V REF V BE R 1max + V (13) BE R 3 Fig. 9. Verified waveform of the startup and V BGR OK signal generation. The plot accords to supply voltages 1.27V and 3.33V, temperatures in range C and all process corners (TT, FFmin, SSmax, FSmin,max, SFmin,max) R 4X = R 4 max R 40 N (14) The levels of the R 1,2 ladders must go concurrently and the levels in R 4 resistor ladder must go the other way around - it means when resistance of R 1,2 rises, the resistance of R 4 must fall. The switching transistors should be designed wide enough not to influence the resistor ladder. Fig. 8. The resistor ladder for trimming Fig. 10. The temperature curves demonstrating the highest and the lowest trimming word setting all across the corners. The plot accords to supply voltages 1.27V and 3.33V, temperatures in range C and all process corners (TT, FFmin, SSmax, FSmin,max, SFmin,max) l) After simulation recommendations: If the values of the particular resistors are precisely set as they were calculated, the adjustable resistors should work correctly in the simulation for the first time. VI. CONCLUSION A Versatile BGR IP block was presented. It is verified with commercial simulation tools on the transistor level. The concept was successfully proven to be feasible to prototype as 397

6 Conditions Min Max Unit V REF setting 0000 to mv at 27 C V DD =1.27 to 3.33V all corner simulation Min: FFmin, 3.33V, 1111 Max: SFmax, 1.27V, 1111 T C± setting 0000 to µv/k temp. slope V DD =1.27 to 3.33V all corner simulation 1 Min: FFmin, 1.27V, 1111 Max: SFmax, 3.33V, 0000 TABLE I THE NUMERICAL VALUES OF V REFmin,max AND THE TEMP. SLOPE VALUES FOR 0000 AND 1111 TRIMMING WORDS ALL ACROSS THE CORNERS (TT, FFMIN, SSMAX, FSMIN,MAX, SFMIN,MAX) an MPW or as a basic building block of analog or mixedsignal ASICs for example in power management ICs. The actual prototyping (MPW fabrication) is being prepared. The presented step-by-step design process also underlies the asset of this work. It is focused on creating robust design through estimating reasonable parameter values which follows with the optimization and adjustment according to presented recommendations. ACKNOWLEDGMENT This project was done with a sponsorship of the Grant Agency of the Czech Republic under No. 102/07/1186. The project is running in a collaboration of the Circuit Theory Dept. at FEE CTU Prague and ASICentrum in Prague. The work on this project was also supported by the Grant Artemis JU No Scalopes and by the research program MSM of the Czech Technical University in Prague. REFERENCES [1] H. Banba et al.: A CMOS bandgap reference circuit with sub-1-v operation, Solid-State Circuits, IEEE Journal of, 34(5): , May [2] T. Urban: Integrated Low-Power Voltage Reference Block, Master thesis, CTU FEE, Prague 2010 [3] S. Segupta et al.: Design considerations in bandgap references over process variations, Circuits and Systems, ISCAS IEEE International Symposium on, pages Vol. 4 [4] P. Tadeparthy: A CMOS bandgap reference with correction for deviceto-device variation, Circuits and Systems, ISCAS IEEE International Symposium on, I Vol.1 [5] T. Ytterdal: Cmos bandgap voltage reference circuit for supply voltages down to 0.6V, Electronics Letters, 39(20): , Oct [6] E. Vittoz and J. Fellrath: CMOS analog integrated circuits based on weak inversion operations, Solid-State Circuits, IEEE Journal of, 12(3): , Jun 1977 [7] S. M. Sze: Physics of semiconductor devices, John Wiley and Sons, 3 illustrated edition, 2006 [8] P. E. Allen and P. E. Holberg: CMOS Analog Circuit Design, Oxford University Press, 2. illustrated edition,