ECE 4430 Project 1: Design of BMR and BGR Student 1: Moez Karim Aziz Student 2: Hanbin (Victor) Ying 10/13/2016

Transcription

1 ECE 4430 Project 1: Design of BMR and BGR Student 1: Moez Karim Aziz Student 2: Hanbin (Victor) Ying 10/13/2016 I have neither given nor received any unauthorized assistance on this project.

2 BMR Schematic Bias Resistors to tune TC Iref Start up Ckt BMR Core Diff Amp BMR Core Output Branch Reference: R. Jacob Baker CMOS Circuit Design, Layout, and Simulation (3rd ed.). Wiley-IEEE Press 2

3 BMR Design Process Assumed K = 4, so (W/L) 2 = 4 * (W/L) 11. To reduce power dissipation, we scaled W/L ratios on right branch of BMR core by half. Therefore, (W/L) 2 = 0.5 * 4 * (W/L) 11 and (W/L) 3 = 0.5 * (W/L) 14 Additional biasing resistors, R4 and R5, with different TCR1 coefficients, were added to the top of BMR core to tune the temperature sensitivity In output branch, M0 scaled current from BMR core to and generate Differential amplifier added to reduce V DD sensitivity Capacitor-based start-up circuit to reduce power. Since resistors push the current in a CTAT direction and transistors push the current in a PTAT direction ( V TH / T is negative) for the operating temperatures we are considering, these elements are placed in series in the BMR core and the output branch to reduce temperature sensitivity of. Challenges: 1) Trade-off between gain of diff amp and power dissipated 2) Low voltage headroom prevents the use of cascade topology 3

4 BMR Temperature Sweep 4

5 BMR V DD Sweep 5

6 BMR Start-up Step VDD response (0 1V) at time 0 rise time = 1 ns 6

7 BMR PSRR 7

8 BGR Schematic R PTAT R CTAT I PTAT I CTAT Start up Ckt BGR Core Diff Amp 1 Diff Amp 2 Diff Amp 3 Reference: 1) R. Jacob Baker CMOS Circuit Design, Layout, and Simulation (3rd ed.). Wiley-IEEE Press. 2) Adrian Ildefonso, Project 1 Sample 1 for ECE4430 Fall

9 BGR Design Process A different topology (separate PTAT and CTAT branch) for easy tuning I PTAT = n V T ln(k) / R PTAT = 1 * * ln(4) / 130k 300 na I CTAT = V D / R CTAT = 0.68 / 1M 680 na (limited by the max resistor size) obtained from weighted sum of I PTAT and I CTAT by M20 and M21, or = w 20 /w 3 * I PTAT + w 21 /w 9 * I CTAT Diff amps 1 & 2 maintain node v1, v2, v3 at the same voltage to generate I PTAT and I CTAT (similar to Baker s topology) Diff amp 3 is added to force V SG20 to change in sync with V SG of PTAT and CTAT branch (thus reduce VDD sensitivity) Optimized diff gain of 50 V/V and ultra lower power Capacitor-based start-up circuit to reduce static power Challenges: 1) Short channel device has large λ and inherently high V DD sensitivity 2) low VDD eliminates headroom for cascode topology 9

10 BGR Temperature Sweep 10

11 BGR V DD Sweep 11

12 BGR Start-up Step VDD response (0 1V) at time 0 rise time = 1 ns 12

13 BGR PSRR

14 Limitations and Improvements and can be extracted differently so that both meet the temperature sensitivity spec simultaneously (impossible for the current output branches of BMR and BGR because TC Vref TC Iref = TCR 20ppm/ S T Iref S T Iref = 20*323 >>1000ppm). To further reduce VDD sensitivity, could be fed back into the tail current of the diff amp; however, for BMR this requires a slight topology change to conserve voltage headroom. The BMR also contains a positive feedback loop, so stability issues could arise when adding the diff-amp tail current. These designs neglect the body effect, meaning that they cannot be manufactured in a standard CMOS process. In addition, for a realistic tapeout, the w/l ratio needs to be appropriate for manufacturing. For BGR, curvature compensation can be added to reduce max temperature sensitivity 14

15 Specification Summary Spec Target BMR BGR Iref Max Supply Sensitivity (ppm) within ±10% of VDD ,254 7,585 Vref Max Supply Sensitivity (ppm) within ±10% of VDD ,627 7,585 Iref Max Temp Sensitivity C) ,820 Vref Max Temp Sensitivity C) 50 8, Max Power consumption (µw) Iref (µa) Vref (V) ΔIref with ΔVTHn = 10% and ΔVTHp = 10% around nominal value N/A 22.0 na 27.5 na ΔIref with ΔR= 10% around nominal value N/A na na ΔIref with ΔVDD = 10% around nominal value N/A 10.8 na 2.72 na ΔVref with ΔVTHn = 10% and ΔVTHp = 10% around nominal value N/A 9.9 mv 13.7 mv ΔVref with ΔR= 10% around nominal value N/A 67.6 mv mv ΔVref with ΔVDD = 10% around nominal value N/A 5.08 mv mv Minumum/Maximum Supply Voltage that the circuit is still working N/A 0.69 ~ 1.3 V 0.95 ~ 1.3 V TCIref 50 N/A -1.55/ C / C TCVref 50 N/A 27.02/ C -1.12/ C TCR1 N/A See schematics TCR1 = 20 ppm/ C Startup delay N/A 100 ns 1.29 μs 15