Orister Corporation. LDO Thesis

Transcription

1 Orister Corporation LDO Thesis

2 AGENDA What is a Linear egulator LDO ntroductions LDO S Terms and Definitions LDO S LAYOUT

3 What s a Linear egulator A linear regulator operates by using a voltage-controlled current source to force a fixed voltage to appear at the regulator put terminal The control circuitry must monitor (sense) the put voltage, and adjust the current source (as required by the load) to hold the put voltage at the desired value. The design limit of the current source defines the maximum load current the regulator can source and still maintain regulation. The put voltage is controlled using a feedback loop, which requires some type of compensation to assure loop stability. Most linear regulators have built-in compensation, and are completely stable with external components.

4 LDO ntroductions LDO S Feature Headroom(Drop: minimum differential: N-OUT) is possible smaller. egulation Condition : a. AC input line voltage ripple b. Steady-state changes in the input over its tolerance band. c. Dynamic changes resulting from rapid load changes. Efficiency = ( P OUT / P N ) = ( OUT OUT / N N ) = OUT / N LDO S Merit good transient response compare with PWM mode. no F noise (due to fast-rise -time voltage or current spikes) no AC switching losses (due to momentary overlap of falling current and rising voltage across the power switch) LDO S Drawback excessive power dissipation in the series pass element (transistor, MOSFET) P D = ( N - OUT ) OUT so that put current is limited < 5A

5 LDO Operating regions Line egion Saturation egion d ds gs O

6 The Drop- oltage Drop voltage is the input-to-put differential voltage at which the circuit ceases to regulate against further reductions in input voltage; this point occurs when the input voltage approaches the put voltage.

7 Linear egulator Structure Generic low drop- series linear regulator architecture Simple low drop- series linear regulator architecture The regulator circuit can be partitioned into four functional blocks: the reference, the pass element, the sampling resistor, and the Error amplifier

8 LDO Fundamental Topology (drop) = CE (sat)+ BE.6 ~.5 OUT (Max)=0A (drop) = CE (sat)+ BE 0.9~.5 OUT (Max)=7.5A (drop) = CE (sat) 0.5 ~ 0.4 OUT (Max)=A charge pump (drop) =oon 35 ~ 350 m (drop) =oon 35 ~ 350 m

9 The FET Advantage OUT OUT B = OUT / β B = 50mA/0 =.5mA G =~μa G PNP LDO P-FET LDO t should be noted that all of the base current required by the power transistor in a PNP LDO flows of the ground pin and back to the negative input voltage return. Therefore, this base drive current is drawn from the input supply but does not drive the load, so it generates wasted power that must be dissipated within the LDO regulator: PW (Base Drive) = N X BASE The amount of base current required to drive the PNP is equal to the load current divided by the beta (gain) of the PNP, and beta may be as low as 5-0 (at rated load current) in some PNP LDO regulators. The wasted power generated by this base drive current is very undesirable (especially in battery-powered applications). Using a P-FET solves this problem, since the Gate drive is very small. Another advantage of the P-FET LDO is that the drop voltage can be made very small by adjusting the ON-resistance of the FET. For monolithic regulators, FET power transistors typically will give a lower ON-resistance per unit area than bipolar PNP devices. This allows making higher current regulators in smaller packages.

10 Comparison of Pass Element Structures PAAMETE DALNGTON NPN PNP NMOS PMOS o,max High High High Medium Medium q Medium Medium Large Low Low drop sat+be sat+be ce(sat) sd(sat)+gs sd(sat) Speed Fast Fast Slow Medium Medium

11 Enter the Bandgap eference Band gaps Offer Good voltage tolerance (inherently) Good noise performance Desirable at low voltages High efficiency

12 Bandgap Theory

13 BJT oltage eference The reference voltage is as follows ln ) ( ) ( q KT BE B BE BE B C BE EF The temperature coefficient is as follows 3 ln 3 q K T BE T EF By optimally choosing the ratio of, a temperature compensated reference voltage is known to be obtained. 3

14 CMOS oltage eference 3 _ 3 _ ln ln EF EF EF NPN NPN NPN NPN BE EF PNP PNP PNP PNP BE EF K K N q KT N q KT ; OSP PNP b PNP OSN NPN b NPN PNP PNP NPN NPN PNP BE PNP NPN BE EF FE EF EF K K N K N K q KT K K K 3 _ 3 _NPN EF ln ln K ) (

15 LDOs Allow for Better Efficiency Efficiency (%) Power Out Power n x 00 ( N ( OUT GND ) ) OUT N x 00 The efficiency of LDO regulator is limited by the quiescent current and input/put voltage difference (drop voltage).to have a high efficiency, drop voltage and quiescent current must be minimized.

16 The Carrot in LDO egulator Ground Pin Current Many (but not all) LDO regulators have a characteristic in their ground pin current referred to as the "carrot". The carrot is a point in the ground pin current that spikes up as the input voltage is reduced.

17 Feedback Basics O O O ( O - AB ( AB) EF O O O A AB B) A A A O EF EF O - O AB

18 LDO Quiescent Current q i o Quiescent, or ground current, is the difference between input and put currents. Low quiescent current is necessary to maximize the current efficiency.

19 LDO Standby Current Standby current is the input current drawn by a regulator when the put voltage is disabled by a shutdown signal. The reference and the error amplifier in an LDO regulator are not loaded during the standby mode.

20 Considerations of LDO regulator circuits Stability Performance Line regulation(dc and AC) Load regulation(dc and AC) Power Supply ejection atio(ps) Output accuracy Transient esponse Output Noise oltage Thermal Consideration Current Limiting Other

21 Stability Performance LDO manufacturers typically provide a graph showing the stable range of the compensation series resistance (CS) values, since CS can cause instability with respect to put currents. The CS is the sum of the equivalent series resistance ( ES ) of the put capacitance and the additional resistor ( add ). CS = ES + add

22 Line regulation A step change of input voltage was applied to the regulator, which is shown at the lower left in the figure. The resultant put voltage has been changed due to the different input voltages as shown in the right side of the figure. The line regulation is determined by L and L since line regulation is a steady-state parameter (i.e., all frequency components are neglected). The broken line shows the range of the put voltage variation ( L ) resulting from the input voltage change. ncreasing open loop gain improves the line regulation.

23 Line regulation in Line regulation Definition ) ( ) ( ) ( ) ( ) // ( m in ref in ds m m ref m in ds ref m in ds in ds EQ G ds G G G G

24 Load regulation The worst case of the put voltage variations occurs as the load current transitions from zero to its maximum rated value or vice versa, which is illustrated in left figure. The load regulation is determined by the LD since load regulation is a steady-state parameter like the line regulation.

25 Load regulation Load regulation Definition m m m in ds G G G

26 Power Supply ejection The ripple rejection is defined by PS o, ripple i, ripple at all frequencies

27 Power Supply ejection PS performance implications of high frequency operation PS supply o o ref in o Av( s) o pass esr esr Av( s) Where :Δsupply is equivalent to Δin for regulators Av(s) is the open-loop gain from ref to o

28 Output accuracy Δ LD Δ L ef Δv O,re f Δ O,a Pass Element Δ OUT +Δ Δ TC +Δ Accuracy specifies all effects of line regulation (Δ L ), load regulation(δ LD ), reference voltage drift (Δ O,ref ), error amplifier voltage drift (Δ o,a ),external sampling resistor tolerance (Δ o,r ), and temperature coefficient (Δ TC ).t can be defined by Accuracy L LD O, ref O o, a o, r TC

29 eference oltage Drift ref ref ref o ref o ref ref ref o ref,,, ) ( ) )( (

30 Error Amplifier oltage Drift, a, ) ( g f Δ βδ g βδ Δ a a O a o L a L a o,a

31 Tolerance of External Sampling esistors ref r O ref O ref r O O,, ) ( ) ( ) ( ;

32 Transient esponse To obtain a better transient response, a higher bandwidth of the LDO regulator, higher values of put/bypass capacitors, and low ES values are recommended, provided they meet the CS requirements.

33 Transient response The transient response is the maximum allowable put voltage variation for a load current step change. The transient response is a function of the put capacitor value (C o ), the equivalent series resistance (ES) of the put capacitor, the bypass capacitor (C b ) that is usually added to the put capacitor to improve the load transient response, and the maximum load-current ( o,max ). The maximum transient voltage variation is defined as follows: o,max 3 tr, max T ES dip ES; peak CO Cb C C Where T corresponds to the closed loop bandwidth. ES is the voltage variation resulting from the presence of the ES ( ES ) of the put capacitor. ES is proportional to ES. T T ES

34 Output Noise oltage Output noise voltage is the MS put noise voltage over a given range of frequencies (0 Hz to 00 khz) under the conditions of a constant put current and a ripple-free input voltage. The noise generated only by an LDO regulator becomes the put noise voltage. Most put noise is caused by the internal voltage reference. Typical specification of put noise voltage ranges from 00 to 500 µ.

35 Frequency response The error amplifier is modeled by a transconductor (g a ) with a load comprised of capacitor C par and resistor par. The series pass element (MOS transistor) is modeled by small signal model with transconductance g p. An put capacitor C o with an equivalent series resistor ( ES ) and a bypass capacitor C b is added. T ( s) Z sig pass //( g a ) // ( par //( // ES sc par sc ) g O p ) // sc Z b

36 Frequency response upper page equation, a part of the overall open-loop transfer function for the regulator is obtained, and the one zero and three poles can be found. f p ; f p ; f p3 ; fz ( P // ) C C C ES pass par par ES b ES C LDO Frequency esponse With Compensation LDO Frequency esponse With External Compensation

37 Frequency response Unstable Frequency esponse of LDO With too High ES Unstable Frequency esponse of LDO With too Low ES

38 Thermal Shutdown The thermal shutdown circuitry in an C prevents the junction temperature from rising high enough to damage the part. This is accomplished by monitoring the die temperature and reducing internal power dissipation to hold the temperature at the limiting value (usually ab 60 C)

39 Current Limiting There are two basic types of current limiting circuits most commonly used in linear regulators (detailed in the next sections): Constant Current Limiting oltage-dependent Current Limiting (sometimes called "Foldback Limiting ) Constant Current Limiting Foldback Limiting

40 Error/Fault Detection When the input to put differential decreases to ab 0% over the drop voltage, the fault pin goes active low by pulling down its open drain put. The Fault pin also goes low during of regulation conditions like current limit and thermal shutdown.

41 Architecture of Designed LDO Linear egulator

42 Schematic of Designed LDO egulator

43 educe the noise and ripper oltage Typical LDO Lay Line Optimization LDO Lay Line

44 LDO PCB Lay deal LDO PCB Lay (ecommended) Poor LDO PCB Lay (NOT recommended)