Programmable Digital Controller for Multi-Output DC-DC Converters with a. Time-Shared Inductor

Transcription

1 Programmable Digital ontroller for Multi-Output D-D onverters with a I. Introduction Time-Shared Inductor Modern portable electronics applications require multiple low-power supplies for their functional blocks. For example, digital still cameras (DS) and cell phones, different supply voltages are used for a LD screen, handset lightg, and camera flash. Most of existg solutions combe multiple switchg converters to supply the different blocks. In these systems each power stage uses a separate ductor, power switches and controller resultg relatively large part number and size of the power module. Multiple output flyback converters are commonly used to mimize the number of components and simplify control. This solution suffers from poor output regulation due to cross-regulation problems [1]. In addition, switchg transistor is exposed to excessive voltage stress []. Analog designs described [3,4] use pulsefrequency modulation (PFM) controllers and share one ductor between several output stages to provide improved voltage regulation. However, both of these solutions, output voltages are fixed and implementation of advanced power management techniques through dynamic output voltages adjustment [3,4] is not a simple task. Even though the flexibility of digital hardware is known, portable applications, digital PFM controllers for multiple-output supplies have not been commonly used, mostly due to their high power consumption that often exceeds the power delivered to the s. In this paper we troduce a new low power digital controller architecture that provides tight regulation of multiple programmable supply voltages for light s and allows simple implementation of power management L techniques portable applications. As Q 0 Vout1(t) H1Vout1(t) H1 Vref1(t) 3µH Q 1 shown Fig.1, similar to analog 1 HVout(t) Vout(t) solutions [3,4], the controller utilizes the V H Vref(t) Q fact that PFM the ductor current is Vout3(t) H3Vout3(t) H3 discontues hence it can be time-shared Vref3(t) Q 3 3 between multiple outputs. H4Vout4(t) Vout4(t) H4 Vref4(t) Besides output voltages, this solution, Q 4 4 the on-times of power switchers can c also be dynamically changed. Therefore 0 (t) tr1(t) tonlut 6-bit c 1 (t) c (t) c 3 (t) c 4 (t) tr(t) Programmable tr3(t) tr4(t) the switchg frequency, maximum on-time logic V DA LUT currents stress, and output ripple can Σ DA also be directly controlled. In the followg section we briefly Fig.1 Sgle ductor multi-output D-D converter based on a Digital PFM expla operation of the time-shared controller Filter 1of 5

2 multi-output digital PFM controller. Section III describes novel low-power architectures of basic functional blocks. Experimental results obtaed with a prototype utilizg the new architecture are shown Section IV and Section V summarizes the ma results. II. System Operation The power supply of Fig.1 is a four-output buck converter controlled with the new digital PFM controller. The output voltages are regulated usg a set of four comparators and programmable on-time logic. The reference voltages of the comparators are programmed by Σ- digital-to-analog converters (DA) and compared to output voltages. When an output voltage v outi (t) falls below reference, comparator Q i sends a signal to on-time logic that resolves possible signal conflicts and turns on the correspondg transistor Q i and the ma switch Q 0 simultaneously, allowg output capacitor i to be charged for a fixed period t on_i. Durg this time all other transistors are disabled and if signals from other comparators occur, they are registered and served based on the order of occurrence. The diodes D 1 to D 3 prevent cross-conduction from high to low output voltage stages. The output v out1 (t) is reserved for the lowest output and does not require a diode. III. Architectures of Basic Functional Blocks All the blocks of the multi-output controller are designed with two specific goals md. They are constructed to be mostly digital and to have very low power consumption, comparable to the state of the art analog solutions [3,4]. Therefore, the proposed architecture can be easily transferred from one implementation technology to another and used various low-power applications. A. Programmable On-Time Logic Programmable On-time logic of Fig. consists of a block named stage selector, two look up tables (LUT), 4-to-1 demultiplexer, and only one programmable delay le. c 0 (t) c 1 (t) c (t) c 3 (t) c 4 (t) tr 1 (t) Based on the trigger signals tr(t) received from output tr (t) sel[1:0] DEMUX Stage tr comparators, stage selector creates a -bit signal sel. Selector 3 (t) 4:1 tr 4 (t) t This signal is fed to puts of 4-word LUTs that c(t) on (t) start produce bary values t on [n] and V ref [n] for the delay Delay Le t on [5:0] le and Σ- DA (Fig.1), respectively. The select signal also controls the 4-to-1 demultiplexer which distributes signal c(t), of duration t on (t) to appropriate power switchers. While one trigger signal is served, stage selector also monitors outputs of the other comparators and processes any request after the ongog task is completed. t on_1 [n] t on_ [n] t on_3 [n] t on_4 [n] t on LUT v DA1 [n] v DA [n] v DA3 [n] v DA4 [n] Fig.. Programmable on-time logic v DA [9:0] DAs LUT of 5

3 ton[0] ton[1] ton[] ton[3] ton[4] ton[5] A1. Delay Le Instead of usg a counter that requires an external clock signal and, some cases, consumes significant amount of power, to create on time, a programmable delay-le [5] is used. The delay le has very simple low-power structure and does not need a high frequency external clock. Figure 3 shows a 6-bit delay le composed of three terconnected 4-to-1 multiplexers and a set of 64 delay cells. The cells are connected to the multiplexer a start logarithmic fashion. One, four, and sixteen, delay cells are connected between each two successive puts of MUX1, MUX1 MUX, and MUX3, respectively. The on-time value t on [n] is connected to the control puts of the multiplexers. Two least significant bits are tied to MUX1, two most significant bits to MUX MUX3, and the remag ones to MUX. After start signal, created by stage selector of Fig., goes 16 delay cells high the signal propagates through t on [1:0] cells and MUX1, MUX3 then passes through t on [3:] x 4 cells and MUX and fally goes through t on [5:4] x 16 cells before appearg at the end output. In this way programmable on-time signal is created. Fig.3. Segmented Delay-Le B. Programmable Voltage eference To mimize power consumption and complexity of the system only one sgle-bit Σ- DA is used to provide programmable reference values for all four comparators. Furthermore, power consumption of Σ- DA is v (t) mimized by operatg it only durg a short V ref Σ Q Vref1(t) 1 portion of each switchg period. Bandgap eference As shown Fig.4 the programmable voltage Q Vref(t) reference consists of four filters, control v[n] 1-bit transistors, voltage reference (bangap), Σ- v DA [n] Σ MOD Q 3 modulator and digital logic that provides clk and... enable signals. The sigma-delta modulates the voltage v Σ- (t) to result the average value proportional to the product V ref x v DA [n], where v DA [n] is provided from the programmable on-time logic of Fig.. This voltage is passed to the enable clk Fig.4. Σ- DA Block Diagram Q 4 c 1 (t) c (t) c 3 (t) c 4 (t) ontrol signals from on-time logic unit Vref3(t) Vref4(t) 3of 5

4 filter through transistor Q i, selected with high value of correspondg signal c i (t), also provided by on-time logic. Durg this period enable signal is high and the Σ- modulator is clocked with a high frequency signal, locally created by the rg oscillator. When signal c i (t) goes low, the rg oscillator is disabled to reduce power consumption. In addition, the transistor Q i, turns off leavg high impedance across the filter and keepg the output capacitor voltage, V ref_i (t), constant. The capacitor voltage is refreshed when the control signal c i (t) is active aga. It should be noted that the operation of Σ- durg the voltage refreshment does not affect the output comparator sce the comparison is always performed prior the refreshment. Figure 5 shows the block diagram of a nd order Σ- modulator, which has a put and produces a sglebit output modulated value. This architecture v DA [n] is based on a well-known error feedback structure [6] used noise-shapg analog-todigital and digital-to-analog converters. The modulator is fully digital and implemented with simple hardware. Delay blocks Z -1 are comprised of set of edge triggered D-flipflops, and the multiplication by is performed with a simple shift register. To reduce filterg delay block v[n] 1-bit bit 1-bit - + Fig.5. Σ- Modulator Block Diagram requirements, Σ- is clocked at a frequency significantly larger than switchg frequencies of the PFM controller allowg modulator to run through enough cycles to charge capacitor to the reference voltage. This implies a tradeoff between the mimum allowable on-time of the transistors and accuracy of voltage regulation. However, sce the output filter capacitor is recharged through each switchg cycle this effect is mimized. z -1 z -1 delay block IV. Experimental System and esults An experimental FPGA prototype based on the diagram shown Fig.1 was built. The put voltage is between 4 V and 8 V, and the outputs are regulated at 1.8V,.V,.5V and 3.3V. The output was varied between 1 ma and 50 ma matag discontuous current and PFM regulation for all operatg conditions. A. Steady State Operation Figure 6 demonstrates operation of the multi-output buck converter steady state. It can be seen that the simultaneous tight regulation of the output voltages is achieved and that the current gog through the ductor is discontuous and shared among different output stages. 4of 5

5 B. Dynamic Mode Operation of system when the digital reference and output are changg is shown Figs. 7 and 8. From Fig.7 it can be seen that the output voltage can be digitally programmed and dynamically changed. esults of the output change experiment are showed Fig.8. It can be seen that the system matas good output voltage regulation and that the crossconduction problems between neighborg stages does not exist. V out1 (t) = 1.8 V V out (t) =. V V out3 (t) =.5 V Inductor urrent Fig.6. Steady state operation of the multi-output buck converter with time shared ductor: h1, h3, and h4 output voltages; h-ductor current. Time scale is 5µs/div. V out (t) h : V out(t) h : h 1: V out1(t) h 1: V out1(t) DA Input u[n] h 4: c 1 (t) 0 ma 10 ma Fig.7. Transient response to change of digital voltage reference: D0 to D9 digital reference; h.1: correspondg output voltage change from 1.8V to.65v h.: The output voltage of a neighborg stage. Fig.8. Transient response to change between 0 ma and 10 ma: h.1: the output voltage of stage regulatg voltage at 1.8 V and operatg steady state; h.4: correspondg gate drive signals; h.: The output voltage of a neighborg stage. In the fal version of this paper additional experimental results will be provided, cludg the demonstration of the controller implemented on a chip, which is currently fabrication. The itial chip simulations verify very low power consumption comparable to state of the art analog solutions. V. onclusion A new programmable digital controller for low power multi-output dc-dc converters used battery powered devices is shown. The controller features unique very low-power architectures of basic functional blocks and significantly simplifies implementation of low-power management systems. 5of 5