Active Shields: A New Approach to Shielding Global Wires

Transcription

1 Active Shields: A New Approach to Shieldg Global Wires Himanshu Kaul University of Michigan, Ann Arbor hkaul@eng.umich.edu Dennis Sylvester University of Michigan, Ann Arbor dennis@eecs.umich.edu David Blaauw University of Michigan, Ann Arbor blaauw@umich.edu ABSTRACT A new shieldg scheme, active shieldg, is proposed for reducg delays on terconnects. As opposed to conventional (passive) shieldg, the active shieldg approach helps to speed up signal propagation on a wire by ensurg -phase switchg of adjacent nets. Results show that the active shieldg scheme improves performance by up to 16% compared to passive shields and up to 9% compared to unshielded wires. When signal slopes at the end of the le are compared, savgs of up to 38% and 7% can be achieved when compared to passive shields and unshielded wires, respectively. Categories and Subject Descriptors B.7. [Integrated Circuits]: Design Aids Lay, Placement and Rg. General Terms Design 1. INTRODUCTION With creasg die sizes and shrkg wire dimensions, wires are becomg longer and more resistive and at the same time clock frequencies are risg. Robust on-chip global signalg the face of heightened couplg capacitance is begng to place fundamental limits on global clock frequencies. The growg couplg capacitance creases the amount of functional noise troduced on a wire as well as enhances the sensitivity of wire delays to aggressor switchg. In the worst-case scenario, when the aggressor is switchg at the same time as the victim but the opposite direction, the victim must charge an effective couplg capacitance twice that of the nomal one (accordg to [1], a factor of 3 results from the absolute worst case scenario). In a recent 1 GHz commercial microprocessor, designers found a 50 MHz reduction achievable clock frequency due to couplg capacitance effects []. To alleviate the problem of noise jected by aggressors, shields can be placed on either or both sides [3]. These are ground or power (V dd ) les placed between two wires to prevent direct couplg between them. Other methods clude creasg wire spacg to reduce the couplg capacitance or creasg wire widths to reduce the ratio of couplg to ground Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted with fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. GLSVLSI 0, April 18-19, 00, New York, New York, USA. COPYRIGHT 00 ACM /0/0004 $5.00. (a) (b) Figure 1. a) Passive shields b) Active shields capacitance. Buffer sertion algorithms already exist to reduce RC delays and noise on long les [4,5]. The shieldg methodology used today is passive that shield wires are tied statically to V dd or ground. A more useful approach would guarantee a best-case switchg scenario for a wire. The concept of active shieldg uses shields on either side of the wire that help to speed up signal propagation through the Miller effect. The Miller effect states that the effective couplg capacitance between two nodes is zero if the transitions at the two nodes occur at the same time and the same direction (a best case scenario can result a factor of 1). Figures 1a and 1b illustrate the concept of active shieldg. Allowg the shields on either side of a wire to switch the same direction helps to reduce the total le capacitance. This approach is scalable sce the creasg le resistance can be offset by the creasg couplg capacitance. We demonstrate that usg active shields as proposed this work results better performance when compared to other methods like passive shieldg and wire spacg/sizg under the same area constrat and capacitive load on the previous stage. Comparisons with buffer sertion are not made sce this approach is not meant to replace the buffer sertion methodology but to complement it. For very long les buffers would still be required to meet performance requirements. The rest of this paper is structured as follows. Section describes the active shieldg approach and develops a simplified analytical model of the theory behd it. Section 3 describes the simulation setup used to compare active shieldg to other approaches, and provides results and optimization approaches to obta the maximum gas from active shieldg. Section 4 details the limitations of this work and future work needed to overcome these limitations. Fally, Section 5 provides conclusions. This work was supported by the MARCO/DARPA Gigascale Silicon Research Center and by Semiconductor Research Corporation (SRC) contract CL 11

2 . ACTIVE SHIELDING The active shieldg approach uses the effective Miller capacitance to reduce the total capacitance on a le. If the transitions on wires adjacent to the wire of terest can be ensured to switch simultaneously and -phase, the effective couplg capacitance on the middle wire is reduced. This will result smaller delays for the wire of terest. At the same time the neighborg wires act as shields when the le is quiet. To ensure -phase switchg of the side wires, they must be driven by the same put signal as the middle wire. This approach can be used to speed up signal propagation two cases a wire with shields on its sides and a wire wide enough to be split up to three wires while matag the same footprt (to avoid area penalties). In the case of the wide (unshielded) wire, the total ground capacitance of the middle wire is reduced (and the effective couplg capacitance is reduced through the Miller effect) while the resistance of the wire creases. The decrease effective capacitance on the le must overcompensate for the crease resistance due to the splittg of the wire for this approach to be practical. The unshielded wire will be referred to as the fat wire henceforth. When a fat wire is converted to an actively shielded one, the noise immunity will improve sce any aggressors that were previously coupled to the fat wire will no longer be coupled directly to the middle wire. Sce the put signal now must drive three verters stead of one (as the two reference cases) we must consider the capacitive load presented to the prior stage. The approach we follow when comparg active shieldg to passive shieldg and unshielded fat wires is to set the total device width of all three new drivers to that of the origal sgle driver. In order to obta analytical sight to the tradeoffs volved keepg the capacitive load on the previous stage the same, we used a simple model (based on work [1]) to compare the delays of the passively shielded and actively shielded configurations. The model assumes there are no coupled aggressors. Figures a and b show the equivalent circuits used for modelg the delays usg passive and active shields (the load capacitance is not cluded the model). The labeled wire parasitics are denoted as per unit length. The equivalent resistance of an verter with NMOS width of 1µm is R 0. Thus, if the driver size the passively shielded configuration is W, then the driver resistance is R drv =R 0 /W. (1) The resistances of the drivers for the side and middle wires are R drv_side =R 0 /W side () R drv _ mid =R 0 /W mid (3) The constrat that is used when convertg from passive to active shields is W=W mid +*W side. Delay due to passive shields (for a wire of unit length) is given by T passive = 0.693R drv (C gmid +*C c ) R wmid *(C gmid + *C c ) (4) Delay due to active shields is given by T active =0.693R drv_mid (C gmid + *k*c c ) R wmid *(C gmid + *k*c c ), (5) k = 1 - t rmid /t rside (6) V V and R drv R drv_side R drv_mid R drv_side Rw_mid Cg_mid Figure a. Passive shields Rw_mid Cg_mid Figure b. Active shields eol1 eol3 eol1 eol3 t rmid =.R drv_mid (C gmid + *k mid *C c ) + 0.9R wmid * (C gmid + *k mid *C c ) (7) t rside =.R drv_side (C gside +k side *C c )+0.9R wside *(C gside +k side *C c ) (8) Obtag the rise/fall times on the middle and side wires (t rmid, t rside ) volves iterations sce these times depend on the effective couplg capacitance durg switchg and the effective couplg capacitance depends on the rise/fall times. Sce the k term is less than one, the effective couplg capacitance on the middle le becomes smaller. To mimize this capacitance, the drivers of the side les should be strengthened to reduce their slew rates. In this case, the effective resistance of the middle driver creases (sce the total W is fixed), creatg an herent tradeoff designg for active shields. Thus, R drv_mid (7) creases while the C c term decreases as drivg power is shifted to the side wires. We expect that there is a particular distribution of driver sizes for which the delay of the middle wire can be optimized. This optimal pot depends heavily on the values of the ground and couplg capacitances. As the C c term creases, it is more favorable to shift more of the drivg capability onto the side wires. Figure 3 shows the delays usg active shields normalized to that with passive shields. The total driver size (W/L of NMOS) was fixed at 00 while the size of the driver for the middle le ( the actively shielded case) was swept. The model does not yield realistic trends for driver sizes less than half the total driver size but it does pot to the existence of an optimal delay pot. The figure shows that as the couplg capacitance rises (by decreasg 113

3 Delay (normalized to passive shield) Delay vs Middle driver size Passive shields Increasg Middle Driver Size (W/L of NMOS) µm.5 µm 0.8 µm 1 3 Figure 4a. Setup for fat wire scheme. L 1 3 Figure 3. Delay with active shields as driver distribution is changed for different couplg capacitances the spacg or creasg the thickness) the delay gas compared to the passively shielded case crease. There are cases where the effective decrease capacitance does not offset the decrease drivg power of the middle wire. In such cases the actively shielded configuration is always slower than the passively shielded one. To get the maximum gas of active shieldg, the couplg capacitance must be maximized (by mimizg the spacg between the side and middle wires). 3. SIMULATION RESULTS 3.1 Simulation Setup Typically fat wires are used to reduce signal delays by limitg the le resistance. For our analysis, the proposed and alternative approaches are compared to the fat wire terms of the achievable delay. In all approaches, the footprt of the signal re is kept the same so as not to cur any area penalty. The total capacitive load on the previous stage (which drives ) is kept the same by matag the total device width of the driver(s) used for transmittg the signal. The only area overhead curred with active shieldg is due to the splittg of one large driver to three smaller drivers. Figures 4-6 show the simulation setups for three cases fat wire, active shieldg, and passive shieldg. The signal is applied at, while 1 and 3 provide switchg activity for the aggressors (1 and 3 switch simultaneously the opposite direction of ). Another configuration we considered was the case which the wire of terest ( Figure 4a) is reduced width while the spacg to the aggressors is creased by the same amount. This represents the wire sizg/spacg methodology to reduce delays and jected noise on wires, under an area constrat. This leads to less couplg capacitance but at the same time creases the ground capacitance. The resistance on the wire creases rapidly but, unlike the active shieldg case, the entire current drive can be used for one wire. In contrast the active shieldg approach aims to reduce the ground capacitance by creasg the couplg capacitance (which can be effectively reduced durg switchg). 0.8µm 0.8µm.5µm 0.8µm 0.8µm C Cg C 1 3 Figure 4b. Cross-section of terconnect structure for fat wire scheme µm µm Figure 5a. Setup for actively shielded wire. 0.8µm 0.8µm _agg Cg side W side Cg mid L.5µm S W mid Cg side W side 0.8µm 0.8µm _agg t h t h 1 3 Figure 5b. Cross section of terconnect structure for actively and passively shielded wire. 114

4 1 0.8 µm i n Voltage (V) (active shield) shield (active shield) (passive shield) µm Figure 6. Setup for passively shielded wire. For the active shieldg approach, the delay depends on C c, C g, and the resistance of each of the three wires (all of which depend on the wire widths) along with the optimal driver size distribution among the three wires used for signal transmission. Optimizg the C c, C g, and le resistances yields optimal widths of the three wires under a constant area constrat. This is further constraed by the mimum width and spacg rules for a particular technology. The simulations considered different technologies (denoted by different wire thicknesses t) with the ter-level dielectric (ILD) thickness (h) fixed at 0.55 times the wire thickness for each technology. The width of the footprt of the wire was kept constant at.5um for each technology and the aspect ratio was fixed at.4 (which dictated the mimum width and spacg). For each technology five different configurations which the wire could be split were used to compare the passively and actively shielded wires. The spacg between the wires was always kept mimum to maximize C c and mimize ground capacitance which is not affected through active shieldg. For each wire sizg configuration, the optimal delay for the actively shielded case was obtaed by sweepg the driver size distributions. The le lengths simulated were 7.5mm and 3.75mm. For the 7.5mm (3.75mm) le length, the driver size beg driven by node was 00X (15X) and the aggressor driver sizes were 00X (15X) each. Delays were measured from to and slopes were measured as 10-90% delays at node. The load capacitance ( ) corresponds to the put capacitance of a 5X verter. All capacitance values this paper were extracted usg a -D field solver. To calculate power, a switchg activity of 0.5 for an 800MHz operatg frequency was applied at node and the current drawn from the supplies for drivg the signal was measured. 3. Analysis of Results For the active and passive shieldg approaches the delay and slopes were normalized to that of the fat wire for each technology (represented by a wire thickness). The results presented show the delays and slopes obtaed with optimized wire and driver sizg configurations ( the case of active shieldg). Typical waveforms for both active and passive shieldg are shown Figure 7. Active shieldg clearly demonstrates superior delay and slew rate characteristics, which is the strength of the active shieldg approach. Further, Figures 8-11 show that the optimal delay usg active shields is always better than that of the fat wire and the passive shields. The absolute numbers for delays of passive and active shields with or with switchg aggressors are very similar. However, for the fat wire they can vary as much as % (delay) and 13% (slope) from the case when the Tim e (ps) Figure 7. Voltage waveforms at the end of the wire for active and passive shields. The signal on the active shields is also shown. Delay / Slope (normalized to fat wire) Delay/slope (normalized to fat wire) Delay / Slope (Normalized to fat wire) D elay (A ctive shields) D elay (Passive shields) Fat w ire (D elay and slope) S lope (A ctive shields) S lope (Passive shields) W ire Thickness (t) (m m ) Figure 8. Optimal delay/slope vs. wire thickness for copper wire of length 7.5mm and aggressors switchg D elay (Active shields) S lope (Active shields) D elay (Passive shields) S lope (Passive shields) Fat w ire (delay and slope) W ire Thickness (t) (m m ) Figure 9. Optimal delay/slope vs. wire thickness for copper wire of length 7.5mm and aggressors not switchg D elay (A ctive shields) S lope (A ctive shields) D elay (Passive shields) S lope (P assive shields) Fat w ire (delay and slope) W ire Thickness (t) (m m ) Figure 10. Optimal delay/slope vs. wire thickness for alumum wire of length 7.5mm and aggressors switchg. 115

5 Delay / Slope (normalized to fat wire) 0.70 Wire Thickness (t) (m m) Delay (Active shields) Slope (Active shields) Delay (Passive shields) Slope (Passive shields) Fat wire (delay and slope) Figure 11. Optimal delay/slope vs. wire thickness for copper wire of length 3.75mm and aggressors switchg. Delay / Slope (normalized to fat wire) Delay (th wire) Slope (th wire) Fat wire (delay and slope) Wire thickness (t) (m m) Figure 1. Delay/slope vs. wire thickness for narrowed middle wire (copper) of length 7.5mm and aggressors switchg. Power (normalized to fat wire) Wire Thickness (t) (m m) Fat wire Active shields Passive shields Figure 13. Power consumption for a 7.5mm copper wire with aggressors switchg. aggressors are not switchg to the case of aggressors simultaneously switchg the opposite direction. Therefore, gas (when compared to fat wires) are reduced when there is no worst-case switchg on the aggressors especially as wires become less resistive (greater thickness). For the same reason passive shields show worsened results as wires become less resistive when there is no switchg on the aggressors. All the results dicate that as the total resistance of the wire creases, the gas through active shieldg reduce. This is demonstrated by the reduction gas for each setup as the wire thickness is reduced. For the same reason, the 7.5mm le with alumum shows less gas than the copper 7.5mm le and the 3.75mm long copper le shows more gas than the 7.5mm copper le. In current 0.18 and 0.13µm processes, repeaters are typically placed every 3-5mm to reduce delay these distances maximize the usefulness of active shieldg. For the case which the fat wire is reduced width to crease spacg from the aggressors, simulations (Figure 1) show that the delay ga is the same as active shieldg but the improvements slopes are much less than with active shieldg. The noise analysis shows that the noise immunity this case is comparable to that of active shields but not as good as passive shields. Figure 13 shows the power consumption for the configurations which the delay was optimized. The power consumption was always smallest for the passively shielded case. This is due to the fact that the actively shielded case extra drivg power is consumed by the er wires fightg the aggressors. The fat wire always consumes the most power sce it has the largest capacitance associated with it and must also fight the aggressors. A noise analysis confirmed that the active shieldg results enhanced noise immunity compared to the fat wire. However, active shields are not as good at screeng functional noise as passive shields. The drivers on the side wires present a highly resistive path to the ground and result degraded shieldg properties. 3.3 Driver and Wire Sizg Issues Convertg a fat wire or a wire with passive shields on its sides to one with active shields while matag the same footprt and capacitive load on the previous stage volves two optimizations wire widths and spacgs and distribution of the total driver size over the three wires. As was shown Figure 3, maximizg the couplg capacitance results smaller delays (due to the crease the useful Miller effect). So, the spacg between the side and middle wires should be kept mimum (as dictated by the technology constrats.) The simulation data dicates that for long les, for which the terconnect delay becomes comparable to the gate delay, the optimal solution is obtaed with fatter middle wires sce the useful couplg effect is not able to overcome the delay due to le resistance. The middle wire is as wide as possible nearly all the cases simulated (this leads to mimum width side les). In a few cases when it is not as wide as possible, the difference delays between when it is widest and the optimal width is less than 6%. Thus, optimal (or near optimal) delays can be obtaed by keepg the middle wire as wide as possible. A figure of merit would be useful determg the potential gas from different wire sizgs. The optimal driver size distribution can be obtaed with the delay model described Section. Though the delay model is not accurate terms of the delay gas, the trends terms of optimal driver sizg are similar to the simulations. Figure14 shows the delay gas compared to passive shields for different technologies usg both the analytical model and SPICE simulations. There is a close match between the predicted optimal driver sizes from the model and SPICE simulations. Table 1 shows the optimal size of the middle driver obtaed through both methods for the setup used Figure 5a. Though the model does not consider aggressors, the optimal driver size distribution should be the same dependent of the presence of aggressors. This trend is shown the simulations as well. The right-most column dicates the maximum difference delays as a percentage of optimal delay (as 116

6 Delay (normalized to passive shield delay) Delay vs Middle driver size from model and simulation t=0.45um (Model) t=0.45um (Simulation) t=um (Model) 0.70 t=um (Simulation) t=um (Model) t=um (Simulation) Middle Driver Size (W/L of NMOS) Figure 14. Comparison of delay obtaed from model and simulation with active shields for various driver sizes. obtaed through simulations) if the optimal driver size predicted by the model is used. The differences are less than 1%. Once the optimal wire sizg is decided upon, obtag the optimal driver size distribution is a relatively simple task with this fairly accurate model. A major discrepancy between the model and the simulation is that the delays predicted by the model converge to the delays usg passive shields (when the drivers of the side wires become very weak) whereas the simulations they do not. The addition of a weak driver to a shield wire results a highly resistive path to the ground through the couplg capacitance. As a result, less current is jected by the middle wire to the couplg capacitances and the delay improves even when the useful Miller effect is negligible. An improvement delay (though not by the Miller effect) can be achieved just by addg very weak verters onto the shield wires. 4. LIMITATIONS AND FUTURE WORK The biggest limitation of this work is that ductive effects are not considered. The simulated cases volved long les which the resistance may dampen much of the ductive effects, matag the results validity. However, ductance may have a large impact on the feasibility of active shields for shorter and much fatter wires, which should be considered [6]. The wire sizg problem needs to be addressed to fd optimal wire sizes with resortg to simulations. Future work will consist of cludg ductive effects to the analysis and developg a figure of merit for analytically determg the optimal wire sizg. Table 1. Comparison of optimal driver sizes for active shields obtaed by model and SPICE. Wire Thickness (mm) 5. CONCLUSIONS The concept of active shieldg was proposed. Simulation results show that convertg a fat wire to an actively shielded wire results lower delays, faster signal slopes, lower power consumption, and better noise immunity. Actively shielded wires were shown to have better performance terms of delay and signal slopes than passively shielded wires at the expense of higher power consumption and slightly degraded noise properties. A simple yet fairly accurate model was developed to obta optimal driver size distribution for actively shielded wires but the optimal wire sizg issue needs to be resolved. Future work should consider on-chip ductance. REFERENCES Optimal middle driver size(s) (W/L of NMOS) Model Simulation Maximum difference delays (%) [1] A.B. Kahng, S. Muddu, and E. Sarto, "On switch factor based analysis of coupled RC terconnects," Proc. ACM/IEEE Design Automation Conference, pp , 000. [] P.K. Green, A GHz IA-3 architecture microprocessor implemented on 0.18? m technology with alumum terconnect, Proc. International Solid-State Circuits Conference, pp , 000. [3] A. Vittal and M. Marek-Sadowska, Crosstalk reduction for VLSI, IEEE Trans. on Computer-Aided Design, vol. 16, pp , [4] L.P. P.P. van Gneken, Buffer placement distributed RC-tree networks for mimal Elmore delay, IEEE International Symposium on Circuits and Systems, vol., pp , [5] C.J. Alpert, A. Devgan and S.T. Quay, Buffer Insertion for Noise and Delay Optimization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, pp , Nov [6] Y. Massoud, S. Majors, T. Bustami, and J. White, Lay techniques for mimizg on-chip terconnect self-ductance, Proc. ACM/IEEE Design Automation Conference, pp ,