CHAPTER 1 INTRODUCTION

Transcription

1 1 CHAPTER 1 INTRODUCTION 1.1 INTRODUCTION TO RF FRONT END DESIGN Rapid growth of wireless market emerges various wireless communication systems, which demands a low power, low cost and compact transceivers capable of supporting many communication standards [1]. This necessitates the design of a wideband RF front end, which can support multiple bands of frequency [2]. It is more attractive to have a complete CMOS multiband receiver on a single chip. An incredible growth of the digital industry due to continuous scaling in CMOS technology has motivated the RF designers to develop CMOS RF analog circuits, which can be integrated along with the digital circuitry. This has led to the tremendous research and development of high reliable RF system in GHz range integrated on a single chip with less power and distortion. Further, CMOS technology is more cost effective for on-chip realization of passive elements such as capacitor and inductor. Remarkable improvement in CMOS technology triggers the RF industry towards 90nm and 45nm CMOS process. Even though this process offers reduced area and low power devices, it has the disadvantage of second order effects like short channel effects, hot carriers, substrate leakage etc. Hence, 180nm is chosen for realizing the RF systems with negligible substrate leakage and reduced second order effects.

2 2 RF Receiver Block diagram of a RF receiver shown in Figure 1.1 consists of a RF Band Pass Filter (BPF), Low Noise Amplifier (LNA), mixer, local oscillator followed by a low pass filter and baseband processing unit. The role of the receiver is to demodulate the received signal and recovers the original information impressed on the transmitter signal. The first stage of a receiver is typically a RF filter and a LNA, whose prime function is to provide good gain for the required band and to overcome the noise of subsequent stages (such as a mixer) [3]. Main functions of LNA in a radio frequency chain is to increase the signal energy and to limit noise in the receiver. It also demands low noise figure, sufficient gain with flatness over wide frequency range, low power consumption and low cost [4]. Mixer, local oscillator and low pass filter are used for down conversion of the received signal to intermediate frequency. Information is retrieved from intermediate frequency by Analog to Digital conversion (A/D) and by base band processing unit. Antenna RF Front End RF Filter Mixer IF Filter Local Oscillator A/D Base band Processing Unit Figure 1.1 Block Diagram of a RF Receiver RF Front End RF Front End is the circuitry between the antenna input terminal and the baseband processing unit of a receiver. An ideal RF front end of the receiver simply translates the incoming signal from a carrier frequency f c down to baseband [73]. The main function of the receiver RF front end is to receive and strengthen the desired band

3 3 of signal and attenuate the unwanted interferer signals. Sensitivity and selectivity are the primary concerns of RF front end. A receiver with high sensitivity can process a very weak desired signal whereas a receiver with high selectivity can process a desired signal in the presence of very strong interferers at adjacent frequencies. The required sensitivity and selectivity of a receiver are highly dependent on the circuit design specifications of RF filter and LNA. RF filter must limit the bandwidth of the input signal in order to minimize the intermodulation distortion and spurious responses. If the transmitter is far away, the strength of the received signal will be very weak. Hence a LNA is used to increase the gain of the received signal to a level needed for demodulation and also it reduces the noise figure of the signal, so as to reduce the noise in following stages. Need for Multiband RF Front End Tremendous growth of wireless communication standards has promoted the need for multiband transceivers, to integrate multiple applications on a single chip. The RF front end of such a receiver has to cover a wide range of different carrier frequencies and should capable of operating required band of frequency. To achieve this goal, wideband performance of the receiver front end is desired. A straight forward method is to use multiple input stages for each interested frequency. The advantage of the approach is that the performances of each RF front end can be optimized for each frequency band, but it suffers from area, power and cost issues. It is necessary to design a single chip, single input stage RF front end to operate for multiple bands of frequencies with less hardware, low power and low cost Existing Architectures of Multiband RF Front End Great efforts have been made to integrate all the components of RF front end on a single chip in order to reduce the power, cost and size. A number of architectures are available for integrated multiband RF front end, such as parallel RF front end, dual band concurrent RF front end and RF front ends using switched capacitors and inductors.

4 4 Parallel RF Front End Architecture of a parallel RF front end [5] is shown in Figure 1.2. The design consists of a separate path for each bands of RF signal connected in parallel configuration. Each path consists of RF filter, LNA and mixer which are operated for a particular band of frequency. Down converted signal from each path is then processed by a common baseband processing unit. Even though it has separated signal paths for various bands, only one path is active at a time. The RF filter of this architecture should be design with high selectivity (high quality factor) to provide strong attenuation and isolation towards the adjacent band of frequency. When there is a requirement of more number of bands, the number of parallel paths have to be increased, which has issues in cost, size and weight of the system. Antenna RF Filter/LNA Mixer IF/Baseband Processing Figure 1.2 Parallel RF Front End Architecture Concurrent RF Front End Block diagram of a concurrent RF front end design for dual band operation [6] is shown in Figure 1.3. It consists of a dual band filter and a dual band LNA. The dual band filter uses two resonant circuits to extract two different frequencies concurrently. The dual band LNA uses resonant circuits connected either at the input or output to match the designed dual frequency and produces amplified output. The dual band signals are then processed and demodulated by a dual band down conversion unit.

5 5 Antenna Dual Band Filter Dual Band LNA Dual Band Down Conversion Unit Base band Signal 1 Base band Signal 2 Figure 1.3 Concurrent Dual Band RF Front End Design The concurrent design requires a number of resonant circuits connected in series or parallel, either at the input or output of LNA, to amplify the dual bands of frequency. The designed resonant circuit should match the source impedance and load impedance at the input and output of the amplifier. A desirable circuit characteristic for multiband operation is obtained by simultaneous tuning of these resonant circuits. The simultaneous tuning of different frequencies suffers from spurious responses. On the requirement of more number of bands, either the number of resonant circuits or the number of dual band RF front end unit has to be increased, resulting in larger chip size. Parallel RF Front End using Switches The architecture shown in Figure 1.4 is based on parallel RF front end design which uses switches to select required path, thereby choosing the band of interest [7]. The switches are realized either by Switching Capacitor (SC) or Switching Inductor (SI) circuit. However, this architecture suffers by discontinuous tuning of the switching operations and also occupies larger area. Antenna Switches RF Filter/ LNA Mixer IF/Baseband Processing Unit (SC / SI Circuits) Figure 1.4 Parallel RF Front Design using Switches

6 RF Design Aspects RF circuits must process high frequency analog signals of wide dynamic range. When the RF circuit is designed, obviously there will be a tradeoff between the critical design parameters which are denoted as RF design hexagon [11] shown in Figure 1.5. RF system design can satisfy any one or a few of the design parameters. Figure 1.5 RF design hexagon RF design issues are: Reactance of the circuit should account the parasitic of the active devices also. Circuit losses cause degradation of quality factor (Q), which leads to the reduction of frequency selectivity and noise performance. Noise arising from RF circuit can be significant and its effects need to be considered. Poor input or output impedance matching leads to reflection and it depends on the circuit size, which is of the order of a wavelength. If a circuit suffers from reflection, a careful design is needed to avoid loss of gain, power, or failure of components. Nonlinearity causes distortion and unwanted frequency components which are undesirable. This design issue needs to be considered in filter and LNA design. Electromagnetic radiation, capacitive coupling and substrate coupling significantly alter the performance of the circuit.

7 7 1.2 RESEARCH MOTIVATION Growth of various wireless applications in consumer market utilizes Ultra Wide Band (UWB) for networking and wireless interconnection between computing devices. The Wi-Media Alliance has divided the UWB frequency range 3.1 GHz to 10.6 GHz into fourteen bands each of 500 MHz bandwidth, which are defined for long and short range commercial applications is shown in Figure 1.6. Band Band Band Band Band Group #1 Group #2 Group #3 Group #4 Group #5 Long range Applications Short range Applications Figure 1.6 UWB Band groups Fast growing wireless communication market necessitates the development of multi standard mobile units. This creates a strong interest towards the design of multiband RF front end for UWB range. It is more advantage to have a single chip of complete CMOS multiband RF front end, which can be tuned to select the required bands in UWB range suitable for applications like wireless communication between computing devices, home networking, medical applications etc.

8 8 1.3 LITERATURE REVIEW OF PREVIOUS WORK Review on Active Inductor Bryan T. Morrison discussed the simulation of inductor using resistors, capacitors and operational amplifiers which forms gyrator [12]. Gyrator is an inductor without any turns of wire. This paper discusses the advantages and disadvantages of gyrator. It gives the idea of realizing an inductor without any turns of wire. A. Thanachayanont, et al. discussed two transistor structures of gyrator (active inductor topology) [13]. The basic concept of active inductor (Gyrator-C) and its equivalent circuit is understood from this work. He had widely discussed the MOS configurations used for positive and negative transconductors of a Gyrator. Gyrator structures involving a common drain stage have greater restrictions on the voltage levels required for biasing of transistors, which has negative impact on the inductance tuning range. Circuits involving a common gate stage have a wide tuning range, but require a negative resistance for high quality inductors. His structure involves common gate and common source configurations along with a common gate MOS transistor connected in the feedback to improve the quality factor. Reported structure has an inductive bandwidth of few MHz to a maximum of 2.97GHz. S.G.E. Khoury, et al. discussed the possibility of constructing active inductors using three or more transistors [14] Y.Chang, et al. proposed an active inductor with high quality factor. He suggested a method of improving the quality factor by boosting the loop gain through feedback [15]. This gives an idea of reducing the series resistance by adding a NMOS transistor in the feedback path. H. Xiao, et al. presented a CMOS active inductor with a self resonance frequency f r = 5.7 GHz [10, 16] using gyrator topology. He used differential configuration for positive transconductance and common source for negative transconductance. Large f r is achieved using NMOS signal path. The measured quality

9 9 factor, Q was 665, but Q can be infinite theoretically. Both f r and Q were tunable via biasing and on-chip varactor. The on-chip varactors have less tuning range and occupy larger chip area. William Bucossi and James P. Becker discussed the practical considerations of CMOS active inductor realized using Gyrator topology [17]. Using transistor level simulation, this paper considered two fundamental active inductor topologies using simple grounded active and a simple cascode active inductor. The design was focussed on robustness with regard to variation with fabrication process, voltage and temperature. Simulation result reveals that the active inductor suffers significant variation in both the realized inductance value and quality factor particularly as a function of transistor variability. Further the design can work for the resonant frequency 250MHz only. R. M. Weng and R. C. Kuo, proposed a tunable CMOS active inductor for RF band pass filters [18] based on gyrator theory. Each transconductor of gyrator are realized using NMOS transistor. They suggested cascode topology for one of the transconductor to improve quality factor and tuning range. He had achieved a Q-factor of 80 at 2.4GHz. Reported structure has attanined the resonant frequencies ranges between 2 to 2.9GHz. H. Ugur Uyanik and Nil Tarim, suggested a compact low voltage high quality factor CMOS active inductor suitable for RF applications [19] using 130nm CMOS process. The schematic had two transistors connected in series between V DD and ground rails, making it very attractive for low voltage applications. To tune the inductance of the active inductor, a varactor is used, connected in such a way without affecting the parasitic series resistance of the active inductor. He has attained an inductive bandwidth reported is 300MHz to 7.32GHz with inductance range between 38 and 144 respectively. Further his structure has power consumption of 1mW. S. Hara, et al. employed only a MOSFET and a resistor for an active inductor design [20-21]. Feedback operation of active inductor was realized as follows;

10 10 increase of input current will result in an increase in the voltage at the input node, since the gate voltage is kept at V DD, V GS is reduced, resulting in lower current out of the active inductor. The major drawback of the Hara active inductor topology is the loss of voltage headroom by at least V T. Inductance is 3±0.4nH and 7.7±0.9nH for the frequency 7.6GHz and 5.5GHz respectively. M. Nair, et al. designed a typical schematic for an active inductor with a negative feedback network in cascode configuration for low power, low noise and ultra wide band amplifier applications [22]. The negative feedback network reduces the parasitic resistances of the synthesized active inductor. The circuit operates for the frequency 3-5 GHz. The capacitance C 3 was incorporated in the design where to improve the quality factor but it increases the synthesized inductance at the cost of reduced self resonant frequency. M. Abdalla, et al. introduced a feedback resistor between the two transconductors of an active inductor to improve the quality factor of the synthesized inductor [23]. The added feedback resistor increases the inductance of the active inductor and at the same time it minimizes the parasitic series resistance, thereby attained quality factor is 100. MOS varactors were used to tune the inductance and quality factor, respectively which has less tuning range of 1 to 2.9GHz. Chun Lee, et al. discussed single ended inductor incorporating Feed Forward Current Source (FFCS) technique for better linearity [59]. The design achieved a Q factor of 200 at 2.85GHz. However the topology suffers from excessive parasitic capacitance and conductance, which in turn decrease the Q factor. Komeil Rasouli, et al. presented a differential active inductor using 180nm CMOS process. The inductance L ranges from 1 to 70nH and has operated for the self resonant frequency 2.6 GHz. The maximum power consumption is 12mW for L=10nH.

11 11 Techniques of designing tunable active inductor using gyrator circuit are studied. The design criteria are frequency of operation, tuning range, noise, power and quality factor. Gyrator topology of realizing an inductor using active elements has conceived from Ref [12], but he used operational amplifiers which occupies larger area and power. Gyrator is realized by connecting a positive transconductor and negative transconductor connected back to back from Ref [13], but the design has less inductive bandwidth. Differential configuration of MOS transistors can be used as positive trasconductor from Ref [10] which is less sensitive to noise and interference, but attained less tuning range. Series reistance of inductor can be reduced by using a feedback transistor [15] in order to increase the quality factor. The techniques of these literatures are used in proposed design of active inductor to improve the quality factor, inductive bandwidth, inductance range and to operate at high resonant frequency with tuning capability Review on Band Pass Filter Bogdan Georgescu, et al. presented a tunable Q enhanced filter using onchip spiral inductors [24]. The quality factor of on-chip spiral inductors, which form the filter resonators was enhanced using a cross coupled differential pair. At the center frequency of 2 GHz, the reported inductor Q factor is 10 and the noise figure is 15dB with the power consumption of 17mW. As, the circuit uses passive on-chip spiral inductors, the design occupy larger area and also suffered from difficulty in center frequency tuning. S. Bantas, proposed a fully integrated active LC BPF based on the triple coupled spiral inductor topology [25]. The tuning range of the center frequency is only 11% around 1GHz with a power consumption of 12.2mW. V. Aparin, et al. designed a widely tunable filter using varactors tunable control circuits for frequency-tuning and Q factor tuning [26]. Reported tuning ranges

12 12 are and GHz bands with 3-dB bandwidths of 86±6 and 126±1.0 MHz. The use of varactors consumes area and it has less tuning range. Peyman Pourmohammadi, et al. discussed a third order BPF design using top coupled topology [27], an idea of using active inductors as resonant circuits in BPF was derived from this paper. The circuit is operated only for the frequency 2GHz with a less gain of 0.3dB. Zhiqiang Gao, et al. presented a wide tuning BPF using active inductors [28]. The structure consists of three stages, including two differential active inductors, negative impedance and buffers. Design issues such quality factor enhancement and noise related to active inductor based BPF were discussed. Reported tuning range is 1.92 to 3.82 GHz and consumed a power of 10.8mW. It had achieved noise figure of 18dB with a mid band gain of 6dB. H. Xiao, et al. discussed 5.4 GHz BPF using active inductor [10]. BPF was implemented by connecting an active inductor between input transconductor G m, and an output source follower. The transconductance of the transistors were varied through the varactors, which varies the center frequency and quality factor. The use varactors resulted in less tuning range and larger area. Further the filter operated at 5.7GHz with Q=100 and midband gain of 4.7dB. Santosh Vema Krishnamurthy, et al. discussed a pseudo differential RF BPF implemented using active inductor [29]. Active inductor was designed with noise cancellation circuit. It achieved a low noise figure of 5dB and the circuit operates for a frequency 3.46 GHz only. Y. Wu and M. Ismail, proposed the design of active RF filter based on the simulated inductor [30]. A dc coupled negative resistance implemented using cross coupled pair of NMOS transistors, used to tune the quality factor of the filter. The direct coupling of the negative resistance to the active inductor had an adverse effect of changing the biasing of the transistors of the active inductor due to direct coupling. And

13 13 also variations of negative resistance for quality factor tuning leads to the changes in center frequency. Idea of constructing RF BPF using active inductor was obtained from above work. Reported tuning range is 400MHz to 1.1GHz for Q factor 2 to 80 with a gain and noise power of -15dB and -72dBm respectively. C. Andriesei,et al. presented a design of BPF using active inductor in differential configuration [31]. An independent tuning of quality factor and center frequency was achieved through two negative resistances. Keeping one of the negative resistances as constant and changing the second, an independent tuning was achieved. It had achieved a less tuning range of 600MHz to 2.4GHz with a power consumption of 1mW. M.M. Reja, et al. presented a wideband band pass filter/amplifier using two active inductors, connected back to back through a coupling capacitor [77]. By controlling a voltage source, the resonant peak of the BPF is tuned to operate as amplifier. The response of the filter is only for the frequency 3GHz. Designs of RF BPF using different topologies were studied. Tuning range, power, center freqeuency tuning range, bandwidth and noise figure were considered as the design criteria for RF BPF design. The resonant circuits of RF BPF is tuned to select the band of interest for multiband RF front end design. Tuning can be done through varying capacitance or inductance of the resonant circuits. It is studied from the literatures that the varactor tuning has less tuning range. Reported results of Ref [28, 29, 30, and 31] shows tuning of inductance through active inductors has wide tuning range. Top coupled topology discussed in Ref [27] is considered to be suitable for connecting the proposed active inductor back to back as in Ref [77] for the design of RF BPF.

14 Review on Wide band LNA C. W. Kim, et al. discussed a common source stage with resistor shunt feedback technique [32] for wideband LNA design. Resistive feedback combined with degenerative source inductance with a wide band input matching for the frequency range 3 to 5 GHz. Further, an additional noise contributed by the feedback resistor R f in the design was one of the limitations of the topology. The circuit had achieved a noise figure of 2.3dB and gain of 9.8dB. To cover wide frequency range 3 to 10 GHz, feedback resistor value need to be lower and the transconductance of the common source amplifier need to be raised. Thereby, width of the transistor has to be increased, results large area. Y. Lu, et al. [34] and B. Park, et al. [35] reported a common gate topology for wideband LNA design. The design achieved a wideband matching by setting the input transistor transconductance reciprocal to the source resistance. Additionally, it needs wide band high impedance biasing to reduce the significant loss of RF signal. Hence, increase in noise figure and power consumption. G. Sapone, et al. discussed a current reused two stage LNA [33, 36], and results reported a low power consumption 7.2mW with a gain of 12.5 at 7.6GHz.The noise figure varied from 3-7dB for wide band of 2.6 to 10.2 GHz with a reverese isolation of -45 db. Yo-Sheng Lin, et al. reported a two stage inverter based LNA with three inductors achieves less noise figure but the gain was not sufficient [37]. J.H. Lee, et al. proposed a two stage LNA design. It consists of cascode amplifier followed by a resistive feedback common source amplifier [38]. It covers UWB frequency range from 3.1 to10.6 GHz. An inductive peaking technique was discussed. The design dissipated 22.7mW power and attained input return loss (S11) of -9.7 to db for a forward gain of 11.4dB and noise figure of 4.12 to 5.16dB over 3.1 to 10.6GHz.

15 15 Wang Chunhua, et al. discussed UWB LNA [39], the circuit consists of a two simple amplifiers with an inter stage inductor. The first stage is a resistive current reuse common source amplifier with a dual inductive degeneration technique to attain a wideband input matching and low noise figure. A common source amplifier with an inductive peaking technique as the second stage achieves a high flat gain and wide 3 db bandwidth. I. A. Galal, et al. discussed a two stage wide band LNA for a bandwidth of 1 to 5 GHz [40]. The first stage was a resistive shunt feedback cascode stage and the second stage was a common source amplifier with an active inductor load. However, the design operates for less bandwidth 1 to 5 GHz and achieved a less gain 13dB having a noise figure of 3.8dB. Yi-Jing Lin, et al. proposed a 3.1 to10.6 GHz UWB LNA utilizing a current reused technique and a simple high pass input matching network [41]. Even though, the current reuse technique reduced the power consumption, the circuit had a power gain of 16dB. For multiband operation, LNA had a gain greater than 20dB. Single LC section was employed for input impedance matching, the input return loss S 11 achieved was less than -8dB. This has to be further reduced for good input impedance matching and may not have good matching responses at low frequency range of UWB range. Yousef, K., H. et al. [42], proposed a current reused cascade amplifier, offered a gain of 12dB over a large bandwidth of 2.5 to 16 GHz with a reduced noise figure 3.3 db. Eventhough it had attained good input and output matching with good isolation, the design had consumed a large power and suffered from poor linearity. Galal, et al. employed a two stage LNA. Inverter with resistive feedback as first stage used for wide band matching and a cascode amplifier as second stage for highly linearity [43]. The design reported input return loss of -11dB, output return loss -8dB, noise figure of 3.5dB and gain of 15dB.

16 16 H.C. Zhan, et al. presented a resistive feedback LNA for wireless applications [72]. A 5GHz broadband LNA achieved 25dB gain, 2dB NF, -14dBm IIP3 and -13dB S11. Different topologies of wideband LNA were studied. Gain, bandwidth, noise figure, input matching for wide band of frequencies and power consumption were considered as performance parameters of wide band LNA. Concept of current reuse technique was studied from Ref [41, 42]. It is observed that, an input impedance of LNA should match with source impedance 50Ω for wide band of frequencies. High pass matching network in Ref [41] and inverter using resistive feedback in Ref [43] as wide band input matching network attains poor responses at lower frequency end. Two stage LNA proposed in [40] had good gain but has less bandwidth Review on Multi band Radio Frequency (RF) Front End Raik Richter, et al. discussed the old method of parallel RF front end for multiband operation [44]. This method had a separated signal path whereas, only one path was active at a time. So, the receiver can get optimum performances for each standard. Hossein Hashemi, et al. discussed concurrent method for dual band 2.45 and 5.25GHz RF front end [6]. Desired circuit characteristics at multiband were simultaneously obtained by adding resonant circuit(s) in series (parallel) with the input (output) matching network. The design reported voltage gain of 14 and 15.5 db with a noise figure of 2.3 and 4.4 db for the two bands respectively. However, the circuit suffered from spurious response. Chong-Ru Wu, et al. proposed a multiband front end, in which LNA was designed with broadband input impedance matching for 3 to 5 GHz. Tunable load at the output was employed to provide the required narrow band amplification. [45].

17 17 Varactors were used for tuning the load impedance. The design had a less tuning range of 3 to 5 GHz with a power consumption of 16mW. Changjae Kim, et al. employed switched capacitor array and switched inductor array for multiband selection [7]. Nevertheless, it suffers from a large power consumption, discontinuous tuning and occupies larger area. Moreover, many switches were needed for the selection of different bands. Switched capacitor or inductor suffer from charge injection and charge leakage problems. Stefan Andersson, et al. presented a flexible RF sampling front end for WLAN operating in 2.4 GHz and from 5 to 6 GHz bands [46]. The circuit was implemented in a 0.13 µm CMOS process, which consists of a wideband LNA and a switched capacitor discrete time decimation filter were used as a sampling IQ down converter. The design was operated at a sampling frequency of 3 GHz and RF carrier of 6 GHz. The gain, linearity, noise figure of whole front end was measured and reported power consumption was 176 mw. Since the circuit employed switched capacitor circuits for different bands of operation, the consumption of more power and area was observed. Robert Malmqvist, et al. investigated a tunable band pass LNAs using RF MEMS switches [47]. Instead of transistor switches for tuning, the circuit employed RF MEMS switches for multiband and reconfigurable front ends for flexible RF systems. It consumed a high dc power of mw and achieved a less tuning range from 4.87 to 6.20 GHz. Mikko Hotti, et al. used a parallel RF front end with wide band mixer [48]. The mixer is reconfigurable for different band of frequencies. The wider operating frequency lowers the performance. Hence, the system requires more design consideration for LNA design, to have high gain and lower noise figure to compensate for the performance of wide band mixer. Rahul Magoon, et al. reconfigurable mixer method [49]. proposed a parallel RF front end method with GSM 850/GSM 900 use reconfigurable mixer

18 18 method and DSC1800/PCS1900 use parallel RF front end method. This method can support wide band operation but it had many components and large size. Jiandong Ge, presented a design of integrated RF front end, in which an input transconductor drive an on-chip LC BPF replacing off-chip BPF [50]. In the design the input transconductor convert a voltage input in to a current output. The current then drive an on-chip LC BPF. The input transconductor provide the impedance matching for LNA. The BPF design includes a tunable LC resonator and a Q enhancement circuit to increase the quality factor with the purpose of tuning the filter bandwidth. Tuning range is 3.53 to 3.88GHz with gain of 30dB and noise figure 15dB. It consumed high power of 120mW. Various architectures of multiband RF front end were studied. It is observed that parallel or concurrent architectures occupy larger area and tuning made through varactors or switches has less tuning range. It is found that the single path multiband RF front end design as Ref [50] is more suitable for wideband applications. 1.4 PROPOSED ARCHITECTURE OF MULTIBAND RF FRONT END One of the key issues in designing a multiband receiver is how to implement a single chip highly integrated RF front-end that can operate at low power consumption. Although dual-band receivers that have good signal isolation and use band selection architecture or a parallel arrangement of several receivers have been developed, these approaches cannot lead to the development of compact low power, low cost system. To achieve a compact low power multiband receiver, the signal separation for the multiple bands on a single RF signal is a key technique. To satisfy the above criteria, a proposed design for multiband RF front end using wideband approach is described in Figure 1.7.

19 19 Antenna UWB LNA Tunable RF BPF using Active Inductor To other blocks (Mixer, IF Base band processing) Figure 1.7 Proposed RF Front End Design UWB LNA with a wideband matching network at its input produces an amplified flat frequency response for wideband of frequencies. It should provide a sufficient gain and noise figure for wideband in order to reduce the noise in subsequent stages. A Tunable RF BPF is placed at the output of UWB LNA to select required band of frequency from the wideband signal. BPF is designed using resonant circuits, which can be tuned to select the bands of interest with a less noise figure. The resonant circuits which are realized using on-chip spiral inductors [8], finds difficult to realize it for larger inductance values, high quality factor and smaller chip area [9] and also suffers hard to tune. Hence, for wide range of tuning, the resonant circuits of BPF can be realized using Active Inductors. It features wide range of tuning capability, high resonance frequency, high quality factor and smaller chip area. The advantage of selecting this wideband approach is that, both the blocks are independently manageable and can achieve accurate selection of different center frequencies of wideband [64]. Design of a single path multiband RF front end with less noise, high tuning range and low power consumption is a challenging task.

20 DESIGN SPECIFICATIONS OF PROPOSED DESIGN The technical specifications for the blocks of UWB front end is derived from link budgets of mode 1 device (mandatory mode) for group #1 of first 3 bands and mode 2 devices (optional mode) for the groups #2 to #4 of bands 4 to 10 of Figure 1.6 published in MBOA proposal [74] and in multiband OFDM physical layer proposal [75] respectively. Table 1.1 gives the link budget of mode 1 and table 1.2 gives the link budget for mode 2 devices. Parameter: Mode 1 Devices (3- band) Table 1.1 Link Budget for Mode 1 Device Value Value Value Information data rate (R b ) 110 Mb/s 200 Mb/s 480 Mb/s Rx power P P G G L 1 L ( R T T R 2 Average noise power per bit ( N 10* log ( R ) ) b (db)) Rx Noise Figure Referred to the 6.6 db 6.6 db 6.6 db Antenna Terminal ( N ) 1 Average noise power per bit P N N ) ( N F F Required E b /N 0 (S) 4.0 db 4.7 db 4.9 db Implementation Loss 2 (I) 2.5 db 2.5 db 3.0 db Link Margin ( M P P S I R N ) 6.0 db 10.7 db 12.2 db Proposed Min. Rx Sensitivity Level m 1 The primary sources for the noise figure are the LNA and mixer. The voltage gain of the LNA is approximately 15 db. The total noise at the output of the LNA is V 2 /Hz. This value includes the noise of the LNA and the input of resistor. Thus, the overall noise figure for the analog front-end is 10log 10 (7.22/2.56) = 4.5 db. Including the losses associated with the pre-select filter (1.1 db), mixer (0.4dB) and the transmit/receive switch (0.6 db), the overall noise figure is 6.6 db.

21 21 2 Includes losses due to cyclic prefix overhead, front-end filtering, clipping at the DAC, ADC degradation, channel estimation, clock frequency mismatch, carrier offset recovery, carrier tracking, etc. Parameter: Mode 2 DEV (7- band) Table 1.2 Link Budget for Mode 2 Device Value Value Value Information data rate (R b ) 110 Mb/s 200 Mb/s 480 Mb/s Rx power PR PT GT GR L 1 L (db)) ( 2 Average noise power per bit ( N 10* log ( R ) ) b Rx Noise Figure Referred to the 8.6 db 8.6 db 8.6 db Antenna Terminal ( N ) 1 Average noise power per bit P N N ) ( N F F Required E b /N 0 (S) 4.0 db 4.7 db 4.9 db Implementation Loss 2 (I) 2.5 db 2.5 db 3.0 db Link Margin ( M P P S I R N ) Proposed Min. Rx Sensitivity Level 5.3 db 10.0 db 11.5 db m 1 The primary sources for the noise figure are the LNA and mixer. The voltage gain of the LNA is approximately 15 db. The total noise at the output of the LNA is V 2 /Hz. This value includes the noise of the LNA and the input of resistor. Thus, the overall noise figure for LNA is 10log 10 (9.09/2.56) = 5.5 db. Including the losses associated with the pre-select filter (1.8 db), mixer (0.4 db) and the transmit/receive switch (0.9 db), the overall noise figure is 8.6 db. 2 Includes losses due to cyclic prefix overhead, front-end filtering, clipping at the DAC, ADC degradation, channel estimation, clock frequency mismatch, carrier offset recovery, carrier tracking, etc.

22 22 The required overall NF and voltage gain of the receiver are determined from the UWB link budget of the proposals [74, 75], the next step of the system level design is to determine the specifications of each building block. The targeted technical specifications of the building block UWB LNA and Tunable RF BPF for the desired frequency band, gain, NF and power consumption as listed in Table 1.3. Table 1.3 Technical Specifications of the Blocks of Proposed Design Parameters UWB LNA Tunable RF BPF RF Front End Frequency Band 4 13 GHz 4 10 GHz 4-10GHz (5 bands each of bandwidth 500MHz) Gain 15dB 5dB 20dB Noise Figure 5 db 10dB 8.6 db Power 18mW 3mW 23mW consumption Process TSMC 180nm TSMC 180nm TSMC 180nm *TSMC (Taiwan Semiconductor Manufacturing Company)

23 RESEARCH OBJECTIVES To design and analyze the performance of a single path tunable multiband RF front end, which can select different UWB bands for different applications using TSMC 180nm CMOS process. The research objectives are: a) Center frequency of RF BPF is tuned through active inductors. To design, simulate and analyze a CMOS tunable active inductor with high inductive bandwidth ranging from a few MHz to GHz, quality factor greater than 600 and power consumption less than 1mW. To obtain layout of the designed active inductor using Cadence design suite. b) To design, simulate and analyze a tunable BPF using CMOS tunable active inductor design to select bands of interest of UWB range with power consumption less than 3mW, noise figure less than 10dB and good linearity. c) To design and analyze an UWB LNA with a wide band matching network and noise cancellation techniques to achieve a noise figure of less than 5dB and a gain greater than 15dB. d) Integrating the UWB LNA in (c) with the tunable BPF (b) to obtain a single path tunable RF front end, to select the required band of UWB range.

24 DESIGN FLOW AND METHODOLOGY The design flow shown in Figure 1.8 describes the sequence of steps in the design of proposed circuits. Figure 1.8 Design Flow of Proposed Design The function of each step is briefly describes as follows: Schematic entry is through the netlist in SYNOPSYS HSPICE RF tool for active inductor, band pass filter and RF front end. UWB LNA schematic is entered in ADS (Advance Design System) RF tool. The circuits are simulated using SYNOPSYS HSPICE RF and ADS for the respective circuits. The layouts of the circuits are extracted using CADENCE Virtuoso XL.

25 25 Design Rule Check (DRC), Layout vs Schematic (LVS) and RCX (Parasitic RC extraction) has been done for Active inductor, BPF and multiband RF front end using CADENCE ASSURA. The methodology used for the proposed designs are listed as follows: i. Design of tunable active inductor using CMOS transistors based on Gyrator C topology. ii. Tunable BPF based on coupled resonator topology is designed using tunable active inductors. iii. Design of wideband matching network for UWB range. Design of UWB LNA with two stage cascode topology with current reuse and noise cancellation technique. The circuit performance is analyzed using scattering parameters and its layout is obtained using Agilent ADS software. iv. To analyze the multiband RF front end by integrating UWB LNA and tunable RF BPF using Synopsys HSPICERF simulator software. 1.8 ORGANISATION OF THE THESIS Chapter 1 discusses the significances of multiband RF front end, motivation, review on active inductor, RF BPF, wide band LNA and multiband RF front end, followed objectives, design specifications, design flow and methodology of the research. Design, analysis and simulation of active inductor will be dealt in chapter 2. In this chapter, single ended active inductors are proposed and their performance parameters are analyzed using Synopsys HSPICE simulator. Parasitic extraction layouts of the active inductors obtained using Cadence design suite are illustrated. Chapter 3 discusses the design and implementation of tunable RF BPFs using active inductors tuned to select the UWB bands. The characteristic parameters of

26 26 tunable BPF such as noise, linearity and power consumption for UWB bands are analyzed. The circuits are implemented using Cadence design suite and their parasitic layouts are extracted. Chapter 4 explains the design of UWB LNA with broad band matching network of bandwidth from 4 GHz to 13GHz. The analysis of characteristic parameters of the LNA from its simulation results is dealt. Performance analysis of multiband RF front end design using the proposed UWB LNA and the tunable RF BPF using active inductor are discussed in chapter 5. Concluding remarks and future work are given in chapter 6.