Finding Loop Gain in Circuits with Embedded Loops

Transcription

1 Finding oop Gain in Circuits with Embedded oops Sstematic pproach to Multiple-oop nalsis bstract Stabilit analsis in eedback sstems is complicated b non-ideal behaior o circuit elements and b circuit topolog. Circuit elements not generall uni-directional transmit a eedorward signal as well as the eedback signal o interest. These signals and node loading must be included in the ull analsis. While analsis o single loop designs has been demonstrated to be complete, embedded and multi-loop designs hae not been so treated. This paper etends stabilit analsis to these more general designs using Driing Point Impedance and Signal Flow Graphs to ind closed orm solutions and to deine circuit conigurations or simulator generation o loop gain actors. Kewords-eedback, stabilit, phase margin, embedded loop, driing point impedance, signal low graph, dpi/sg I. INTRODUCTION Feedback sstems are generall analzed ollowing H. Black s description based on ideal non-loading and uni-directional blocks, Figure. s in ( Figure : General Ideal Feedback Sstem The transer unction or this sstem is gien as: ሻݏሺܪ ܣ ( ͳ ܣ The unction in the denominator 0 (s is the sstem loop gain G(s. s this unction approaches ngle 0 the transer unction increases in magnitude becoming sensitie and possibl unstable. The degree o stabilit is measured as the phase margin o this unction, the angle dierence rom 0 degrees at magnitude. [] Black, HS, Stabilized Feedback mpliiers, Bell Sstem Technical Journal, Vol 3, Januar 934. (2 o gustin Ochoa Ramtron International Corp Carlsbad C, US From an ideal block description it is eas to open the loop, drie one end, and look at the return response as G. Compleities arise in real circuits where loading and bidirectional nature o circuit elements must be considered. The eedback element in Figure loads both and ports o the ampliier and allows a eed-orward as well as a eedback signal to propagate, as does the ampliier. I we simpl open the loop we change the impedance enironment at some nodes and ma not account or some bi-directional signals. The open loop gain approimation to G is dependent on where the loop is broken and to the etent that the elements dier rom ideal behaior, passie as well as actie, and how we terminate the loop. sstematic approach to eedback analsis or single loop sstems using driing point impedance and signal low graphs, dpi/sg 2, has preiousl been demonstrated. In this paper we etend this approach to include multiple loop conigurations. Section II shows that what ma seem like a proper loop gain unction etracted rom a signal low graph ma be incorrect and we identi the proper loop gain. In section III we show that the proper loop gain unction can be obtained rom a node impedance analsis. In Section IV, a simulation test bench setup or obtaining loop gain actors is presented and in Section V the process is demonstrated in the analsis o a common mode eedback loop. We conclude and summarize in Section VI. II. MUTIPE OOP FEEDBCK THE PROPER OOP GIN Consider the two amp embedded eedback coniguration shown in Figure 2. Stage 2 has local compensation producing an internal loop embedded in the major loop that contains both ampliiers, a oltage regulator topolog. in - + n c stg stg 2 - r r 2 Figure 2: Two mp Internall Compensated Sstem [ 2] Ochoa,., nalzing Feedback: Properl Simulating the Open oop, MidWest Smposium on Circuits and Sstems, 998. n2 c i oad

2 signal low graph or this topolog is shown in Figure 3 (using simpliied amp model parameters g m, g o, etc.. We can sole the graph or the sstem transer unction in the orm o ( b irst collapsing the inner loop and identi a potential loop gain unction G as ( 2: Figure 3: Flow Graph or the Two mpliier Internall Compensated oop r sc r ( sr c g sr ( c c G r sc r sc ( sr c g sr ( c c ( K g m ( 2 We could instead perorm dierent graph algebra irst transorming this graph into an equialent one beore soling the graph. Consider or eample combining the two eedback paths into one block containing the sum o the original eedback paths, (Kg m +sc. This leads to a dierent unction that can be identiied potentiall as the sstem G, G 2 shown in ( 3. r ( sc 2 r K g m m sc G2 ( ( 3 sr c g sr ( c c These and other ariants can be better seen using a simpliied algebra b grouping the blocks in the direct path as and renaming the two eedback paths B or sc and C or Kg m. The combined eedback o B+C orm results in transer unction: H ( s ( 4 combined ( B C The unction subtracted rom one in the denominator becomes the potential loop gain unction. The collapse o the inner loop irst transer relation is: ( 5 H s B separate ( C B For the graph algebra satisied with paths B and C interchanged we obtain et another orm: H separate _ 2 ( s C B C ( 6 reealing et another potential loop gain. This pseudoequialenc is another source o conusion in recognizing the appropriate loop gain unction in circuits containing internal loops rom signal low graphs. Graph manipulations result in equialenc onl between ariables that are not aected b the transormation. Here the / transer unction remains constant but internal ariables and unctional orms that are modiied b the transormation do not. From ( 4 we see that combining the eedback paths results in the transer unction orm that we get rom using Mason s Rule to reduce the algebra o the graph while ( 5 shows that maintaining the eedback paths separate keeps the pole due to the embedded loop (B in the denominator unction. The orm in ( 6 conuses the inner loop with the outer eedback path so that the topolog grouping is not maintained. O these results the transer unction in ( 5 is seen to maintain the circuit grouping as we traerse the outer loop and is the onl proper loop gain, ( 2. To ind the sstem loop gain it is necessar to maintain the low graph in its most primitie orm keeping embedded loops closed properl so that the relect the circuit topolog. III. OOP GIN FROM DRIVING POINT IMPEDNCE NYSIS The driing point impedance o a eedback sstem is a unction o the sstem loop gain and can be used to etract the proper loop gain. This approach is deeloped here. First consider a single two port, Figure 4, and its small signal model, Figure 5. i i 2 Figure 4: General Two-Port Block 2 gm 2 gm 2 Figure 5: Small Signal -parameter Model or the General Two Port Block

3 B shorting to we orm a eedback sstem, Figure 6. I we now ecite the circuit with a current source we can ind the driing point impedance looking into the shorted node as the oltage response. This DPI is a unction o a local impedance Z and the sstem loop gain, ( 7, rom which we ind the loop gain to be as gien in ( 8. Since this DPI Z is a direct unction o the proper loop gain, the unction we obtain rom the port impedance is the correct loop gain unction. I ( 9 test I test ( 2 2 ( In this last orm we separate the admittance components to gnd rom cross-coupled transconductance tpe. low graph or this relation is shown in Figure 9. i test /( + 2 i in -( gm 2 gm 2 Figure 6: Two Port with Input Shorted to Output Z ' Z G G g g ( 7 m 2 ( 8 g To etend this to an arbitrar circuit as depicted in Figure 7 we irst ind a wire in the outer eedback loop and maintain internal loops closed. To ind the DPI Z we appl a oltage source to node and split the node as shown in Figure 8. We write or the total current I test equation ( 9. Figure 7: rbitrar Feedback Circuit with wire in the Outer oop. 2 Figure 9: Flow Graph or Port Impedance Z From this graph the loop gain is seen as the product o the two blocks in the loop. The cross terms 2 and 2 are unctionall equialent to g and g in ( 8. With the driing source set to unit magnitude loop gain G is seen to be the negatie o the sum o the cross currents (g m s diided b the sum o the sel-currents (to- gnd. ( 2 2 G ( 0 ( i2 i i i 2 IV. OOP GIN SIMUTION BENCH oop Gain actors can be obtained rom SPICE simulations directl. We can insert an isolation inductor and port coupling capacitors o large magnitudes as shown in Figure 0 and perorm two ac sweeps, one with 2 zero while sweeping in requenc and the second with zeroed sweeping 2. These simulations can be done in one run and the response currents combined as deined in ( 0 using the simulator s calculator or b eporting the response ariables to a math engine such as Matlab. i is current into node due to ecitation, a transconductance or cross current, while i is current into node due to ecitation at, a to-gnd current. 2 i i 2 2 Figure 8: To Find Port Z at Split the Node and ppl Two Sources. Figure 0: Simulation Coupling o ac Sources to Broken Circuit Node

4 V. COMMON MODE FEEDBCK EXMPE This technique is applied to a common mode eedback loop in a P dierential loop ilter and charge-pump block shown below. The reerence current in the pull down charge pump current source nmos diode is corrected b the eedback common mode oltage signal (generated at the loop ilter b a transconductance ampliier driing the oltage at cm to re, Figure. re cm Figure : Simulation Setup or a Common Mode Feedback oop top-leel test bench or this block is shown in Figure 2. The loop is opened in the outer path at, duplicated and drien as discussed aboe. The transconductance ampliier is a simple pmos dierential stage. The charge pump dries the dierential loop ilter through a switching network controlled b the phase detector set to short the loop ilter terminals or common mode ecitation. The common mode oltage cm is generated rom two source ollower buers and resistor summers (not shown. The sel and cross currents are combined to create the loop gain unction plotted in Figure 3 as magnitude and phase. The loop gain reaches unit at MHz Figure 3: Simulation Response or CP Common Mode oop Gain, Magnitude and Phase Showing 7 Degrees o Phase Margin VI. CONCUSION Sstem loop gain unctions are used to deine stabilit o eedback sstems. Obtaining this unction is complicated b loading eects, bi-directional transmission in elements, and b circuit topolog. technique using driing point impedance and signal low graphs has been used preiousl to ind loop gain unambiguousl or single loop sstems. Multi-loop sstems had not been sstematicall soled or loop gain. In this paper algebra perormed on a primitie low graph or multi-loop sstems is shown to generate unctions that are not the proper sstem loop gains loop gain poles ma be cancelled or improper grouping o eedback paths occur changing eedback path associations. In this paper we hae deeloped the general multi-loop sstem loop gain rom a driing port impedance perspectie. Signals generated in a wire in the outer eedback loop are identiied as sel and cross currents induced to ind the driing point impedance at a wire in the outer loop as: G=the negatie o the sum o the cross currents (g m s diided b the sum o the sel-currents (to- gnd. This approach maintains internal loops closed thereb generating the proper loop gain unction. oltage regulator topolog is analzed with this approach to ind the loop gain in closed orm. Simpliied deice models were used to keep the algebra tractable. with a phase o 7 degrees. Figure 2: Simulation Test Bench or Feedback oop, Charge Pump Common Model To ull ealuate sstem loop gain it is necessar to include complicated deice models thereb generating complicated algebra. This ull model analsis can be done using a circuit simulator such as SPICE. simulation bench containing two sstems is created to demonstrate the approach to obtain the sel and cross currents to ind the proper loop gain rom one simulation run. This approach is demonstrated using a pll common mode eedback loop.

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