High Speed Voltage Feedback Op Amps

Transcription

1 MT056 TUTORIAL High Speed Voltage Feedback Op Amps In order to intelligently select the correct high speed op amp or a given application, an understanding o the various op amp topologies as well as the tradeos between them is required. The two most widely used topologies are voltage eedback (VFB) and current eedback (CFB). An overview o these topologies has been presented in previous tutorials (MT050, MT 05, MT052), but the ollowing discussion treats the requencyrelated aspects o the two topologies in considerably more detail. HIGH SEED VOLTAGE FEEDBACK (VFB) O AM TOOLOGIES A voltage eedback (VFB) op amp is distinguished rom a current eedback (CFB) op amp by circuit topology. The VFB op amp is certainly the most popular in low requency applications, but the CFB op amp has some advantages at high requencies. We will discuss high speed CFB in detail in Tutorial MT057, but irst the more traditional VFB architecture. Early IC voltage eedback op amps were made on "all NN" processes. These processes were optimized or NN transistors the "lateral" N transistors had relatively poor perormance. Some examples o these early VFB op amps which used these poor quality Ns include the 709, the LM0 and the 74. Lateral Ns were generally only used as current sources, level shiters, or or other noncritical unctions. A simpliied diagram o a typical VFB op amp manuactured on such a process is shown in Figure below. v in v i v a C X v out V REF u u CL 2πC SR C Figure : Voltage Feedback (VFB) Op Amp Designed on an "All NN" IC rocess Rev.0, 0/08, WK age o 0

2 MT056 The input stage is a dierential pair (sometimes called a longtailed pair) consisting o either a bipolar pair (Q, Q2) or a FET pair. This "g m " (transconductance) stage converts the smallsignal dierential input voltage, v, into a current, i, and its transer unction is measured in units o conductance, /Ω, (or mhos). The smallsignal emitter resistance, r e, is approximately equal to the reciprocal o the smallsignal g m. The ormula or the smallsignal g m o a single bipolar transistor is given by the ollowing equation: q q I g ( I ) T m C, or Eq. re kt kt 2 I g T m, Eq. 2 26mV 2 where is the dierential pair tail current, I C is the collector quiescent bias current (I C /2), q is the electron charge, k is Boltzmann's constant, and T is absolute temperature. At 25 C, V T kt/q 26 mv (oten called the thermal voltage, V T ). As we will see shortly, the ampliier unity gainbandwidth product, u, is equal to g m /2πC, where the capacitance C is used to set the dominant pole requency. For this reason, the tail current,, is made proportional to absolute temperature (TAT). This current tracks the variation in r e with temperature thereby making g m independent o temperature. It is relatively easy to make C reasonably constant over temperature. The Q2 collector output o the g m stage drives the emitter o a lateral N transistor (Q3). It is important to note that Q3 is not used to ampliy the signal, only to level shit, i.e., the signal current variation in the collector o Q2 appears at the collector o Q3. The collector current o Q3 develops a voltage across high impedance node A, and C sets the dominant pole o the ampliier. Emitter ollower Q4 provides a low impedance output. The eective load at the high impedance node A can be represented by a resistance, R T, in parallel with the dominant pole capacitance, C. The smallsignal output voltage, v out, is equal to the smallsignal current, i, multiplied by the impedance o the parallel combination o R T and C. Figure 2 below shows a simple model or the singlestage ampliier and the corresponding Bode plot. The Bode plot is conveniently constructed on a loglog scale. age 2 o 0

3 MT056 v in v C i v R T X v OUT NOISE GAIN G A O O 6dB/OCTAVE O 2πR T C u 2πC u CL u UNITY GAIN FREQUENCY u G CLOSED LOO BANDWIDTH CL Figure 2: Model and Bode lot or a VFB Op Amp The low requency breakpoint, O, is given by: o. Eq. 3 2πR C T Note that the high requency response is determined solely by g m and C : v out g v m. Eq. 4 jωc The unity gainbandwidth requency, u, occurs where v out v. Letting ω 2π u and v out v, Eq. 4 can be solved or u, u g m. Eq. 5 2πC We can use eedback theory to derive the closedloop relationship between the circuit's signal input voltage, v in, and its output voltage, v out : age 3 o 0

4 MT056 vout ω. Eq. 6 vin j C g m At the op amp 3 db closedloop bandwidth requency, cl, the ollowing is true: 2πcl C, and hence Eq. 7 g m cl, or 2πC Eq. 8 cl u. Eq. 9 This demonstrates the undamental property o VFB op amps: The closedloop bandwidth multiplied by the closedloop gain is a constant, i.e., the VFB op amp exhibits a constant gainbandwidth product over most o the usable requency range. As noted previously, some VFB op amps (called decompensated) are not stable at unity gain, but designed to be operated at some minimum (higher) amount o closedloop gain. However, even or these op amps, the gainbandwidth product is still relatively constant over the region o stability. Now, consider the ollowing typical example: 00 µa, C 2 pf. We ind that: I / 2 50μA g T m Eq. 0 V 26mV 520Ω g m 2πC T 2π(520)(2 0 u 2 ) 53MHz. Eq. Now, we must consider the largesignal response o the circuit. The slewrate, SR, is simply the total available charging current, /2, divided by the dominant pole capacitance, C. For the example under consideration, dv dv I I C, SR, SR Eq. 2 dt dt C age 4 o 0

5 MT056 I / 2 50 A SR T μ 25V / μs. Eq. 3 C 2pF The ullpower bandwidth (FBW) o the op amp can now be calculated rom the ormula: SR 25V / μs FBW 4MHz, Eq. 4 2πA 2π V where A is the peak amplitude o the output signal. I we assume a 2 V peaktopeak output sinewave (certainly a reasonable assumption or high speed applications), then we obtain a FBW o only 4 MHz, even though the smallsignal unity gainbandwidth product is 53 MHz! For a 2 V pp output sinewave, distortion will begin to occur much lower than the actual FBW requency. We must increase the SR by a actor o about 40 in order or the FBW to equal 53 MHz. The only way to do this is to increase the tail current,, o the input dierential pair by the same actor. This implies a bias current o 4 ma in order to achieve a FBW o 60 MHz. We are assuming that C is a ixed value o 2 pf and cannot be lowered by design. These calculations are summarized below in Figure 3. Assume that 00µA, Cp 2pF I c A VT 50μ 26mV 520Ω u 53MHz 2π Cp Slew Rate SR BUT FOR 2V EAKEAK OUTUT (A V) FBW SR 4MHz 2π A Must increase to 4mA to get FBW 60MHz!! Reduce g m by adding emitter degeneration resistors Figure 3: VFB Op Amp Bandwidth And Slew Rate Calculations In practice, the FBW o the op amp should be approximately 5 to 0 times the maximum output requency in order to achieve acceptable distortion perormance (typically to 20 MHz, but actual system requirements vary widely). Notice, however, that increasing the tail current causes a proportional increase in g m and hence u. In order to prevent possible instability due to the large increase in u, g m can be reduced by inserting resistors in series with the emitters o Q and Q2 (this technique, called emitter degeneration, also serves to linearize the g m transer unction and thus also lowers distortion). age 5 o 0

6 MT056 This analysis points out that a major ineiciency o conventional bipolar voltage eedback op amps is their inability to achieve high slew rates without proportional increases in quiescent current (assuming that C is ixed, and has a reasonable minimum value o 2 or 3 pf). This o course is not meant to say that high speed op amps designed using this architecture are deicient, just that there are circuit design techniques available which allow equivalent perormance at much lower quiescent currents. This is extremely important in portable battery operated equipment where every milliwatt o power dissipation is critical. VFB O AMS DESIGNED ON COMLEMENTARY BIOLAR ROCESSES With the advent o complementary bipolar (CB) processes having high quality N transistors as well as NNs, VFB op amp conigurations such as the one shown in the simpliied diagram in Figure 4 below became popular. V S Q3 D Q4 OUTUT BUFFER Q Q2 X C V S Figure 4: VFB op amp using two gain stages Notice that the input dierential pair (Q, Q2) is loaded by a current mirror (Q3 and D). We show D as a diode or simplicity, but it is actually a diodeconnected N transistor (matched to Q3) with the base and collector connected to each other. This simpliication will be used in many o the circuit diagrams to ollow in this section. The common emitter transistor, Q4, provides a second voltage gain stage. Since the N transistors are abricated on a complementary bipolar process, they are high quality and matched to the NNs, and thereore suitable or voltage gain. The dominant pole o the Fig. 4 ampliier is set by C, and the combination o the gain stage, Q4 and local eedback capacitor C is oten reerred to as a Miller Integrator. The unitygain output buer is usually a complementary emitter ollower. age 6 o 0

7 MT056 A model or this twostage VFB op amp is shown in Figure 5 below. Notice that the unity gainbandwidth requency, u, is still determined by the input stage g m and the dominant pole capacitance, C. The second gain stage increases the dc openloop gain, but maximum slew rate is still limited by the input stage tail current as: SR /C. i v C v in v a X v out V REF u u CL 2πC SR C Figure 5: Model or Two Stage VFB Op Amp A twostage ampliier topology such as this is widely used throughout the IC industry in VFB op amps, both precision and high speed. Another popular VFB op amp architecture is the olded cascode as shown in Figure 6. An industrystandard video ampliier amily (the AD847) is based on this architecture. This circuit also takes advantage o the ast Ns available on a CB process. The dierential signal currents in the collectors o Q and Q2 are ed to the emitters o a N cascode transistor pair (hence the term olded cascode). The collectors o Q3 and Q4 are loaded with the current mirror, D and Q5, and voltage gain is developed at the Q4Q5 node. This singlestage architecture uses the junction capacitance at the highimpedance node or compensation (C STRAY ). Some variations o the design bring this node to an external pin so that additional external capacitance can be added i desired. age 7 o 0

8 MT056 V S 2 2 C COM Q Q2 Q3 V BIAS Q4 X C STRAY Q5 AC GROUND 2 D V S Figure 6: AD847Family Folded Cascode Simpliied Circuit With no emitter degeneration resistors in Q and Q2, and no additional external compensating capacitance, this circuit is only stable or high closedloop gains. However, unitygain compensated versions o this amily are available which have the appropriate amount o emitter degeneration. The availability o JFETs on a CB process allows not only low input bias current but also improvements in the slew rate tradeo, which must be made between g m and ound in bipolar input stages. Figure 7 shows a simpliied diagram o the AD845 6 MHz op amp. JFETs have a much lower g m per ma o tail current than a bipolar transistor. This lower g m o the FET allows the input tail current (hence the slew rate) to be increased, without having to increase C to maintain stability. V S D Q5 Q6 Q3 Q4 C V BIAS X Q Q2 V S Figure 7: AD845 BiFET 6MHz Op Amp Simpliied Circuit age 8 o 0

9 MT056 The unusual thing about this seemingly poor perormance o the JFET is that it is exactly what is needed or a ast, high SR input stage. For a typical JFET, the value o g m is approximately I s /V (I s is the source current), rather than I c /26mV or a bipolar transistor, i.e., the FET g m is about 40 times lower. This allows much higher tail currents (and higher slew rates) or a given g m when JFETs are used as the input stage. Until recently, op amp designers had to make the above tradeos between the input g m stage quiescent current and the slewrate and distortion perormance. ADI has patented a circuit core which supplies currentondemand, to charge and discharge the dominant pole capacitor, C, while allowing the quiescent current to be small. The additional current is proportional to the ast slewing input signal and adds to the quiescent current. A simpliied diagram o the basic core cell is shown in Figure 8 below. V S Q5 Q7 Q Q2 C X Q3 Q4 C 2 Q8 Q6 V S Figure 8: "QuadCore" VFB Stage orcurrentondemand The quadcore (g m stage) consists o transistors Q, Q2, Q3, and Q4 with their emitters connected together as shown. Consider a positive step voltage on the inverting input. This voltage produces a proportional current in Q that is mirrored into C by Q5. The current through Q also lows through Q4 and C 2. At the dynamic range limit, Q2 and Q3 are correspondingly turned o. Notice that the charging and discharging current or C and C 2 is not limited by the quad core bias current. In practice, however, small currentlimiting resistors are required orming an "H" resistor network as shown. Q7 and Q8 orm the second gain stage (driven dierentially rom the collectors o Q5 and Q6), and the output is buered by a unitygain complementary emitter ollower. age 9 o 0

10 MT056 The quad core coniguration is patented (see Reerence ), as well as the circuits that establish the quiescent bias currents (not shown in Fig. 8). The "quad core" is also oten reerred to as an "HBridge" core. A number o VFB op amps using this proprietary coniguration have been released and have unsurpassed high requency low distortion perormance, bandwidth, and slew rate at low quiescent current levels. Figure 9 lists a ew o the voltage eedback op amps using this architecture or comparison. LISTED IN ORDER OF DECREASING SULY CURRENT ART # I SY / AM BANDWIDTH SLEWRATE AD8045 () 9mA 000MHz 350V/µs ADA4899 () 6.2mA 600MHz 30V/µs AD8099 () 6mA 500MHz 600V/µs AD8074 (3) 0mA 600MHz 600V/µs AD8057 () 7.5mA 325MHz 50V/µs AD8038 ().5mA 350MHz 425V/µs Number in ( ) indicates single, dual, triple, or quad Figure 9: Some High Speed VFB Op Amps REFERENCES. Hank Zumbahlen, Basic Linear Design, Analog Devices, 2006, ISBN: Also available as Linear Circuit Design Handbook, ElsevierNewnes, 2008, ISBN0: , ISBN3: Chapter. 2. Walter G. Jung, Op Amp Applications, Analog Devices, 2002, ISBN , Also available as Op Amp Applications Handbook, Elsevier/Newnes, 2005, ISBN Chapter. Copyright 2009, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility or customer product design or the use or application o customers products or or any inringements o patents or rights o others which may result rom Analog Devices assistance. All trademarks and logos are property o their respective holders. Inormation urnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality o the content provided in Analog Devices Tutorials. age 0 o 0