AN-1106 APPLICATION NOTE

Transcription

1 AN-06 APPCATON NOTE One Technology Way P.O. Box 906 Norwood, MA , U.S.A. Tel: Fax: An mproved Topology or Creating Split Rails rom a Single nput oltage NTRODUCTON Even with the widespread use o rail-to-rail single supply op amps, there is still oten the requirement or dual rails (or example, ±5 ) to be generated rom a single (positive) input power rail to power dierent parts o the analog signal chain. These are oten low current (such as 0 ma to 500 ma) with relatively well-matched loads on the positive and negative supplies. One solution to this problem is to use two dierent converters; one to provide the positive rail and one to provide the negative rail. This can be expensive and, as this application note shows, unnecessary. Another solution is using a lyback; however, the supplies tend not to track each other very well with dierential loading, it requires a large and expensive transormer, and it tends to be ineicient. A better solution is a SEPC-Ćuk converter. This topology consists o an unregulated Ćuk converter tied to the same switching node as a regulated SEPC converter. This by Kevin Tompsett combination results in two supplies that track each other very well under all but a 00% load mismatch. An analysis o the converter s operation and implementation using the Analog Devices, nc., ADP6x demonstrates the versatility o this topology. n addition, a revolutionary new design tool is introduced, providing a quick path to implementing a SEPC-Ćuk in user applications. N C N a a Q C C Q3 b b Q C + C Figure. Schematic o the SEPC-Ćuk Converter Rev. A Page o

2 AN-06 TABE OF CONTENTS ntroduction... Revision History... Description o Topology... 3 imits to the Coupling Coeicient... 4 Dierential oad and Output oltage Tracking... 4 Small-Signal Analysis and oop Compensation... 5 Application Note Power Component Stress...6 Output Filter...8 ADP6x Design Tool...9 ab Results... 0 Reerences... 0 Conclusion... 0 RESON HSTORY 7/3 Rev. 0 to Rev. A Changes to Figure / Revision 0: nitial ersion Rev. A Page o

3 Application Note DESCRPTON OF TOPOOGY nitially, the SEPC-Ćuk appears to be a complicated converter with our dierent inductors and switches. Fortunately, it can be broken down into its two constituent converters, simpliying the analytical problem. For a SEPC or Ćuk converter, the Q and Q switches operate in the opposite phase rom one another. Figure shows the current low diagram or the two dierent switch states in a SEPC converter. (Q S COSED; Q S OPEN) a Q C N SN SN C N (Q S OPEN; Q S COSED) N a C SN SN Q C N Q Q b b C C Figure. Current Flow in a SEPC Converter t is not immediately obvious, but the transer capacitor (C) voltage is approximately constant N (with small ripple). Figure 4 shows the idealized waveorms or a SEPC converter. When Q is on, the voltage at SN is equal to N. Thus, during the time that Q is on (Q is o), the voltage across both a and b is N and when Q is o (Q is on), then the voltage across both a and b is. Applying the principles o inductor-volt second balance, the equilibrium dc conversion ratio as shown in Equation can be calculated. D is the converter s duty cycle (the raction o the switching cycle that Q is on). SEPC D () ( D) N The Ćuk converter operates in a similar manner to the SEPC converter, however, in this case, Switch Q is connected to ground rather than the output and the nductor b is connected to the output instead o ground. Figure 3 shows a current low diagram or the Ćuk converter during both switch positions. The Ćuk is a negative output converter, so current lowing out o the load is actually delivering power to the output (Q S COSED, Q S OPEN) a C N SN SN b C N (Q S OPEN, Q S COSED) N a C SN SN b C N Q Q Q Q C C Figure 3. Current Flow in a Ćuk Converter AN-06 The idealized waveorms or a Ćuk converter are shown in Figure 4. Applying the principles o inductor-volt second balance and capacitor charge balance, the voltage across C is N +. Thereore, the SN switch node switches between GND, when Q is closed, and (N + ). The voltage across both a and b while Q is on (Q is o), is N and, while Q is o (Q is on), the voltage across both a and b is. Comparing the waveorms in Figure 4 and Figure 5, note that the voltages across the inductors in a Ćuk are identical to those or the SEPC. Thus, the duty cycle equation or a Ćuk is simply negative the duty cycle or the SEPC,` as shown in Equation. N + N /( D) D ( D) ON TME NODE OTAGES COMPONENT CURRENTS OFF TME ON TME Figure 4. dealized Waveorms SEPC SN SN OFF TME a b (Q) Rev. A Page 3 o

4 AN-06 Application Note N + N /( D) D ( D) Cuk N ON TME NODE OTAGES COMPONENT CURRENTS OFF TME ON TME Figure 5. dealized Waveorms Ćuk SN SN a b Q OFF TME D () ( D) The act that the duty cycles are equal and opposite, the switch node (SN) voltages are identical, and the inductor currents are identical is what makes it possible to simply attach the two converters together at Node SN. The combined converter is shown in Figure. Q and Q3 have been replaced by diodes because these supplies are generally lower power analog supplies where an asynchronous controller makes good sense. n addition, two inductors (a and a) are in parallel. The reason or this is that a and b, and a and b, are coupled together using two separate coupled inductors. This has multiple advantages. Coupling the inductors reduces current ripple in the inductors by a actor o two (see the Ćuk-Middlebrook paper cited in the Reerences section). n addition, it signiicantly reduces the complexity o the small signal model and enables higher bandwidth by eliminating the SEPC and Ćuk resonances located according to Equation 3 and Equation 4. This enables the use o a wide variety o o-the-shel parts since there are not many three winding :: inductors available. SEPC resonance (3) a b C Cuk resonance (4) a b C A six winding part, such as ound in Coilcrat s Hexapath line product line, or a custom three winding transormer could also be used MTS TO THE COUPNG COEFFCENT Even though coupling the inductors has distinct advantages, it is undesirable or the coupling to be tight enough or there to be signiicant energy transer through the core. To avoid this situation, the designer must ensure that the magnitude o the complex impedance o C (and C) at the switching requency is less than a tenth that o the impedance o the leakage inductance (KG) plus the DCR o a single winding. This inequality is designated in Equation 5. The leakage inductance (l) can be calculated using Equation 6 and the coupling coeicient (K) generally ound on coupled inductor data sheets. m is the measured sel-inductance that appears in the data sheet. Note that in Equation 5, the x in Cx and x reers to either C or C or or. Z Cx = ESR DCR lkg x 0 + C Cx Z lkg 0 x Cx sw lkg x (5) ( K) (6) m DFFERENTA OAD AND PUT OTAGE TRACKNG By nature, the Ćuk (negative) output o the SEPC-Ćuk is unregulated; thus, there is some amount o load variation with changes in output current and, particularly with load mismatch, compared to the SEPC (positive) output. Note that the tracking is much better than a similarly conigured lyback converter, especially in the case o a transient or a load mismatch. This is because the coupling between channels is a direct connection rather than through the transormer with its inherent leakage inductance. Figure 6 shows a 30 ma transient applied to the Ćuk ( ) output o a SEPC-Ćuk converter, while a constant 00 ma remains on the SEPC output. t shows that both outputs respond to the transient load. This is the worst-case transient because the Ćuk output is unregulated. nterestingly, most o the deviation shown on the rail is actually dc regulation shit caused by the mismatch between the loads applied to the two rails (+, ). Rev. A Page 4 o

5 Application Note AN-06 C C3 C4 C C F B W ACM 5.00m/D 5.00m C3 F B W ACM 5.00m/D.900m + + C F B W DC 50.0mA/D 99.00mA C4 F B DC 50.0mA/D 50.00m TMEBASE 0.00ms 500µs/D 500kS 00MS/s TRGGER C3 DC STOP 300µ EDGE POSTE Figure 6. Transient Response rom a 30 ma Step oad Applied to the Negative (Ćuk) Output With an identical load on both supplies, at steady state, the most signiicant error terms are a mismatch in the DCR o the inductors and the orward voltage o the diodes, both o which can be made quite small relative to the output voltage. With substantial load mismatch, the error grows as shown in Figure 7. Thereore, in some applications it may be necessary to put a small dummy load on one or both o the channels to keep both supplies in their regulation window. Note that, in general, analog chips, like op amps, are largely insensitive to dc changes in their power supplies as long as there is suicient head room available. / N (%) OAD ON + = 0.A OAD ON + = 0.0A OAD ON + = 0.05A OAD ON + = 0.006A NEGATE SUPPY (A) Figure 7. Relative oltage Regulation Between Rails with Dierential oading SMA-SGNA ANAYSS AND OOP COMPENSATON A complete small-signal analysis o the SEPC-Ćuk converter is beyond the scope o this paper; however, the equations provided in this application note should allow the designer to correctly compensate their design. The ADP6x SEPC-Ćuk design tool uses a more complete model which is more accurate, but much more complicated. The equations shown reer to the Rev. A Page 5 o ADP6x part in SEPC-Ćuk and may not be accurate or other parts made by Analog Devices or the company s competitors. The small-signal model or a SEPC-ĆUK looks very similar to a SEPC converter with no attached Ćuk as long as a ew design requirements are met. t is assumed that identical inductors are used on the SEPC-Ćuk rails. This requirement makes sense because both outputs are designed or the same voltage and current. n their paper, Ćuk and Middlebrook (see the Reerences section) show that a coupled inductor, rom both a small signal and a large signal, behaves like an inductor with twice its single winding inductance value, without the SEPC or Ćuk resonances. Thereore, analysis in this application note is shown using the eective inductance, that is, twice the single winding inductance value that appears on coupled inductor data sheets. The analysis assumes identical resistive loads, though the converter remains stable with signiicant load imbalance. The two transer capacitances (C and C) should be nearly the same value, erring on the side o having C slightly larger than C. These are assumed to be ceramic capacitors and, thus, the designer needs to take into account the dierences in their dc bias value when calculating their eective capacitances. The irst step in compensating a SEPC Ćuk is to choose an achievable target crossover requency. ike most boost and buck-boost topologies, the SEPC-Ćuk has a right hal plane zero (RHP) located according to Equation 7. An RHP has the dual eect o adding gain, like a zero, and subtracting phase, like a pole. Thereore, the converter must be compensated or a crossover requency a maximum o one ith o the requency o the RHP (RHP). The SEPC-Ćuk has an additional resonance caused by the leakage inductance (lkg ) and transer capacitance (C) that occurs at Fres. This resonance is generally well damped by the DCR o the inductors, but can introduce signiicant phase lag; thereore, it is good to crossover at least a decade beore it. n addition, a current mode controller with standard Type compensation is used, thus, the maximum achievable crossover requency is approximately one-tenth the switching requency. Target u should, thereore, be chosen as the minimum o these three constraints, as shown in Equation 9. RHP.5 ROAD DQ = (7) D Q res = (8) π C lkg RHP res sw u = minimum,, (9) 5 0 0

6 AN-06 Application Note N Q S R G CS CK + C C POWER STAGE AND NNER CURRENT OOP RAMP a a C D C Q b R C C C R C b R ESR 3 C 3 D R ESR C G M FEEDBACK AND COMPENSATON REF Figure 8. Block Diagram Showing Power Stage and Compensation Components R OAD + R OAD The compensation values in Figure 8 can be calculated as ollows. Since it is assumed ceramic output capacitors will be used, CC can be selected as 0 p. C R where: C c C C p C REF 4π G A m c p u C C R F R F u p (0) () C p is the dominant pole or the current mode converter with some correction actors to account or ramp compensation and inite current gain. p ( Do ) Do M c D on C out C out3 C R OAD () Ac is the magnitude o the open-loop converter gain at the crossover requency u. u F rhp m A c (3) ( ) Fmout Don D ond u o DonDo Rload p Mc and Fm are terms derived rom Ridley s thesis (see the Reerences section) on current mode control. M F A RAMP sw cs c (4) N A sw cs m (5) 4 M cn ramp and Acs are ixed constants within the chip. 0. (ADP6/ADP63) (6) RAMP A 3.5 (ADP6/ADP63) (7) cs POWER COMPONENT STRESS As is oten the case, a 30% ripple in the inductors generally results in a reasonable value (see Equation 9). However, with large step down ratios it can be more optimal to increase this ripple percentage in the input inductor to 50% or 60%. N (into each inductor a and a) (8) N 0.3 N (9) pkx a N (0) pkx b () N ( ) () N sw The currents in the FET Switch Q and the two diode switches, Q and Q3, are shown in Figure 9. The dc components o the switch current are also shown in Figure 9. Note that Q carries the current or both the SEPC and the Ćuk rails. The peak currents depend on the ripple chosen in Equation 9. Rev. A Page 6 o

7 Application Note AN-06 /( D) /( D) 4 Q Q = Q3 ON TME OFF TME ON TME OFF TME Figure 9. dealized Waveorms or SEPC-Ćuk Calculating the switching loss in the primary Switch Q is beyond the scope o this application note. Note that, in many cases, the switching loss can be quite large since the voltage swing the switch sees is large (~N + ) and so are the currents (see Figure 9). The ADP6/ADP63 work to reduce this loss by switching very quickly. The FET chosen must be rated to withstand at least N + and good engineering allows some margin or switch node ringing due to stray inductances, in addition to thermal stress rom RDS on loss and switching losses The peak-to-peak output voltage ripple on the SEPC (positive) output is (Δripple SEPC) and is approximated by DON Δripple SEPC ESRC ( DON ) (3) C sw The value o the current through the capacitor (RMS Cout SEPC) is D DON ON ( ) 3 rms C SEPC (4) DON The peak-to-peak output voltage ripple on the Ćuk (negative) output (Δripple Ćuk) is approximated by D ON ripple Cuk ESRC3 (5) 8 swc3 The rms value o the current into the C on the Ćuk (negative) output (Δrip Ćuk) is approximated by rms _ C _ Cuk (6) 3 The ripple on C and C should be chosen or around 5% o N. As stated earlier, they should have similar values despite the dierence in dc voltage across them. D ON N ripple _ Cx N ESRC x (7) swc t is important to consider rms ratings when choosing C and C since the current through them is quite large. D ON D ON rms _ C C 3 pk _ pk _ N N xa xa 3 pk pk xb xb (8) DON N ripple Cx _ N ESRCx (9) C sw Rev. A Page 7 o

8 AN-06 Since Q and Q3 are generally diodes, there are several things to consider when choosing a component. ds max must be rated to at least N +. The continuous current should be at least /3 the peak current to be seen. nterestingly, because o the phase relationship between the output voltage ripple o the two supplies, the SEPC diode actually receives the ull switch or some amount o time beore the current achieves a more even split. As expected though, the average current through both diodes is the same,. n addition, the package must be able to handle the in the thermal environment o the application. DC _ diode _ current _ rating N (30) 3 PUT FTER The SEPC-Ćuk as a dual rail converter is typically used or analog power supplies, which oten require very low output ripple. ow output ripple (down to m) is generally easily achieved on the Ćuk (negative) output rail simply by using ceramic output capacitors because the output current is continuous like the output current o a buck converter. On the SEPC (positive) rail, the output current is discontinuous like the input current o a buck converter. This results in a step change in the current into the output capacitors. These switching spikes are not well attenuated even by ceramic capacitors because o their inductance. Thereore, it is oten necessary to put a small, damped output pi ilter on the output o the SEPC winding. Q R FT FT Application Note + C C Figure 0. Schematic o the Output Filter Although this ilter aects the small-signal model in new and interesting ways, this issue is not ully discussed in this application note. As long as the damping resistor is chosen according to the Equation 3 and Equation 3, and the converter is designed to crossover at a tenth o ωo or less, no instability should be caused by the pi ilter. C should be chosen or around % output ripple and C should be chosen to match the output capacitor o the Ćuk output using the equations in the power components stress section. A good value or ilt is generally μh, and Qo should be set to. o C C iltc C (3) R ilt R R load load ilt C C C Q o o C C ilt Q oo ilt (3) Rev. A Page 8 o

9 Application Note ADP6X DESGN TOO The ADP6x SEPC-Ćuk design tool is a ully integrated Excel -based designer or the ADP6x chips in a SEPC-Ćuk coniguration. Once the user has enabled macros (which may require a change o the security settings in Excel), the Enter nputs dialog box appears, or can be ound by pressing the Find Solution button. n the dialog box, enter the voltages and currents required or the design and choose whether to optimize or cost, loss, or size. the iew Solution button is pressed, the design tool outputs a complete, optimized design. This includes a costed BOM with compensation values, an accurate, tested eiciency plot across load, a plot o power loss across load, a ull load bode plot, perormance parameters, component stresses, and power dissipation or every component. n addition, the Build Your Design tab provides the same BOM, but with the components arranged to it on the blank demo board (ADP6x-B3-EZ) and any extra components required to conigure the demo board. Figure. Advanced inputs Dialog Box AN-06 One o the most powerul eatures o this tool are the component buttons ound on the User nterace tab. This unctionality gives the user the ability to individually change each component to ully customize the design. Each o the components in the drop-down list have been preselected rom a database o thousands o components to produce a unctional design, and sorted according to the optimization chosen in the Enter nputs dialog box. The components must be selected in order, rom top to bottom, since there are dependencies between the dierent components Figure. Basic nputs Dialog Box Additional customization tools are available in the Advanced Settings dialog box. Here the user can select parameter speciications or output voltage ripple, current, transient response, optional output ilter usage, an external UO, and more. A more in-depth description o the unctionality o these options is provided in the Program Details dialog box available by clicking the Program Details button ound on the Enter nputs dialog box Rev. A Page 9 o

10 AN-06 AB RESUTS To demonstrate the eicacy o the design tool, a design was done using the tool or 5 N, ±5 at 50 ma with the advanced speciications shown in Figure and Figure. n addition, the diode was changed or slightly lower loss. The jagged eiciency line at around 0 ma is caused by the converter going into discontinuous mode. Once both the switches have turned o, the switch node rings causing zero voltage switching at speciic load currents. A schematic or the circuit is shown in Figure Application Note REFERENCES Ćuk, Slobodan and R.D. Middlebrook Coupled- nductor and Other Extensions o a New Optimum Topology Switching DC-DC Converter. Advances in Switched-Mode Power Conversion, olumes and. rvine, CA: Tesla Co. Ridley, Dr. Ray A New Continuous-Time Model or Current-Mode Control. Brandenton, F: Ridley Engineering. CONCUSON n conclusion, the SEPC-Ćuk provides an inexpensive and robust way to create dual rails using only one controller. The ADsimPOWER design tool allows complete customization o the design and can be relied on to create robust SEPC-Ćuk designs quickly. EFFCENCY (P /P N ) PREDCTED EFFCENCY MEASURED EFFCENCY (A) Figure 3. Eiciency eriication C C 5nF R C 7.4kΩ ENABE C C 0pF RF 6.5kΩ N C N µf, 6.3, 0603 U ADP63 COMP FB EN GND R B 0 0Ω SS RT N SW C 5 µf, 6.3, 0603 RFB 49.9kΩ b a PD40-53 b a PD40-53 D C µf, 6, 0805 C SS 0nF C µf, 6, 0805 Figure 4. Schematic o Test Circuit D C µf, 6.3, 0603 C 3 0µF, 6.3, 0805 µh ME30-0MB C 0µF 6.3, Rev. A Page 0 o

11 Application Note AN-06 NOTES Rev. A Page o

12 AN-06 Application Note NOTES 0 03 Analog Devices, nc. All rights reserved. Trademarks and registered trademarks are the property o their respective owners. AN /3(A) Rev. A Page o