Building An Average Model For Primary-Side Regulated Flyback Converters

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1 ISSUE: March 7 Building An Average Model For Primary-Side Regulated Flyback onverters by Yann Vaquette, O Semiconductor, Toulouse, France Ac analysis is well covered in the literature or a classical lyback topology involving an optocoupler associated with a shunt regulator like the popular TL43. With the emergence o smartphones and other tablets, the adapter market and more precisely the travel adapter market, the trend is to reduce the size and cost o this black box connected to the mains. What are the possibilities to meet these goals? One option is to simpliy the eedback chain and adopt a primary-side regulated type o structure. While regulation through a primary-side winding is a well-known principle, several improvements have been introduced such as better overall accuracy and the ability to control the output current without actually measuring it. These primary-side-regulated (PSR) controllers are now ound in a variety o applications and compete against existing optocoupler-based designs. However, the compensation is not covered at all in the literature or the PSR topology. To compensate a power supply, an ac analysis has to be perormed by using an average model or instance. This article will describe the main dierences between a classical lyback converter with optocoupler and a PSR lyback. Then we will see how we can build an average model or the PSR lyback (one that includes the required sample-and-hold network) and simpliy it without impacting the transer unction. The transer unction will be evaluated and results obtained with Mathcad plots o the transer unction will be compared with simulations o the converter. Finally, the loop compensation will be plotted and calculations needed to adjust the phase margin detailed. lassical Flyback Versus PSR The term classical lyback implies a loop built around a secondary shunt regulator the TL43 or instance and an optocoupler used to convey the inormation to the primary side. The typical schematic o such converter is shown in the Fig.. Ac Ac Prim 3 Sec Aux 4 6 S DRV 3 FB GD Vs/ V 4 Fig.. Simpliied schematic o a classical lyback structure. In this coniguration, the output voltage is directly sensed on the secondary side. By modulating the optocoupler LED current, the regulation inormation is sent back to the primary-side controller, which adjusts the requency and/or the primary peak current to keep the output voltage at its nominal value. 7 HowPower. All rights reserved. Page o 9

2 However, the optocoupler is a relatively expensive part which consumes more PB space than simple SMD resistors or capacitors (such as those in an 63 package.) And because millions o travel adaptors are shipped with a cell phone every year, removing the secondary-side circuit and the optocoupler would lead to a substantial economy or the manuacturers. For this reason, new solutions have been developed to eliminate these components as shown in Fig. while maintaining regulation accuracy similar to that achieved by the classical lyback. Ac Ac Prim 3 Sec Aux 4 6 S DRV 3 omp GD Vcc 4 Fig.. Simpliied schematic o a PSR-based lyback structure. The PSR Principle Looking at the schematic in Fig. we can see that the only connection between the primary side (high voltage) and the isolated secondary side (low dc voltage) is the transormer. From a saety and reliability point o view, the elimination o the optocoupler brings advantages: optocouplers are known to drit as they age (such as current-transer ratio (TR) degradations) and they can also be susceptible to external perturbations. What is the operating principle o a primary-side-regulated structure? Let s have a look at signals around the transormer as shown in Fig. 3. vds t V vse t V PS out V vaux t PA V PS out Fig. 3. SPIE waveorms measured on or near the lyback transormer. 7 HowPower. All rights reserved. Page o 9

3 During the o time, the drain voltage (VDS) is the sum o the input voltage and the output voltage as aected by the primary-to-secondary turns ratio designated by PS (secondary/primary). ow we will ocus our attention on the secondary winding voltage (VSE). The voltage during the o time, i.e. when the primary-side MOSFET is turned o, equals the output voltage plus a voltage determined by the output rectiier and output capacitor. During the to phase, the output rectiier diode conducts to supply the load and charges the output capacitor. I we zoom-in on the secondary winding voltage as shown in Fig. 4, we can see that the voltage decreases according to the diode current. This slope comes rom the diode dynamic resistance rd. ise t i t sec V V r i t out T d sec V V r i t out T d sec vse t r d Fig. 4. The eect o diode dynamic resistance on the secondary winding voltage (simulation curves.) Indeed, the voltage drop across a diode is the sum o two parameters: The conduction threshold: VT r i t. The drop across the dynamic resistance:. d sec VT is a technology-dependent parameter while rd depends on the operating point o a given diode. The voltage on the auxiliary winding will exhibit the same shape as that o the secondary winding voltage but its voltage value is aected by the auxiliary turns ratio. With the help o Fig. 4, we can easily see that i the primary-side controller samples the voltage at the beginning o the demagnetization time (where the irst dotted vertical line appears in Fig. 4), the output voltage inormation will be aected by the current. At ull load, the output voltage will be lower than in light-load operation. The presence o the dynamic resistance explains this dierence. In order to correctly inorm the controller, our PSR circuit precisely detects the end o the core demagnetization the auxiliary voltage knee beore sampling this voltage. This technique naturally produces a aithul representation o the output voltage. In practice, inside the controller die, a sample-and-hold circuit is connected to the Vs/ pin the pin used to detect the zero crossing o the auxiliary voltage and perorm the V regulation to implement this eature. The sampled signal is then compared to a reerence voltage and generates constant-voltage regulation through an (operational transconductance ampliier) OTA as illustrated in Fig.. 7 HowPower. All rights reserved. Page 3 o 9

4 Vs / Zero rossing & Signal Sampling Sampled FB_V omp OTA Vre_V Fig.. A simpliied schematic or constant-voltage regulation. The waveorm on Fig. 6 shows the curves related to the sampling process. The signal connected to the OTA (red curve) is compared to the reerence voltage and is rereshed cycle by cycle without being impacted by the output current. Thanks to this method, the constant voltage regulation is accurate over the output load or input voltage. Load-regulation perormance is presented in Fig. 7: we achieved better than.% over the output power range, which is something a conventional, simple auxiliary-based converter could not reach. vsync t vout sample t Reresh Reresh Reresh vzcd t Fig. 6. Reresh o the voltage or V regulation. 7 HowPower. All rights reserved. Page 4 o 9

5 Accuracy (%) Exclusive Technology Feature V Load regulation.%.%.%.%.% -.% -.% -.% -.% Iout (A) 8 V rms V rms V rms 99 V rms 3 V rms 6 V rms Fig. 7. onstant voltage regulation as a unction o load current and input voltage or a PSR controller measured in the lab. Power Stage Average Model With Primary-Side-Regulation Topology One option or studying the stability o our converter is to use an average model. To create this model, we will use the pulse width modulation (PWM) switch model introduced in the 9s and adapted to quasi-resonant (QR) operation in reerence []. The principle behind the PWM switch is to model a cell made o the diode and the primary MOSFET which introduce a discontinuity during the switching event. This approach lead to a simple large-signal three-pin model later linearized or study o the requency response. Since this method is well covered in the literature (see reerences [] and []), we will not spend more time on this topic. Using the PWM switch model or the QR lyback topology, the schematic in Fig. 8 can be drawn. trl Vin Fsw D Ip Ip dc Fsw a T R L p U Resr Rload c PWMBMM Lp 3 out Aux 4 Resr Ric Rupper XFMR v cc Rlower zcd Fig. 8. The PWM switch model in a lyback converter. This schematic integrates all components around the transormer without simpliication or now. onnected to the secondary winding, we can identiy the output capacitance (out) with its equivalent series resistance (Resr) and the output load (Rload). On the auxiliary winding, the Vcc capacitor (Vcc) in series with its ESR (Resr) is 7 HowPower. All rights reserved. Page o 9

6 visible. In parallel, the I consumption has been modeled with the RI resistance. Finally, the resistors connected between the auxiliary winding and the pin are also present. Simulating this schematic in SPIE, we can extract the control-to-output Bode plot o the power stage (trl node to ). Fig. 9 displays the results. Please note that while the component values used in simulating the Fig. 8 schematic are not shown, these values are representative o a practical application. d (db) ( ) H -d H -4d G c 9. db - -6d -4-8d P c >> -d Hz Hz.KHz KHz KHz DB(V()) P(V()) Frequency Fig. 9. Power stage transer unction. Let s select a crossover requency c at khz. This is a good tradeo between a quick transient response and good noise immunity. The right hal-plane zero (RHPZ) present in a DM current-mode lyback converter is ar away and does not bother us. At this cuto requency, the power stage attenuation is measured as 9. db and the phase as As the eedback signal is built rom the auxiliary winding, we need to build the same Bode plot with the output observed on the V aux node (Fig..) The phase shape is not changed but the magnitude curve is aected by the transormer turns ratio: G di PA.83 log log 3.4 db PS.3 () d (db) ( ) H -d - -4d H G c.9 db - -6d d P c >> -d Hz Hz.KHz KHz KHz DB(V(Vaux)) P(V(Vaux)) Frequency Fig.. Transer unction observed on the auxiliary winding. Using this average model coniguration, all components present on the output are automatically relected to the auxiliary winding. Here, both diodes have negligible dynamic resistances and are treated as short circuits. 7 HowPower. All rights reserved. Page 6 o 9

7 Simpliication O The Power Stage Average Model The next step will consist o simpliying the schematic and reducing the number o components without altering the transer unction. Looking at the schematic in Fig. 8, we see three windings: the irst one is the primary winding, the second is related to the power delivery (secondary power winding) and the third one is used or output voltage measurement. It is also designed to supply the controller (auxiliary winding.) Since the inal goal is to plot the open-loop transer unction, we will try to simpliy the transormer with a single secondary-side winding. All Bode plots will not be shown in this article but the irst step was to remove the I consumption resistance and then the Vcc capacitor. The last possible simpliication is to relect the components connected to the secondary side to the auxiliary winding. Let s ocus our attention around the transormer as shown in Fig.. ompared to Fig. 8, the number o components connected to the auxiliary winding is now limited to the pin bridge resistances. The turns ratios linking the primary to the power secondary and auxiliary windings are respectively labeled PS and PA where S aux PS and PA. P P T Resr s out Rload p 3 Aux aux Rupper 4 Rlower zcd Fig.. The transormer and secondary components. Simpliying this schematic will allow us to simply the power stage average model. To clariy what we re doing, we will divide this exercise into two steps. First, the output capacitor and resistive load are relected to the primary side as illustrated in Fig.. Then later, these elements will be relected rom the primary to the auxiliary winding. T R'esr 'out R'load 3 Rupper Aux 4 Rlower zcd Fig.. Output capacitor and load relected to the primary side. 7 HowPower. All rights reserved. Page 7 o 9

8 Relecting omponents Around The Transormer How can these components be relected across the transormer i we treat the circuit components as ideal, particularly allowing the diodes to have a -Ω dynamic resistance? Let s have a look at the equation around an ideal transormer drawn in Fig. 3. I I V n n V Z o 3 Fig. 3. Ideal transormer. n V I n V I () Ohm s law gives us a chance to write: V Zo I (3) Rearranging (), we know that: V V (4) I I () Substituting (4) and () into (3): V V Z Z o i I I (6) Input impedance Zi can be extracted: Z Zi o (7) ow that the relationship between the load and its relected equivalent is established, we can easily apply it to our schematic in Fig. where R R' load load PS (8) R R' esr esr PS (9) ' out out PS () 7 HowPower. All rights reserved. Page 8 o 9

9 By applying the same method, we can now move the impedance rom the primary side to the auxiliary winding using the new turns ratio (PA): R" load Rload PA PS () R" esr Resr PA PS () PS " out out PA (3) We can update Fig. 8 according to the previous simpliication. The result is shown in Fig. 4. trl Vin Fsw D Ip Ip dc Fsw a p T R L PA AUX P R"esr Rupper Aux c PWMBMM 3 "out R"load Rlower zcd Lp Fig. 4. Simpliied PWM switch model. The corresponding Bode plot is shown in Fig.. The magnitude and phase curve o the original schematic have been superposed (dashed red trace or the gain and dashed blue trace or the phase). Both curves are identical. d (db) ( ) H -d - H - -4d G c.9 db -6d d P c >> -d Hz Hz.KHz KHz KHz DB(V(Vaux)) P(V(Vaux)) Frequency Fig.. Transer unction (trl node to Vaux) obtained with the simpliied schematic. 7 HowPower. All rights reserved. Page 9 o 9

10 Sample-And-Hold etwork In The Power Stage The last part that needs to be introduced in the power stage is the sample-and-hold network. Indeed, as explained at the beginning o this article, the constant voltage regulation depends on this network being inserted between the pin and the OTA. A sample-and-hold network transer unction can be modeled in the requency domain by a zero-order hold (ZOH). The ZOH transer unction TZOH can be described by the ollowing Laplace transorm expression: T ZOH s e st st sw sw (4) In (4), we can identiy the numerator as the original signal plus an inverted delayed signal. The denominator is an integration unction. Following reerence [3], the equivalent circuit in Fig. 6 can be assembled. Please note that this circuit cannot deliver a dc component and can only be used or a pure ac analysis. OUT I ZOH T I GAI = {/Tsw} I = V TD = {Tsw} Z = R64 Fig. 6. ZOH modeling with delay line plus an integrator. By including the ZOH in our primary-regulated converter, we have completed the conversion chain and we can update our average model (Fig. 7.) trl Vin Fsw D Ip Ip dc Fsw c a p T R L PWMBMM Lp 3 R"esr "out R"load Rupper Rlower Aux zcd T3 TD = {Tsw} Z = OUT I I R64 GAI = {/Tsw} I = V ZOH Fig. 7. Average model o the power stage including the sample-and-hold network. The trl node to ZOH output gain and phase curves can be plotted as in Fig. 8. At the selected crossover requency (i.e. khz), the gain and phase can be extracted. Both values will be needed to dimension the compensation network. G 3.8 db () Fc P 9.4 (6) Fc 7 HowPower. All rights reserved. Page o 9

11 d (db) ( ) -d -4d - H d H G c 3.8 db -8d -4 -d d d P c 9.4-6d -9 - >> -8d Hz Hz.KHz KHz KHz DB(V(ZOH)) P(V(ZOH)) Frequency Fig. 8. Transer unction o the power stage now including the internal sample-and-hold network. Derivation O ontrol-to-output Transer Function ow that we have determined the proper simulation architecture, we need to determine an expression or the control-to-output transer unction. The power stage will be divided in several parts. Then each individual transer unction will be computed and then multiplied to orm the complete power stage response. trl Vin Fsw D Ip Ip dc Fsw a T R L p Resr Rload c PWMBMM Lp 3 4 out Rupper Aux T4 OUT I I GAI = {/Tsw} I = V ZOH Rlower zcd TD = {Tsw} Z = R6 Fig. 9. The power stage is divided into three main sections the power stage, the auxiliary winding structure, and the sample-and-hold network. Let s start with the power stage only, considering the control voltage (Vctrl) to the output voltage V out. The transer unction o a borderline (or boundary) conduction mode (BM or QR or quasi-resonant) current-mode lyback converter is: s s s s z s z Hs H Vctrl s s s p (7) By using the loss-ree network concept described in reerence [], we can identiy: 7 HowPower. All rights reserved. Page o 9

12 Rload H V out Kcomp PS Rsense PSVin p R load out PSVin V PS in (8) (9) z R R esr out PSVin PSVin load z PS Lp V out () () Please note the parameter Kcomp in the dc gain H is related to the internal divider between the OTA output and the control voltage. The ac response shown in Fig. is obtained by plugging equation 7 into a Mathcad sheet. The values used are the same ones used in the SPIE simulation o Fig. 9. The magnitude and phase curves o the simulation ile depicted in the irst part o this article (Fig. 9 dashed blue trace or the gain and dashed red trace or the phase) are a perect match. ( ) (db) H H 6 e 3 e 4 e Fig.. Power stage transer unction plots generated using Mathcad. The impact o the transormer is easy to calculate. It is a dc gain called KT linked to the turns ratio between the primary and the secondary PS and between the primary and the auxiliary winding PA: 7 HowPower. All rights reserved. Page o 9

13 K T PA PS () The next step is related to the red rame in Fig. 9. The network used to adjust the output voltage is perormed by the R upper and R lower resistances plus the iltering capacitor. This capacitor is adjusted to turn the MOSFET on when the drain-source voltage is at its minimum thus reducing switching losses. The transer unction o the network can be easily calculated by using the Fast Analytical Techniques described in [4]: D D K s K s (3) where Rlower KD R R lower upper and R R lower lower R upper R upper. The last block is related to the sample-and-hold network that we already tackled above. It enters the equation as a multiplicand as shown below. s s s s e s s st s p z z 3 T D ZOH T D H s H s K K s T s K H K st sw sw (4) The last step and the most important one is to check that both Mathcad and simulation responses are identical. The curves appear in Fig.. ( ) (db) H H Simulation Mathad e 3 e 4 e Fig. Power stage ac response including the internal ZOH block. We can see that the magnitude curves are identical up to khz. The addition o the ZOH contribution clearly appears beyond khz where a noticeable deviation shows up in the phase. The compensation exercise will not be aected by these deviations as we plan to ix the crossover requency around khz. From the graph, we can extract the numbers below, G Fc 33. db () 7 HowPower. All rights reserved. Page 3 o 9

14 P Fc 9. (6) which are to be compared with the measurement done with the simulation model: G Fc 3.8 db P Fc 9.4 (7) (8) ow we have a match between a SPIE simulation and a Mathcad analysis, we can look at the compensation strategy. The compensation o our primary-side-regulated controller is done around an OTA. Looking at the open-loop phase response at the selected crossover requency, we see there is a need or some phase boost to meet the minimum requirement o a 4 phase margin. The type- compensation only aects the magnitude curve and does not provide phase boost. Thereore the study that ollows will thus ocus on the type- architecture. Transer Function O OTA With Type- ompensation A typical OTA coniguration appears in Fig. where the output drives a capacitor connected in parallel with an R network. V in OTA V comp V re_v R Fig.. OTA with type- compensation. Let s start by calculating the impedance oered by the three passive components: in parallel with the series connection o and R: Z eq s R s s R s s (9) By developing and rearranging, we have Z eq s sr (3) s sr One more step to ormat the equation is to actor sr in the numerator: Z eq R s sr (3) sr 7 HowPower. All rights reserved. Page 4 o 9

15 The output current lowing out o the OTA is the dierential input voltage aected by the transconductance parameter gm: I V V g m (3) out OTA In Laplace notation, the reerence voltage is ixed and its small-signal response is V. Thereore I s V s g (33) in out OTA Applying Ohm s law, we can write: comp m V s I Z s (34) out OTA eq Substituting (3) and (33) in (34) implies: R V s V s g comp in m sr From (3), we extract the transer unction: (3) sr Vcomp s gmr sr Gs Vin s sr (36) From this expression, we can identiy the mid-band gain G, the zero and the pole: gmr G (37) z R (38) p R (39) ow, we need to deine the position o the pole and zero so that the open-loop gain crosses db at the cuto requency with the expected phase margin. Several tools can be used to build the compensation network like the manual placement oered in [4] or the k actor method introduced by Dean Venable in the 9s. [] The second solution will be used or this article. It consists o determining the position o zero and the pole with respect to the crossover requency so that adequate phase boost is produced. The number k is deined by: boost k tan 4 (4) where the boost parameter is the needed compensation phase boost determined as: 7 HowPower. All rights reserved. Page o 9

16 Boost PM PS 9 (4) In this equation: PM is the desired phase margin at selected crossover requency c PS is open-loop phase o the converter at the selected crossover requency c -9 is incurred by the origin pole. The pole and zero locations can be now calculated like the compensation network: z c k (4) p k c (43) R p (44) R G R g m z (4) (46) I we consider, <<, R becomes: R G gm (47) umerical Example Let s apply these ormulas to our design goal o a -khz crossover requency with a 7 phase margin. Our design data are the ollowing: khz c PM 7 PS 9. G c 33dB G c 33) G 44.7 From these values, we can calculate: Boost (48) 7. k tan 4 6. (49) ow that the k-actor is known, the pole and zero requency can be evaluated: 7 HowPower. All rights reserved. Page 6 o 9

17 z 4 Hz 6. () k khz () p c Finally, we can calculate the type- compensation network component values: 44.7 R 3. kω µ () 4.6 nf 3.k 4 (3) pf 3.k6.k (4) The normalized values will be kω or R, 4.7 nf or while will equal pf. The Mathcad dynamic response appears in Fig. 3. The crossover requency is measured as 96 Hz with a 69.8 phase margin (db) M ( ) T T c 96 Hz e 3 e 4 e Fig. 3. Ac response generated in Mathcad or a converter with a type- compensation network. The inal step is to compare these curves to the simulation model. The ollowing schematic in Fig. 4 shows the OTA with the type- compensation consisting o, and R. The compensation loop is broken between the comp signal and the internal Kcomp divider in order to inject the ac modulation. Vdd Vre V.Vdc ZOH G I+ OUT+ I- OUT- GVALUE 4.7nF R k OMP pf L3 G 6 G IJ V76 Vac Vdc R Kcomp. trl Fig. 4. Type- compensation schematic with the internal Kcomp divider. 7 HowPower. All rights reserved. Page 7 o 9

18 We can now import this schematic into the power stage schematic presented in Fig. 7 to obtain the complete open-loop gain o the converter. This is what Fig. shows. (db) ( ) T T M 7 98 Hz c Fig.. PSpice open-loop gain o the BM lyback converter operated in PSR mode The crossover requency and the corresponding phase margin are almost identical between the Mathcad ile implementing the transer unction and the simulation model, which conirms the validity o our approach. Practical Application A PSR converter based on the P36 has been assembled as shown in Fig. 6. The component values calculated in above have been adopted or the compensation section and soldered onto the board. The -V output is subject to a load step rom A to A in µs. As conirmed by Fig. 7, the transient response is excellent regardless o the input voltage. Fig. 6. A PSR board using O Semiconductor s P36 has been assembled. It delivers V and up to A o output current. iout t vout t ΔV = mv Fig. 7. The transient response measured at low- and high-line conditions conirms the excellent stability o the converter. 7 HowPower. All rights reserved. Page 8 o 9

19 onclusion This article has addressed two mains topics: operation o the lyback converter under primary-side regulation and use o the power stage average model to analyze its operation. We have progressed in the modeling process by irst simulating a simple QR power stage to which we have added an auxiliary winding. Finally, the sample-and-hold circuit has been brought in to complete the picture. With modern primary-side-regulated controllers, the dierence between the classical lyback topology and the PSR lies in the way the regulation is perormed. With a careully-designed transormer, the perormance in regulation and stability is very close to that o an optocoupler-based power supply. In the second part o this article, we showed the calculation o the transer unction o a primary-side regulated converter with the integration o the internal sample-and-hold network within the controller I. Thanks to the Mathcad sotware, we were able to build the Bode plot rom the transer unction and compare it to the simulation model presented earlier in the article. Both waveorms showed similar results. Finally, the needed compensation network has been deined and dimensioned to match the phase margin requirement. Thanks to this article, you are able to design the type- compensation network or a converter using PSR. O course, the same method can be used or other topologies like those used to implement power actor correction. Practically speaking, some PSR controllers are internally compensated so the designer does not have this design option. But with the O Semiconductor PSR controller cited in this article (and others that may ollow), the ability to design the external compensation network through modeling will eliminate the trial and error approach that designers may have relied on previously. Reerences. Switch-Mode Power Supplies: SPIE Simulations and Practical Designs nd edition by hristophe Basso, McGraw-Hill, ew-york,.. Simpliied analysis o PWM converters using the model o the PWM switch, parts I (M) and part II (DM) by Vatché Vorpérian, Transactions on aerospace and electronics systems, vol. 6, no. 3, May Generic average modeling and simulation o discrete controllers by Daniel Adar and Sam Ben-Yaakov, Applied Power Electronics onerence,. 4. Linear ircuit Transer Functions: an Introduction to Fast Analytical Techniques by hristophe Basso, Wiley, 6.. The k-factor: A ew Mathematical Tool or Stability Analysis and Synthesis by Dean Venable, Proceedings o Powercon, 983, pp -. About The Author Yann Vaquette has been an application engineer at O Semiconductor in Toulouse, France since.in this role he has developed several switching controllers dedicated to the lyback topology. Ater working on the design o high-requency quasi-resonant lyback converters, he has developed a high-density version o a 4-W notebook adapter. He now handles the primary-side regulated controllers amily dedicated to travel adapter applications. Yann graduated rom the ESI engineering school. During his study, Yann worked part time with O Semiconductor in Toulouse or three years beore being hired as an application engineer in the ac-dc business unit. For urther reading on modeling lyback converters, see the HowPower Design Guide and do a keyword search on primary side regulation. 7 HowPower. All rights reserved. Page 9 o 9