Peak Current Mode Control Stability Analysis & Design. George Kaminski Senior System Application Engineer September 28, 2018

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1 Peak Current Mode Control Stability Analysis & Design George Kaminski Senior System Application Engineer September 28, 208

2 Agenda Goals & Scope Peak Current Mode Control (Peak CMC) Modeling Peak CMC Buck Converters Example Verify Loop Stability with Testing Summary Contact Appendix 2

3 Agenda Goals & Scope Peak Current Mode Control (Peak CMC) Modeling Peak CMC Buck Converters Example Verify Loop Stability with Testing Summary Contact Appendix 3

4 Goals Provide you an introduction to current mode control. Help you become familiar with modeling current mode regulators using the Middlebrook & Tan y-parameter model. Provide you with a reference for further study in DC/DC converter stability. The training material can be used as a reference for future DC/DC converter applications. Provide you the background for application to other topologies boost, buck-boost, forward, push pull, half bridge, full bridge, phase shifted full bridge, flyback, sepic, etc. 4

5 Scope Stability Analysis Buck Converter Peak Current Mode Control (Peak CMC) Continuous Conduction Mode (CCM) Input Filter Not Considered 5

6 Agenda Goals & Scope Peak Current Mode Control (Peak CMC) Modeling Peak CMC Buck Converters Example Verify Loop Stability with Testing Summary Contact Appendix 6

7 Peak Current Mode Control Current Sense Vo Vc Vc Vin PWM Inductor Current SW SW ton toff T ON OFF PWM Modulator Vramp Vc Error Amp Vref The control voltage is used to control the peak inductor current. A sawtooth ramp (Vramp) is usually required for slope compensation. There are two feedback loops an inner current loop and an outer voltage loop. 7

8 Current Mode Advantages Simpler Compensation The error amplifier programs a current instead of a voltage. The output inductor is eliminated and the power stage transfer function is reduced to a single pole. A type 2 error amplifier can now be used (instead of type 3). Right Half Plane Zero (RHPZ) Buck converters do not have a RHPZ. The RHPZ in boost and buck-boost converters is not eliminated. Compensation is simplified because the restriction to keep the crossover frequency above the LC output filter is eliminated (easier to place the crossover well below the RHPZ). 8

9 Current Mode Advantages Natural Input Voltage Feed Forward The on time inductor current slope is a function of the input voltage. Δi/Δt = (Vin Vo)/L Input voltage changes are immediately corrected because the inductor current is directly compared to the error amplifier control voltage. Inherent Cycle by Cycle Current Limiting The switch current is sensed during the on time allowing cycle by cycle current limit protection. 9

10 Current Mode Advantages Stable in DCM A CCM stable converter is stable in DCM. The loop gain near the cross over is similar in both modes allowing stable operation in each. Line to Output Noise Rejection Greater than 0x improvement compared to voltage mode. First Order Transient Response (when properly compensated) The load step response is first order with minimal overshoot. Voltage mode has a second order response with ringing and overshoot. 0

11 Current Mode Disadvantages Current Sensing Required Requires high side switch or inductor current sensing. Current sense signal noise can cause unpredictable/chaotic behavior. Subharmonic Oscillations Subharmonic instability occurs when the duty cycle is 50%. Slope compensation is required. Two feedback loops an inner current loop and an outer voltage loop. Stability analysis is more complicated. Load regulation is worse in current mode due to its higher output impedance at lower frequencies.

12 When Do You Use Current Mode Control? The power supply output is a current source. Paralleling and current sharing of converters is needed. First order transient response with minimal overshoot is needed. When input noise rejection is important. Input line rejection is greatly improved with current mode control. For equivalent performance from a voltage mode converter, the loop gain must be increased significantly. When transformer flux imbalance is a concern (push-pull converters). 2

13 Where Should the Buck Current be Sensed? There are five possible locations to sense the current: A B C E Vo Vin D 3

14 Where Should the Buck Current be Sensed? A This represents the average input current and does not provide any inductor current information. Cannot be used for current mode control. B This is the inductor upslope (turn on) current and is the most common peak current mode current sense location. The switch MOSFET Rdson can be used as the sensing element. C This is the actual inductor current and it can be used for current mode control. As the current is predominately DC at this point, it is more dissipative than location B. The inductor DCR can be used as the sensing element. D This location provides downslope inductor (turn off) current. This is the wrong current for trailing edge PWM modulation. It can be used for leading edge PWM modulation in valley current mode control. E The average output current is available here (no inductor current information). Cannot be used for current mode control. 4

15 Subharmonic Oscillation Instability Instability above 50% duty cycle when operating in CCM. The inductor current will oscillate at ½ of the switching frequency. When the duty cycle is < 50% and the inductor current is perturbed, the disturbance will decrease with time (ΔI < ΔI 0 ). After a few cycles the control loop will stabilize. 5

16 Subharmonic Oscillation Instability When the duty cycle is 50% and the inductor current is perturbed, the disturbance will increase with time (ΔI > ΔI 0 ). This is subharmonic oscillation. 6

17 Subharmonic Oscillation Instability Eliminated with a compensating ramp (slope compensation). The disturbance will decrease with time (ΔI < ΔI 0 ) and after a few cycles the control loop will stabilize. The ramp can be added to the sensed inductor current signal. The ramp can be subtracted from the control voltage Vc. 7

18 Subharmonic Oscillation Instability As the duty cycle increases towards 50% and beyond: The two current loop poles become complex. The Quality Factor of the current loop increases, reducing phase margin and increasing ringing. Slope compensation lowers the Quality Factor of the current loop causing its poles to be real. What compensating ramp (m) is needed? m2 = inductor current downslope m > 0.5 x m2 (Minimum) If m = m2, then the inductor current is corrected in one cycle, the (optimal transient response). 8

19 Agenda Goals & Scope Peak Current Mode Control (Peak CMC) Modeling Peak CMC Buck Converters Example Verify Loop Stability with Testing Summary Contact Appendix 9

20 Modeling Peak CMC Buck Converters The peak current mode control model discussed is a general y- parameter small signal model. It was developed by R. D. Middlebrook and F. Dong Tan. Middlebrook, Topics in Multiple-Loop Regulators and Current-Mode Programming, IEEE Transactions on Power Electronics, April Middlebrook, Modeling Current-Programmed Buck and Boost Regulators, IEEE Transactions on Power Electronics, January Tan and Middlebrook, Unified Modeling and Measurement of Current- Programmed Converters, IEEE Power Electronics Specialist Conference, Tan and Middlebrook, A Unified Model for Current-Programmed Converters, IEEE Transactions on Power Electronics, July

21 Modeling Peak CMC Buck Converters Middlebrook and Tan Buck Y-Parameter Model Peak CMC Buck Converter Rs L Vo Vg Ncs C RL Resr Vramp PWM Modulator Vc Error Amp Vref 2

22 Modeling Peak CMC Buck Converters Basic Equations D Vo Vg Buck converter on-time duty cycle. m Vg L Vo On-time inductor current upslope. m2 Vo L Off-time inductor current downslope. Rf m N cs Rs Vramp fs Rf Effective current sense resistor. Slope compens ation ramp. n 2m Numerical parameter relating m to m. m 22

23 Modeling Peak CMC Buck Converters Basic Equations Dmax n n Maximum on-time duty cycle with s lope compens ation (no subharmonic oscillation). dmin d D R Vo Io m 2 m Lowest value of - D (off-time duty cycle) for stability. Off-time duty cycle. Must be greater than dmin for current loop stability. Y-parameter model operating point. K 2L fs R Conduction parameter. Must be greater than d to avoid discontinuous conduction. 23

24 Modeling Peak CMC Buck Converters Current Loop Quality Factor (Qs) - Controlled by the compensation ramp and can approach infinity (subharmonic oscillation at fs/2) if dmin > d. 2 Qs d dmin Angular Switching Frequency (ωs in rad/sec) s 2 fs Current Loop Sampling Pole (ωp in rad/sec) Needed because the duty cycle is determined only once per switching period. p s d dmin 4 s 2 Qs fp p 2 24

25 Modeling Peak CMC Buck Converters Extrapolated Current Loop Crossover Frequency (ωc in rad/sec) This is not necessarily the crossover because of the potential influence of fp. fc goes to infinity at the stability limit (n x d - D = 0). c s ( nd D) s d dmin s 2 Qs fc c 2 Current Loop Transfer Function (Closed Loop) Gcl( f) Qs s( f) s 2 s( f) s

26 Modeling Peak CMC Buck Converters If Qs < 0.5 (overdamped) or Qs = 0.5 (critically damped): The current loop crosses over with a - slope at fc. Both fp and fc poles are real. The sampling pole is insignificant. As Qs increases significantly beyond 0.5 (underdamped): The current loop poles become more complex. The sampling pole becomes more significant. fs fp fc 2 The crossover moves toward fs/2 with a -2 slope (subharmonic oscillation). Slope compensation lowers Qs. Current loop poles to be more real. fc fs 2 fp 26

27 Modeling Peak CMC Buck Converters Current Loop and Qs 40 Closed Loop Current Gain 20log Gcl f i 0. 20log Gcl f i log Gcl f i 20log Gcl f i fs 2. MHz f i fp( 0.) MHz fc( 0.) 0 khz Qs 0. fp( 0.5) 2.2 MHz fc( 0.5) 550 khz Qs 0.5 fp( ). MHz fc( ). MHz Qs Gcl( f Qs) Qs s( f) s 2 s( f) s 2 2 fp( 0) 0 khz fc( 0) MHz Qs 0 27

28 yc x vc y2 x vo y2 x vg y2c x vc Modeling Peak CMC Buck Converters Y-Parameter Circuit Model vg vo y y22 28

29 Modeling Peak CMC Buck Converters Buck Y-Parameters (Parameters change with the topology) s( f) 2 fj y2( f) D nd KR s( f) 2 fc y2c( f) Rf s( f) 2 fc y22( f) nd D KR s( f) 2 fc s( f) s( f) D y( f) cd 2 R c 2fs s( f) 2 fc y2( f) c2d R c2 2fs s( f) 2 fc yc( f) D Rf s( f) L R s( f) 2 fc nd c c2 K nd K D 29

30 Modeling Peak CMC Buck Converters Open Loop Transfer Functions Control to Output Transfer Function (Ac) Ac( f) vo vc s( f) 2 fp y2c( f) y22( f) ZL( f) s( f) 2 fp ZL(f) is the load impedance and includes the output filter capacitance. Line to Output Transfer Function (Ag) Ag( f) vo vg Output Impedance (Zo) s( f) 2 fp y2( f) s( f) 2 fp y22( f) ZL( f) Zo( f) s f ( ) y22( f) ZL( f) 2 fp 30

31 Agenda Goals & Scope Peak Current Mode Control (Peak CMC) Modeling Peak CMC Buck Converters Example Verify Loop Stability with Testing Summary Contact Appendix 3

32 Example Synchronous Buck Vg = 4V (minimum) Vo = 3.3V Io = 3.3A Vg Rs Ncs PWM L C Resr R Vo RL Po = 0.89W RL = Ω Vramp fs = 2.2MHz L = 2.2μH C2 C = 30μF R2 C Resr = 2mΩ Rs = 25mΩ PWM Modulator Vc Error Amp Vref Ncs = 0 32

33 Example D Vo Vg 82.5 % On-time duty cycle. m Vg L Vo 0.38 amp s On-time inductor current slope. m2 Vo L.5 amp s Off-time inductor current slope. Rf N cs Rs 250 m Effective current sense resistor. m m2 Vramp fs Rf Set slope compensation equal to m2. Vramp m2 Rf fs mv Compensating ramp peak voltage. Vramp 80 mv m Vramp fs Rf.58 amp s Slope compensation. 33

34 Example 2m n Numerical parameter relating m to m. m Dmax n n 9.6 % Maximum on-time duty cycle with slope compensation. D 82.5 % On-time duty cycle with minimum input votage (Vg = 4V). dmin 2 m m d D 7.5 % 8.4 % Lowest value of d = - D for stability. Off-time duty cycle. Must be greater than dmin for current loop stability. R Vo Io Operating point. K 2L fs R 9.68 Conduction parameter. Must be greater than d for continuous conduction. 34

35 Example Current Loop Quality Factor (Qs) - Controlled by the compensation ramp and can approach infinity (subharmonic oscillation at fs/2) if dmin > d. 2 Qs d dmin Angular Switching Frequency (ωs) s 2 fs rad fs 2.2MHz sec Current Loop Sampling Pole (ωp) Needed because the duty cycle is determined only once per switching period. p s d dmin rad sec p s 2 Qs rad sec fp p 2.89 MHz 35

36 Example Extrapolated Current Loop Crossover Frequency (ωc) This is not necessarily the crossover because of the potential influence of fp. fc goes to infinity at the stability limit (n x d - D = 0). c s d dmin rad sec c s ( nd D) rad sec c s 2 Qs rad sec fc c khz nd D.092 Must be greater than zero for current loop stability. 36

37 Example Gcl( f) Qs s( f) s( f) Qs s s fp MHz fs 2 Closed Loop Current Gain fc fp fs 2 fc. MHz fc 64 khz 20log Gcl f i With Qs 0.5, the current loop is critically damped (the sampling pole is insignificant). The current loop crosses over with a - slope at fc. Both fp and fc are real. f i 37

38 Example Open Loop Control to Output Transfer Function (Ac) Ac( f) vo vc s( f) 2 fp Ac( f) y2c( f) s( f) 2 fp y22( f) ZL( f) ZL(f) is the load impedance and includes the output filter capacitance. 20log Ac( 30kHz) 3.22 arg( Ac( 30kHz) ) deg 20 Control to Output Gain (db) and Phase (Degrees) log Ac f i arg Ac f i f i 38

39 Example Open Loop Line to Output Transfer Function (Ag) Ag( f) vo vg s( f) 2 fp Ag( f) y2( f) s( f) 2 fp y22( f) ZL( f) 20log Ag( 20 Hz) Line to Output Transfer Gain (db) 40 20log Ag f i f i 39

40 Example Open Loop Output Impedance (Zo) Zo( f) s( f) 2 fp y22( f) ZL( f) Zo( 30kHz) m 0 3 Outp ut Imp edance (mohm) Zof i f i 40

41 Example Error Amplifier Compensation Select the desired crossover frequency (fvc): fvc = 30kHz Calculate the error amplifier gain (Gea) needed at fvc: Gea Ac( fvc) log ( Gea) 3.22 Select the desired phase margin (Φ margin ): margin 65 Calculate the error amplifier phase boost (Φ boost ) from 90 needed at fvc: boost margin arg( Ac( fvc) ) arg( Ac( 30kHz) ) deg boost 57 4

42 Example Type 2 Error Amplifier R = 0kΩ R2 = 7.8kΩ C = 000pF C2 = 00pF f z 2 R2 C 8.94 khz f po 2 ( C C2) R C C2 f p2 2 R2 C C khz khz G ea ( f) V c V o R2 C s( f) C2 s( f) R2 C s( f) C2 s( f) R s( f) 2 s( f) 2 f po f z s( f) 2 f p2 42

43 Example Type 2 Error Amplifier Gain and Phase 60 Error Amp lifier Gain (db) and Phase (Degrees) log G ea f i arg G ea f i G ea ( fvc).65 Gea.449 f i 46.4 arg G ea ( fvc) boost

44 Example Loop Gain (T) T( f) G ea ( f) Ac( f) 75 Loop Gain & Phase Margin f c log T f i arg T f i f i Crossover Frequency (fc) = 33.0kHz Phase Margin =

45 Example Closed Loop Line to Output Transfer Function (Agf) Agf ( f) Ag( f) T( f) Closed Loop Line to Output Transfer Function 20log Agf ( 20 Hz) Closed Loop Line to Output Gain (db) 60 20log Agf f i f i 45

46 Example Closed Loop Output Impedance (Zof) Zof( f) Zoff c Zo( f) T( f) m Closed Loop Output Impedance 50 Closed Loop Out put Impedance (mohm) 000 Zoff i f i 46

47 Agenda Goals & Scope Peak Current Mode Control (Peak CMC) Modeling Peak CMC Buck Converters Example Verify Loop Stability with Testing Summary Contact Appendix 47

48 Verify Loop Stability with Testing Always measure the loop (Bode Plot) of your switch mode converter design. Make sure that loop was tested at extreme operating conditions and not just nominal conditions. Do not rely only on an analysis. The measurement should confirm your analysis. This gives credibility to your analysis and your understanding of the design. Measure the transient load step response of your switch mode converter. This ensures that the over/undershoot is acceptable and that there is not excessive ringing. 48

49 Agenda Goals & Scope Peak Current Mode Control (Peak CMC) Modeling Peak CMC Buck Converters Example Verify Loop Stability with Testing Summary Contact Appendix 49

50 Summary Understand when to use peak current mode control. What are the advantages/disadvantages? Avoid subharmonic oscillation. Add slope compensation. Model your converter: Design the compensation to meet your performance objectives. Verify internally compensated designs are stable with good performance. Always verify the loop stability with testing. 50

51 Agenda Goals & Scope Peak Current Mode Control (Peak CMC) Modeling Peak CMC Buck Converters Example Verify Loop Stability with Testing Summary Contact Appendix 5

52 Contact For further information please contact George Kaminski Senior System Application Engineer IFAM ATV SMD AMR M SRM George.Kaminski@infineon.com 52

53 Agenda Goals & Scope Peak Current Mode Control (Peak CMC) Modeling Peak CMC Buck Converters Example Verify Loop Stability with Testing Summary Contact Appendix 53

54 Appendix Modeling Peak CMC Buck Converters Tan Thesis Reference Modeling Peak CMC Buck Converters Basic Definitions TLS420 EXCEL Stability Tool Voltage Mode Review When Do You Use Voltage Mode Control The K Factor Method 54

55 Modeling Peak CMC Buck Converters Additional reference: Thesis by Fang Dong Tan, 994, Modeling and Control of Switching Converters: I. Unified Modeling and Measurement of Current- Programmed Converters II. A Generic Averaged Model for Switches in DC to DC Converters 55

56 Modeling Peak CMC Buck Converters Basic Definitions Vg = input voltage Vo = output voltage Vc = Error amplifier output (control voltage) Vref = Error amplifier reference voltage L = buck output inductance C = buck output capacitance Resr = buck output capacitor ESR ZL = the effective output impedance (load and output capacitor) fs = converter switching frequency Po = output power Io = output load current RL = output load resistance (Po/Vo) Vramp = compensating ramp peak voltage at the end of the switching period. Rs = current sense resistance Ncs = current sense gain 56

57 TLS420xx 2A Sync Pre-Regulator Family Key Specification VIN : 3.7V.. 40V VOUT : 5V, 3.3, ADJ Wide Switching Frequency 320kHz.. 2.8MHz 00% duty cycle Current mode with PWM and PFM, Internal compensation EN, PGOOD, Spread Spectrum Over-Voltage / Under-voltage monitoring Current consumption : 25µA (ON mode) Efficiency : > 90% Package: TSDSO4 Block Diagram Competitive Advantages Ease of use (integrated compensation, sync rectification) Suitable for cranking application Low noise / EMC optimized 57

58 TLS420 EXCEL Stability Tool 58

59 Voltage Mode Review Voltage Mode Control (VMC) The control voltage (Vc) is compared to a fixed sawtooth ramp voltage to generate the duty cycle of the converter switch. Vo Vramp Vin PWM Vc Vramp Vc SW SW ton toff T ON OFF PWM Modulator Vramp Vc Error Amp Vref 59

60 When Do You Use Voltage Mode Control? Low cost applications (fewest components). Light load applications where the current ramp is too small for stable operation. Noisy applications where the current ramp signal could be disturbed. Good cross regulation is needed with multiple outputs. Voltage mode with (feed forward) in applications with wide input voltage ranges. Current mode has natural voltage feed forward. However, current mode requires slope compensation for high duty cycles which complicates the compensation circuit. 60

61 K Factor Method A design oriented method for designing error amplifier compensation circuits is described in: H. Dean Venable, The K Factor Method: A New Mathematical Tool for Stability Analysis and Synthesis ool%20for%20stability%20analysis.pdf 6

Chapter 3 : Closed Loop Current Mode DC\DC Boost Converter

$Chapter 3 : Closed Loop Current Mode DC\DC Boost Converter$ Chapter 3 : Closed Loop Current Mode DC\DC Boost Converter 3.1 Introduction DC/DC Converter efficiently converts unregulated DC voltage to a regulated DC voltage with better efficiency and high power density.