DC/DC Converter. Introduction

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1 DC/DC Converter Introduction This example demonstrates the use of Saber in the design of a DC/DC power converter. The converter is assumed to be a part of a larger system and is modeled at different levels of abstraction utilizing a top down design methodology. That is, starting at a very high level of abstraction and working down into a more and more detailed design until finally a physically realizable circuit is developed. High level design requirements: o Voltage in, voltage out o Current out o Transient performance Questions answered: o How much power does the converter need to supply to our system based on different ideal load configurations? o How does transient performance affect our overall system? Switching level converter design requirements: o Voltage in, voltage out o Current out o Line/Load regulation o Ripple voltage/current o Transient performance Questions answered: o Can the chosen topology meet all requirements? o What is the actual power system performance under ideal switching conditions? How does the switching level version respond to load changes? o Does the system start up correctly? o Is the system stable over the range of specifications? 1

2 Abstraction Levels There are two levels of abstraction included with the current release: level 0 - system level, averaged level 1 - ideal switching level At level 0 abstraction, the DC/DC converter is described behaviorally. Most of the basic functionality of a DC/DC converter is covered. The output of the level 0 model does not include some secondary effects, such as switching ripple. The only non-ideal characteristic included in the level 0 model is the following: Dynamic response (overshoot and settling time) to a step change in input voltage or output current can be specified; This level of abstraction is useful for system level simulation when detailed characteristics of a dc/dc converter are not required. Fast simulation times can be achieved with this level of model. Simulating Level 0 This example includes a schematic for running a simulation with this design. The Saber command for a typical time domain transient simulation for this design is given below. Schematic: dcdc_behavioral_test.ai_sch Simulation command: tr (monitor 1000,siglist /...,tend 1m,trip zero,tstep 1n 2

3 Simulating Level 1 For level 1 abstraction, the dc/dc conversion is realized using a 2 switch forward converter topology. Break up the design into pieces to make the process easier. The following 4 circuits are used in the design process. 1. This design is just the power stage of the converter. It provides nominal operation but no regulation. Schematic: dcdc_switch_level_power_stage.ai_sch Experiment: fwd_pwr_stg.ai_exp 2. This design is used in an intermediate design step to aid in designing the compensator. The power stage is replaced with a state-averaged model and a behavioral compensator block is added in the feedback loop. Provide Experiment fwd_avg_cntrl2out_ol.ai_exp to perform transient and open-loop control-to-output ac analysis. Then, provide a second Experiment fwd_avg_loop.ai_exp to evaluate the system loop response, after the compensator is designed. Schematic: dcdc_averaged_comp10b.ai_sch Experiment (open loop): fwd_avg_cntrl2out_ol.ai_exp Experiment (system loop response): fwd_avg_loop.ai_exp 3. This design is the same as #2 above except that you replace the behavioral compensator block with an ideal opamp circuit. This circuit is used to validate the compensator design. Schematic: dcdc_averaged_opamp.ai_sch Experiment (open loop): fwd_avg_cntrl2out_ol.ai_exp Experiment (system loop response): fwd_avg_loop.ai_exp 4. This design represents the final dc/dc converter design including the power stage, compensator, and modulation circuitry. Schematic: dcdc_switch_level_final.ai_sch Experiment: fwd_pwr_stg.ai_exp 3

4 At this level, you can explore the circuit topology of various function blocks, particularly, the control compensation scheme. From this point in the design process, it is possible to include additional circuitry such as over-current protection or soft start capability. Design Specifications The circuit topology selected for this tutorial is a 2 switch forward converter. The design specifications are given in Table 1. The circuit configuration and specifications are somewhat arbitrary as it is intended that the design process be extensible to other types of converters with varied specifications. Table 1 Design Specifications Specification Value Input Voltage 288V Output Voltage 14V Nominal Power 300W Maximum Power 375W Efficiency 85% Output Regulation 1.5% Input Voltage 85% to 115% of nominal Output Ripple Voltage 25mV Inductor Ripple Current <5% Switching Frequency 200kHz Design Methodology In this section, the design procedure is described for each level. The level 0 design (high level) uses the behavioral DC/DC converter block called by dcdc_1_os. The level 1 design implements the actual converter topology. To facilitate the ease and speed of the design process, this level employs ideal components which may later be substituted for characterized component models. Table 2 shows the model usage for each level. 4

5 Table 2 Design Level Model Usage Transforme Switches Diodes Compensat Behaviors to Level r or simulate Level 0 N/A N/A N/A N/A System level verification for DC and transient Level 1 Xfrl2 Ideal Ideal Op1 Can ideally simulate all converter design specifications. 5

6 High Level Design In order to provide fast, easy verification of the overall system design, use level 0 or a behavioral model. You can characterize the dcdc_1_os model to include most of the effects available in an actual converter design. The characteristics covered by this model include line/load regulation, overshoot, settling time, and protection features. Since there is no switching going on in the model there are no ripple effects or losses due to the switches as would be encountered with a physical converter design. Figure 1 shows the test circuit used to characterize the high level model. This design is available as dcdc_behavioral_test.ai_sch Figure 1 - High Level Model Test Circuit 6

7 Switch Level Design During this design phase, the 2-switch forward converter is implemented using high-level ideal component level models. This allows quick and easy evaluation of the design by postponing the need to select power switching devices and drive circuitry until you determine some of the more high-level design considerations. Given below is the design of the power stage and then the compensation circuitry. Power Stage Design the power stage to meet the design specifications given in Table 1. Figure 2 is a schematic representation of the switch level design. This design is available as dcdc_switch_level_power_stage.ai_sch 7

8 Figure 2 - Switch Level Power Stage The first step of the design process is to define the switching duty cycle and turns ratio of the transformer. Note that you design the converter for use in Constant Conduction Mode (CCM). The following equation defines the relationship between the input and output voltage of the converter: Vout = (Vin/n)*D (1) Where Vout = dc output voltage n = transformer turns ratio (np/ns) D = Duty cycle 8

9 Vout and Vin are given in the design specification. If you select the duty cycle to be 0.3, then the turns ratio is calculated to be ~6. This calculation does not take into account the voltage drop of the diode between the transformer and the actual output of the converter. To correct for the diode drop, you can alter the duty cycle. Rearranging equation 1 and adding the diode voltage yields the following relationship: D = ((Vout+Vdiode)*n)/Vin = (( )*6)/288 = (2) The transformer model xfrl2 allows the characterization of the winding inductances either by electrical specification or by magnetic specification. Since, you do not perform magnetics modeling at this stage of the design process, the inductances are calculated based on electrical specifications. First, you can calculate the nominal input power: Pin = Pout/efficiency = 300/0.85 = 353W (3) Next the input current: Iin = Pin/Vin = 353/288 = 1.225A (4) Next the conduction time: T = (1/f)*D = (1/200000)* = 1.55uS (5) The inductance of the primary winding: Lp = (Vin*T u)/1.225 = 0.365mH (6) The inductance of the secondary winding: Ls = Lp/n2 = 0.365m/36 = 0.01mH (7) The next step of the power stage design is to design the output filter which consists of an inductor and a capacitor. Calculate the inductor value to limit the ripple current based on the design specification. And calculate the capacitor value to limit the ripple voltage. 9

10 First, determine the value of allowable inductor current from the specifications. The nominal output current can be calculated by: Iout = Pout/Vout = 300/14 = 21.43A (8) The ripple current is then: 21.43*0.05 ~ 1A Since VL = L(di/dt) then L = (VL*dt)/di Where dt is the maximum off time of the inductor current waveform. VL = 14V di = 1A Dt = (1-D)/f = ( )/ = 3.45uS (9) Therefore the inductor value is: L = (14*3.45u)/1 = 48.3uH Now calculate the output capacitor value using the inductor ripple current and the ripple voltage specification. C = Iripple/(8*f*Vripple) = 1/(8*200000*.025) = 25uF (10) After designing the component values for the power stage, you can simulate and validate the design for nominal operation. One last task is to calculate the nominal load value. Rload = Vout/Iout = 14/21.43 = Figure 3 shows the simulated results for the output voltage and inductor current after running a transient simulation analysis. The experiment editor file fwd_pwr_stg.ai_exp is provided as a means to perform this analysis. 10

11 Figure 3 - Simulation Results for Power Stage Compensation Stage Now that the power stage has been designed to work under nominal conditions, add the compensation circuitry to the design to provide regulation. The feedback loop consists of an error amplifier or compensator and modulation circuitry to provide PWM control of the switches. In order to perform the AC analysis required to design the compensator, use a state-averaged model of the power stage. You also use a behavioral compensator block to facilitate the design process. Figure 4 shows the circuit used for designing the compensation circuit. This circuit is available as dcdc_average_comp10b.ai_sch. The selector switch in the feedback loop allows this circuit to be used for transient, open-loop AC and closed-loop analysis. If you perform a transient analysis on the 11

12 averaged model, it should yield the same results as the switching model with the exception of the switching ripple. This allows us to use the averaged model for performing AC analysis and also makes for very fast simulation times. You can determine several of the requirements for the compensator without even simulating. The desired crossover frequency will be ¼ of the switching frequency or 50KHz and the desired roll off at the crossover frequency is 20dB/decade. This should yield a phase margin of around 50 degrees. As the output filter of the power stage has 2 poles, the compensator needs 2 zeros to compensate the phase shift. These 2 zeros are placed at ½ of the resonant frequency of the output filter. The compensator also needs a pole at the crossover frequency to counter the effects of the capacitor ESR at higher frequencies. The compensator block called comp10b is a behavioral model for a 2-pole 2-zero compensator which provides an easy way for us to add these effects without needing to calculate any component values. Figure 4 - Compensation Design Circuit The first step to characterizing the compensator block is to determine the resonant frequency of the output filter: fr = 1/(2**sqrt(L*C)) = 1/(2*3.141*sqrt(48.3u*25u)) = 4580Hz (12) Define the zeros of the comp10b model by the parameters w1 and w3, which are set to ½ of 4580 or 2.3KHz. The parameter w2 denotes the pole of the compensator, which is set to 50KHz. The comp10b model provides the equivalent of a voltage divider in the parameter dcoff. This is the offset between the converter output voltage and the reference voltage that you use. In this case dcoff is14-5=9v. The only parameter left to be determined for the compensator block is k. This is the low frequency gain at 1/(2) or Hz. To determine the value of k, you must perform an open- 12

13 loop control-to-output AC analysis. Use this to determine how much additional loop gain is required to ensure that the transfer function provides 0dB gain at the crossover frequency. The experiment editor file fwd_avg_ctrl2out_ol.ai_exp is provided to perform the necessary analysis using the circuit of Figure 4. Figure 5 shows the resulting bode plot of the transfer function. Figure 5 - Averaged Model Control-to-Output Transfer Function As can be seen in Figure 5, you require an additional dB of loop gain at the crossover frequency. Also, you require an additional 3dB of gain due to the compensator pole at the crossover frequency for a total additional loop gain at 50KHz of dB. Now you can calculate the value of the low frequency gain of the compensator (k). The gain of the compensator at 50KHz needs to be dB as previously determined. The gain at 2.3KHz is: *log(50k/2.3k) = -7.7dB 13

14 This is because the transfer function is increasing from 2.3kHz to 50KHz at 20dB/decade. The gain at 0.159Hz is therefore: *log(2.3k/0.159) = 75.5dB The gain decreases at 20dB/decade from.159hz to 2.3KHz This yields a value for k of: 10^(75.5/20) = Verification Methodology High Level Design Table 3 lists the parameters you use to characterize the dcdc_1_os model. Table 3 - dcdc_1_os parameters Para meter Voutnom Vinnom Input Output Transient efficiency Value 288V 14V Vinon=243,vinmin=244,vinmax=331,vinoff=332 Loadreg=1.5,diout=25,linereg=1.5,dvin=43,ioutnom=25 Ioutmax_vs_vin[0,0,243,0,244,27.2,288,26.8,331,26.4,332,0 os_line=0.05,ts_line=0.1m,dvin=undef,os_load=0.05,ts_load=0.1m,diout =undef Eff0=0.85,eff_data= 14

15 Figure 6 shows the results of a transient simulation using the behavioral model. Note the start up transients. Figure 6 - Simulation Results for Behavioral Model 15

16 Switch Level Design After designing the compensator based on the control-to-output transfer function, you can verify the loop response of the system. The experiment editor file fwd_avg_loop.ai_exp has been provided to run this analysis. Figure 7 shows the system AC loop response. Note that the gain at 50KHz is near 0 and the phase margin is 51.5 degrees. Figure 2 - Loop Response of Compensated System 16

17 Now that you have designed the compensator design using the comp10b behavioral model it can be easily converted into an equivalent opamp circuit. The circuit shown in Figure 8 provides the same results as comp10b using the ideal opamp model op1. Figure 3 - Ideal Opamp Compensator Circuit 17

18 At high frequencies, the capacitors in the opamp circuit look like shorts. Therefore the high frequency gain is determined by the ratio of R2/R3. As you have already determined that the compensator gain at 50KHz needs to be dB, you can use this to determine the values for R2 and R dB = log-1(18.977/20) = 8.89 If R2 is chosen to be 50K then R3 = 50k/8.89 = 5.62k Next, you can determine the low frequency gain required for the 2 compensator zeros at 2.3KHz by: Av(2.3KHz) = 8.89*(2.3K/50K) = This gain is determined by R2/(R3+R1). You can solve R1 using the previously determined values for R2 and R3 yields: R1 = R2/0.409-R3 = 50K/ k = K Then you can calculate the final resistor value R4 based on the voltage divider formed by R1, R3, and R4. Knowing that the output voltage of the power stage is 14V and assuming a 5V reference voltage, you can solve R4 by: R4 = (5/9)*(R1+R3) = (5/9)*(116.63K+5.62K) = 67.92K You can calculate the capacitor values based on the low frequency (2.3KHz) poles that they contribute. C1 = 1/(2**R1*2.3K) = 1/(2*3.141*116.63K*2.3K) = 593.3pF C2 = 1/(2**R2*2.3K) = 1/(2*3.141*50K*2.3K) = 1384pF Figure 9 shows the circuit of figure 4 with the new compensator circuit in place of the behavioral block. You can use this configuration to validate the transfer function of the compensator design. This circuit is available as dcdc_averaged_opamp.ai_sch 18

19 Figure 4 - Averaged Model with Opamp Compensator Using the fwd_avg_loop.ai_exp file to run the loop analysis on this new configuration yields the results displayed in Figure 10. These results show us that the compensator is performing as expected. Figure 5 - System Loop Response with Opamp Compensator 19

20 Now that the compensator design is complete, you can replace the averaged model with the switch circuit and transformer. To complete the design, you can add some simple modulation circuitry and perform validation testingd. Figure 11 shows the final switch level design including the modulation circuitry. This design is available as dcdc_switch_level_final.ai_sch. Figure 6 - Final Switch Level Converter Design 20

21 Figure 12 shows the simulation results for the final design. In this simulation, you varied the load resistance and input voltage +/- 15% from their nominal values in order to validate the regulation characteristics of the converter. Of course for the design using ideal components, the regulation percentages are well below the specification. Figure 7 - Test Results for Switch Level DC/DC Converter 21

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