ON THE CIRCUIT ORIENTED AVERAGE LARGE-SIGNAL MODELING OF SWITCHING POWER CONVERTERS AND ITS APPLICATIONS

Transcription

1 ON THE CRCUT ORENTED AVERAGE LARGE-SGNAL MODELNG OF SWTCHNG POWER CONVERTERS AND TS APPLCATONS Carlos Eduardo Cuadros Ortiz Dissertation submitted to the Faculty o the Virginia Polytechnic nstitute and State University in partial ulillment o the requirements or the degree o Doctor o Philosophy in Electrical Engineering Dushan Boroyevich, Chairman Douglas Lindner Jacobus Van Wyk Ricardo Burdisso Virgilio Centeno William Baumann August 8, 003 Blacksburg, Virginia Keywords: average modeling, slow dynamics maniold, PWM converters, ZVS and ZVZCS ull-bridge converters, sot-switched three-phase buck rectiier, space vector modulation.

2 ON THE CRCUT ORENTED AVERAGE LARGE-SGNAL MODELNG OF SWTCHNG POWER CONVERTERS AND TS APPLCATONS Carlos Eduardo Cuadros Ortiz ABSTRACT A systematic and versatile method to derive accurate and eicient Circuit Oriented Large Signal Average Models (COLSAMs) that approximate the slow dynamics maniold o the moving average values o the relevant state variables or Pulse-Width Modulated (PWM) dc to dc and three-phase to dc power converters is developed. These COLSAMs can cover continuous conduction mode (CCM) as well as discontinuous conduction mode (DCM) o operation and they are over one order o magnitude cheaper, computation wise, than the switching models. This method leads primarily to simple and eective input-output oriented models that represent transer as well as loading characteristics o the converter. Sine these models consist o time invariant continuous unctions they can be linearized at an operating point in order to obtain small-signal transer unctions that approximate the dynamics o the original PWM system around an orbit. The models are primarily intended or sotware circuit simulators (i.e. Spice derived types, Saber, Simplorer, etc), to take advantage o intrinsic eatures such as transient response, linearization, transer unction, harmonic distortion calculations, without having to change simulation environment. Nevertheless, any mathematics simulator or ordinary dierential equations can be used with the set o equations obtained through application o Kircho s laws to the COLSAMs. Furthermore, the COLSAMs provide physical insight to help with power stage and control design, and they allow easy interconnection among themselves, as well as with switching models, or complete analysis at dierent scales (time, signal level, complexity; interconnectivity).

3 A new average model or the Zero-Voltage Switched Full-Bridge (ZVS-FB) PWM Converter is developed with the above method and its high accuracy is veriied with simulations rom a switching behavioral model or several circuit component values or both CCM and DCM. ntrinsic positive damping eects and special delay characteristics created by an energy holding element in a saturable reactor-based Zero-Voltage Zero-Current Switched Full-Bridge (ZVZCS-FB) PWM converter are explained or the irst time by a new average model. ts large signal predictions match very well those rom switch model simulations whereas its small-signal predictions are veriied with experimental results rom 3.5 kw prototype modules. The latter are used in a multi-module converter to supply the DC power bus in and aircrat. The design o control loops or the converter is based on the new model and its linearization. The ZVZCS-FB PWM converter s average model above is extended to deal with interconnection issues and constraints in a Quasi-Single Stage (QSS) Zero-Voltage Zero- Current Switched (ZVZCS) Three-Phase Buck Rectiier. The new model reveals strong nonlinear transer characteristics or standard Space Vector Modulation (SVM), which lead to high input current distortion and output voltage ripple inadmissible in telecommunications applications. Physical insight provided by this average model led to the development o a combined modiied SVM and eed-orward duty-cycle compensation scheme to reliably minimize the output voltage ripple. Experimental results rom a 6 kw prototype validate large signal model or standard and modiied SVM, with and without duty-cycle compensation scheme.

4 ACKNOWLEDGEMENTS would like to express my sincere appreciation to my advisor, Pro. Dushan Boroyevich, or his guidance, encouragement, patience and support through the course o this work. also wish to thank Pros. William Baumann, Ricardo Burdisso, Virgilio Centeno, Douglas Lindner and, Jacobus van Wyk or their contributions and suggestions as members o my committee. Special thanks are due to my ellow classmates Sriram Chandrasekaran and Kunrong Wang or writing the control program, designing and building the prototype and discussing technical issues or the three-phase rectiier. Without their help, this work would not have been possible. n addition, would like to thank all the aculty, sta and students at CPES or all their support, collaboration and riendship. iv

5 To Ligia, Maria Fernanda and Miguel Eduardo

6 Table o Contents 1. NTRODUCTON Motivation and Goals Literature Review Dissertation Outline and Major Results 6. MATHEMATCALDESCRPTON OF SWTCHNG POWER CONVERTERS AND THER LARGE SGNAL AND SMALL- SGNAL MODELNG Characteristics and State-Space Description o PWM Converters Continuous-time state-space equations Sampled-data state-space equations Sampled-data modeling o a simple PWM converter Generalized Method o Averaging or PWM Converters Procedures o the method llustration o the generalized method o averaging or a simple PWM Converter Generalized method o averaging or the open loop buck converter Averaging Method or Two-Time Scale PWM Converters State-space description or two-time scale PWM converters Practical procedure or the method 5.4. Synthesis Method or Averaged Circuit Models o PWM Converters n place-averaging PWM switch equivalent circuits 9.5. Analysis o Strengths and Weaknesses o these Methods A New Procedure or Averaged Circuit Models Philosophy o the new average modeling procedure Steps o the new average modeling procedure and their guidelines Application o the new procedure to the buck converter Model veriication and comments MODELNG OF THE ZVS-FB PWM CONVERTER ZVS-FB Converter Operation CCM operation DCM operation New Averaged Circuit Model or the ZVS-FB Converter Step 1: Fast/slow classiication o state variables Step : LT input/output parts Step 3: ndependent variable drawn rom LT input network and Dependent variable delivered to LT output network Step 4: Calculation o one-cycle average or the variables in the previous step Step 5: Calculation o algebraic constraints..67 vi

7 3..6. Step 7: mplementation o circuit oriented simulation Previous Average Models or the ZVS-FB Converter Simulation Results Transient simulations or parameter set Transient simulations or parameter set Transient simulations or parameter set Transient simulations or parameter set Transient simulations or parameter set Transient and small-signal simulations results MODELNG OF THE SATURABLE NDUCTOR BASED ZVZCS-FB-PWM DC-DC CONVERTER ZVZCS-FB-PWM Converter Operation CCM operation DCM operation New Average Circuit Model or the ZVZCS-FB Converter Step 1: Fast/slow classiication o state variables Step : LT input/output parts Step 3: ndependent variable drawn rom LT input network and Dependent variable delivered to LT output network Step 4: Calculation o one-cycle average or the variables in the Previous step Step 5: Calculation o algebraic constraints Step 7: mplementation o circuit oriented simulation dentiication and modeling o energy holding elements in ast dynamic subsystems Simulation Results Transient simulations or parameter set Transient simulations or parameter set Transient simulations or parameter set Transient simulations or parameter set Transient simulations or parameter set Transient simulations or parameter set Dynamics Comparison among Buck, ZVS-FB and ZVZCS-FB Converters Transient response and small-signal transer unction rom new average model and its linearization Small-signal experimental results MODELNG AND MODULATON SCHEME FOR QSS-ZVZCS THREE-PHASE BUCK RECTFER Three-Phase Buck Rectiier Three-phase buck rectiier averaged model Three-phase buck rectiier with single-loop control Modiied SVM (swapping) QSS-ZVZCS Three-Phase Buck Rectiier Operation vii

8 5..1. Three-phase buck rectiier and ZVZCS-FB converter synchronization QSS-ZVZCS three-phase buck rectiier operation with standard SVM Topological stages and analytical description New Average Circuit Model or the QSS-ZVZCS Rectiier Step 1: Fast/slow classiication o state variables Step : LT input/output parts Step 3: ndependent variable drawn rom LT input network and Dependent variable delivered to LT output network Step 4: Calculation o one-cycle average or the variables in the previous step Step 5: Calculation o algebraic constraints Step 7: mplementation o circuit oriented simulation Modeling o energy holding elements in ast dynamic subsystems Analysis o Variable Distortion Hardware mplementation mplementation o digital controller mplementation o decoder logic Sotware mplementation Synchronization with input voltages Compensation Scheme or Standard SVM Compensation Scheme or Modiied SVM Compatibility o Modiied SVM and Compensation Scheme with Single nput Control Strategy CONCLUSONS REFERENCES..178 A Saber Template and Schematics or Buck Converter B Saber Templates or ZVS-FB Converter Average Models C Analysis and Design Procedure or Saturable Reactor-Based Zero-Voltage Zero-Current Switched, Full-Bridge Converter and Saber Template or its Average Model.0 D Modiied Equations or Cases and 3 o QSS-ZVZCS Three-Phase Buck Rectiier Operation and or Compensated First Duty-Cycle or Case 1.4 VTA 9 viii

9 LST OF FGURES.1. PWM converter structure Simple buck PWM converter with current eedbac Buck converter circuit topologies Relevant waveorms or duty-cycle calculation Partition o PWM converter structure The PWM switch PWM-switch equivalent average circuit Starting point or new average modeling procedure Step 1: Slow/ast variables separation Step : dentiication o Linear Time nvariant input/output parts Step 3: dentiication o dependent variable drawn rom input and independent variable delivered to output LT parts Step 4: Calculation o controlled source one-cycle average Step 5: Calculation o algebraic constraints Step 6: ncorporation o eedback loop Step 7: implementation o circuit simulator oriented average model Average circuit model or buck converter in CCM operation Buck converter in DCM operation Average circuit model or buck converter in DCM Average circuit models or buck converter in CCM and DCM operation.5.0. nput/output structure average circuit models or buck converter in CCM and DCM operation Analog computation o d Analog computation o d and d with eedback loop Simulation results rom average (red-dashed) and switch (green-solid) mode. Top: duty ratios, middle: inductor current, bottom: output voltage Simulation results rom average (red-dashed) and switch (green-solid) mode ZVS-FB PWM converter Typical ZVS-FB PWM converter waveorms in CCM Typical ZVS-FB PWM converter waveorms in DCM ZVS converter equivalent average models and waveorms in CCM ZVS converter equivalent average model and waveorms in DCM Analog schematic or computation o D tr and D Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average(black) models or parameter set 1 with zero initial state or all models Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 1 with zero initial state or all models Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 1 with zero initial state or all models.. 77 ix

10 3.10. Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 1 with zero initial state or all models Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set with zero initial state or all models Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set with zero initial state or all models Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set with zero initial state or all models Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 3 with zero initial state or all models Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 3 with zero initial state or all models Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 3 with zero initial state or all models Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 4 with zero initial state or all models Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 4 with zero initial state or all models Duty ratios (top), ilter inductor current (middle) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 5 with zero initial state or all models Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 5 with zero initial state or all models Capacitor voltage (top) and ilter inductor current (bottom) transient response rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set Capacitor voltage (top) and ilter inductor current (bottom) transer unctions rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set Capacitor voltage (top) and ilter inductor current (bottom) transient response rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set Capacitor voltage (top) and ilter inductor current (bottom) transer unctions rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set....9 x

11 4.1. ZVZCS converter ZVZCS-FB PWM primary and ilter inductor current waveorms in CCM ZVZCS-FB PWM primary and ilter inductor current waveorms in DCM ZVZCS converter equivalent average models and waveorms in CCM Calculation o average blocking capacitor voltage Analog computation o D tr and D Analog implementation o dynamic relationship between ilter inductor current an blocking-capacitor peak voltage Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), irst average (blue) and second average (pink) models or parameter set 1 with zero initial state or all models Zoom in o ilter inductor current and capacitor voltage rom switching (green), irst average (blue) and second average (pink) models or parameter set 1 with zero initial state or all models Zoom in o ilter inductor current and capacitor voltage rom switching (green), irst average (blue) and second average (pink) models or parameter set 1 with zero initial state or all models Whole transient and zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 1 with zero initial state or all models Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 1 with zero initial state or all models Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 1 with zero initial state or all models Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 1 with zero initial state or all models Whole transient o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set with zero initial state or all models Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set with zero initial state or all models Whole transient o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 3 with zero initial state or all models Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 3 with zero initial state or all models Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 3 with zero initial state or all models.1 xi

12 4.0. Whole transient and zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 4 with zero initial state or all models Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 4 with zero initial state or all models Whole transient and zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 5 with zero initial state or all models Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 5 with zero initial state or all models Whole transient and zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 6 with zero initial state or all models Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 6 with zero initial state or all models Capacitor voltage (top) and ilter inductor current (bottom) transient response rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set Control to capacitor voltage (top) and control to ilter inductor current (bottom) transer unctions rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set Capacitor voltage (top) and ilter inductor current (bottom) transient response rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set Control to capacitor voltage (top) and control to ilter inductor current (bottom) transer unctions rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set Experimental control to capacitor voltage (top) transer or Buck and ZVZCS-FB converters with parameter set QSS-ZVZCS three-phase rectiier Three-phase buck rectiier and electric sectors Three-phase buck rectiier with standard SVM Three-phase buck rectiier ideal SVM operation Three-phase buck rectiier average model structure Three-phase buck rectiier SVM with and without swapping Synchronization between three-phase buck rectiier and ZVZCS-FB converter QSS-ZVZCS rectiier typical waveorms and switch structures QSS-ZVZCS PWM rectiier average model structure Calculation o average blocking capacitor voltage QSS-ZVZCS rectiier desired and experimental waveorms with typical SVM operation xii

13 5.1. QSS-ZVZCS rectiier equivalent primary and secondary duty-cycles cases with typical SVM operation Three-phase buck rectiier (solid) and QSS-ZVZCS rectiier simulated eective (dashed) primary and secondary duty-cycles or whole line cycle with SVM Normalized QSS-ZVZCS rectiier simulated and experimental dutycycles, compensation with SVM and phase voltage QSS-ZVZCS rectiier open-loop experimental phase voltage and currents and output voltage ripple with SVM, beore and ater compensation or 360V peak line voltage, 48V output voltage and 40A load current Control block diagram QSS-ZVZCS rectiier power stage or V line voltage, 48V output voltage, 6 kw output power and 40 khz switching requency QSS-ZVZCS rectiier closed-loop experimental phase voltage and currents and output voltage ripple with SVM, beore and ater compensation or 360V peak line voltage, 48V output voltage and 40A load current QSS-ZVZCS rectiier simulated and experimental duty-cycles and compensation with modiied (duty-cycle order swapping) SVM QSS-ZVZCS rectiier phase currents and secondary rectiier voltage at swapping border (phase voltage crossing) with modiied SVM QSS-ZVZCS rectiier open-loop experimental output voltage ripple, phase current and voltage with modiied SVM, beore and ater compensation or 360V line voltage, 48V output voltage and 40A load current QSS-ZVZCS rectiier closed-loop experimental output voltage ripple, phase current and voltage with modiied SVM, ater compensation or 360V line voltage, 48V output voltage and 40A load current QSS-ZVZCS rectiier closed-loop response to step load disturbance (1.6 Ohm load switched in) with swapping and compensated duty cycles or 380V peak line voltage, 48V output voltage and 1.1 Ohm initial load QSS-ZVZCS rectiier closed-loop response to step load disturbance (1.0 Ohm load switched in) with swapping and compensated duty cycles or 380V peak line voltage, 48V output voltage and 1.1 Ohm initial load..175 xiii

14 LST OF TABLES 1. Parameter value sets or transient response o ZVS-FB converter Parameter value set or small-signal model and transient response o Buck, ZVS-FB and ZVZCS-FB converters Parameter value set or small-signal model and transient response o Buck, ZVS-FB and ZVZCS-FB converters Parameter set values or transient simulations 11 xiv

15 1. NTRODUCTON 1.1. Motivation and Goals Switching power converters have become ubiquitous in consumer products as well as in industrial, medical, and aerospace equipment due to their high eiciency, low volume and weight, ast dynamic response, and low cost. Even though extensive eorts and resources are continuously devoted to new component technologies and converter the development o versatile modeling techniques suitable or general switching power converters is still lagging. This dissertation aims at reducing that gap by providing a systematic approach to the development o accurate and computationally eicient but still intuitively simple circuit oriented, average large-signal models or pulse-width modulated (PWM) ullbridge (FB) derived, dc to dc and three-phase to dc power converters. Since a large number o new converter topologies based on these structures have emerged lately, versatile and reliable models are needed to speed up exploitation o their ull potential. The objectives o the circuit oriented, continuous-time, large-signal average models developed here are, besides allowing very ast simulation times and reduced memory space with respect to discrete and switching models, to gain physical insight, to guarantee complete representation o large and small-signal behavior and to overcome limitations o existing average models by including discontinuous conduction mode (DCM) and continuous conduction mode (CCM) operation and storage element eects in the orm o algebraic and/or dynamic constraints to handle large and asymmetric ripple components as well as eedback loops. This approach makes the new models very useul in large signal analysis and design o single-stage single and multi-module converters, as well as multistage converters, together with their respective input and output ilters. n addition, the new models can be linearized at an operating point to derive a small-signal model that closely approximates the behavior around an orbit or the original system, and hence, provides a solid starting point or control design. As a result, thorough studies o 1

16 interaction eects and trade-os amongst power stage(s) and ilter(s) structures, current and voltage ripple, harmonic distortion, modulation scheme, control loop(s), stability, transient response, to name a ew, can be conducted. The systematic modeling procedure allows or easy adaptation o the models to perorm analyses at dierent scales, such as time, signal level, complexity, interconnectivity. Model extension or hybrid simulation, i.e. mixing o average and switching models, can be easily carried out to accelerate analysis o speciic subsystems in multi-stage and/or multi-module converters. Even though the new circuit oriented average models can be used with any commercial mathematics sotware that allows simulation o ordinary dierential equations, one o the major motivations or this work is to take advantage o common eatures in commercial circuit simulators, i.e. transient response, linearization, transer unction, harmonic distortion calculations; to help with power converters analysis and design issues without having to change simulation environment. 1.. Literature Review Most o the reerences mentioned in this work have excellent reerence lists therein, which are also assumed reerenced and that are omitted here or compactness. Switching power converters can be mainly classiied according to the type o input (ac or dc) and output (ac or dc) variables [E5, M7]. Further classiications with respect to parameters such as control variable, PWM, or requency modulation, [E5, M7], waveorm, i.e. piece wise linear or resonant [E5, M7], switching stresses, i.e. hard or sot [E5, J4, M7, H3, V6, V7], among others, are well known. Most common PWM power converters have switch transitions determined by control and state variables through constraint equations [B6, B11, B1, C5, C7, C8, C0,

17 E1, E3, E5, F1, G1, H6, K7, L, M7, O3, S4, T8, V3, X], and in between those transitions the converters are very accurately described by linear autonomous ordinary dierential equations. Sampled-data models [A1, B6, B1, F1, G1, G3, H4, L, L13, L15, M5, P1, T7, V3, V4] are suitable to represent and to simulate these converters at switching instants, but they lack inormation between samples and are computationally expensive. However, the closed-loop operation can be accurately described and characterization (Poincare maps) o iterative maps or instability, biurcation and chaotic behavior analysis can be easily obtained [A, B, C3, C17, D1, F4, H1, J1, L3, P4, S4, T3]. Large signal stability o PWM and quasi-resonant converters through nonlinear modeling and control has also been discussed in [C4, C17, E3, F, G3, H6, L17, S18, S19]. From all o these large signal approaches, continuous-time small-signal models can be obtained through linearization around a periodic trajectory (orbit). When the starting model is discrete subsequent transormation o the results into continuous time is needed [F1, F3, L, S17, T7, V3, W5]. Small-signal models have also been obtained rom very dissimilar perspectives such as model itting with neural networks o data rom converter simulations [H5, L7], analytical approximations [E, V11, W4], and perturbation o exponential transition matrices either on computer [M4, W5] or on state plane graphs [O4]. The well-known state-space averaging method [B11] can also be developed as the low-order approximation in several dierent methods by retaining only the irst terms in: (a) power series or the matrix exponentials in the sample-data modeling [V3], (b) multi-requency averaging [C1], (c) the generalized method o averaging [K6, L4, L6, N3, S, S13, V3, W3]. t provides inormation about the average o the state variables, but loses accuracy in the high requency range, i.e. near a hal o the switching requency, and/or when the ilter time constants are close to the switching period, as it usually happens in some o the sampled-data models above. Similar characteristics with slight result 3

18 improvements are exhibited by the current injection-absorption method [K5], by the averaged PWM-switch model [V8] and its several extensions or multi-switch PWM converters and resonant converters, and by several other circuit-oriented average models [A3, C5, C6, C7, C4, E4, J5, L9, L11, K4, M, M6, N, R1, O1, O, R1, S4, S6, S7, S8, S0, T4, T8, V1, V8, V9, V10, W3, W7, X, X4, Y]. Validity o the method o averaging to simple PWM converter topologies was rigorously proved [B3, K6, L4, S] and extended to provide requency-dependent continuous-time average models or open and closed-loop operation [B5, L5, L6]. Unortunately, application o this technique or the amiliar state-plane portrait methods [G, O3, S10], useul to analyze operation o low order resonant converters, to more complex sot-switched power converters becomes almost intractable. Analytic approximations and modiications to the method o averaging have also been proposed or PWM and some types o resonant converters [N3, S13, S14, S, W3, X3]. Extended describing unctions and multi-requency methods [C1, C18, S3, Y1] overcome this tractability problem and had been proven useul in small-signal analysis o resonant and multi-resonant converters o any order, despite their lack o physical insight and the need or special sotware. Some special simulator programs and/or algorithms have been developed to provide shorter simulation times [B6, B7, L8, M1, N1, P, S5, T, D, B9, B10] at the expense o limited unctionality and data preparation. Following the attempt made in [R4], a corrected and general continuous-time, state-space, small-signal model o current programmed PWM converters was developed in [T5, T7] and veriied with the so called exact small-signal models obtained by application o time varying transer unctions [T6, T9]. However none o these papers discusses relevance o time varying eects at requencies near a hal o the switching requency which are detailed in [P3] and analyzed or three-phase PWM modulators in 4

19 [H]. The same happens in [K5, S16, S1, S4, T1, V8, V10] where attempts to it and/or explain small-signal measurements in the high requency range were made without dealing with the stochastic characteristics o those measurements. Furthermore, extensive similar work on small-signal modeling o the modulator and/or the whole converter or peak and average current control has been reported in [B8, C19, K1, K8, L10, P5, R5, S3, S4, T1, X1]. Geometrical linearization through graphical analysis o perturbed steady-state waveorms was used in [V5] to provide an approximate small-signal model o the widely used Zero-Voltage Switched, Full-Bridge (ZVS-FB) PWM converter [S1] based on the PWM switch model. An approximate large signal model whose usage is restricted to a narrow range in CCM and a small-signal model derivation along the lines o [S1] or the ZVS-FB converter was presented in [T4]. Similarly small-signal models or some ZVS and Zero-Voltage Zero-Current Switched Full-Bridge ZVZCS-FB converters are developed in [C15, X5]. Lately, with the progress in symbolic math packages, methods to obtain closed orm expressions or large and small-signal models o PWM converters have been developed [B4, S1]. These methods separate ast and slow dynamic subsystems in the converter and describe their interaction through an algebraic equation. However, they do not allow or non-linear or energy holding components in the ast dynamic subsystem or high order systems or which closed orm solutions cannot be computed. Thereore they cannot be applied to many new sot-switched topologies [B1, C9, C10, C11, C1, C16, J, J3, J4, K, K3, L1, L1, L14, M3, V6, V7, W1, W, W6, X5]. From a dierent perspective, power transer based models [S7, S8, E5] provide good low requency description o input-output characteristics or certain PWM converters when loss-less switching devices are considered. When losses are included, the principle o energy conservation needs to be invoked [C4]. These approaches, when combined with other models such as current injection-absorption, state-space averaging, 5

20 PWM and resonant switch, are useul in model veriication as well as in calculation o input and output impedances or subsystem interaction analysis [C13, G, R3]. A ew attempts to develop a SPCE oriented dual model to deal both with CCM & DCM were plagued with convergence problems [C7, G4, S1]. n [R5] the same authors o [C7] presented a revised version that solved those problems or the buck converter. A decade later the subject was retaken in [N4] where dual models or most o the simple PWM converters are presented. As a matter o completeness the ollowing special modeling approaches are also mentioned: geometric [S9], phasor transormation [R], switching low graph [S11], virtual winding or transormer magnetizing current [L16]. For the modeling presented here on the three-phase buck rectiier and a ZVZCS three-phase to dc converter the wonderul theses [H, N] and the reerences therein provide all the needed background Dissertation Outline and Major Results. 1. Mathematical description o large signal average models or switching power converters. The next chapter reviews analytical procedures or variations o the generalized method o averaging [K6, S13] proposed or switching power converters (SPCs). The theoretical oundation behind a method to synthesize averaged circuits models or SPCs [S4] is also presented. Scope and limitations o these methods are discussed. A new systematic procedure to derive circuit oriented average models, which describe input-output characteristics or PWM converters, and that overcomes several o those limitations is developed. This procedure combines the theoretical oundation o [S4] with variations o some ideas rom in-place circuit averaging techniques in [V8, V9], extensions to constraints derivation to keep them valid during transient conditions [V3], 6

21 practices rom analog and circuit simulation in order to model CCM-DCM biurcation [R5] and heuristic guidelines or selecting averaged circuit structure and relevant states as well as or modeling energy storage components. Basic eatures o the new modeling procedure are introduced by applying it to a simple buck PWM converter. CCM and DCM operation is covered by the same average model.. Modeling o the ZVS-FB PWM converter. n Chapter 3 a new and very accurate average model or both DCM and CCM mode o operation is developed and its superiority compared to existing models is clearly seen or dierent parameter and load values. Small-signal models obtained through linearization o the new average model at dierent operating points show strong positive damping eects, i.e. intrinsic negative eedback, over the output ilter. These results agree very well with those rom experiments. 3. Modeling o a saturable reactor-based ZVZCS-FB PWM converter. Extension o the circuit averaging procedure to include new eects created by a saturable reactor and a so-called energy holding component, in power converter modeling literature, provided the only reported model or this ZVZCS converter. The model, detailed in Chapter 4, explains and recreates the interaction o power stage components, which leads to negative damping eects, i.e. intrinsic positive eedback, over the output ilter. These eects were also reported or the irst time with the model. Large signal simulation results rom the average circuit model closely match those rom a switching model or dierent parameter and load values. Small-signal models rom linearization o the average circuit model, which correctly predicted the negative damping eects seen in transer unction measurements conducted on 3.5 kw prototypes, were a useul starting point or current-loop design in a multi-module prototype. 4. Average modeling and modulation scheme development or a Quasi-Single Stage ZVZCS Three-Phase Buck Rectiier. Chapter 5 illustrates versatility o 7

22 the modeling procedure when dealing with interconnection issues in this special multi-converter structure. t is ormed by cascading a three-phase buck rectiier and the ZVZCS converter in the previews chapter. Physical insight provided by the average circuit model developed or this three-phase rectiier, which is also a new result, helped to discover the main causes o strong nonlinear relationships between commanded duty-cycles and eective duty cycles, i.e. voltage transer ratio, near the boundaries o the sixty-degree electrical sectors in standard space vector modulation (SVM). These nonlinearities induced high distortion and ripple in ac input currents and dc output voltage, which rendered the system unsuitable or the intended telecommunications application. Physical insight rom the model also helped to develop a new simple and eective modiied SVM with eedorward duty-cycle compensation scheme that reliably minimizes current distortion and voltage ripple while keeping the same single dimension control. 8

23 . MATHEMATCAL DESCRPTON OF SWTCHNG POWER CONVERTERS AND THER LARGE AND SMALL-SGNAL MODELNG This chapter starts with a review o state-space descriptions or PWM converters in continuous and discrete time orms ollowed by an outline o small-signal model derivation in both time orms. Aterwards variations o the method o generalized averaging are introduced. n addition the approaches to synthesize averaged circuit model or PWM converters are also discussed and a comparison analysis o these methods is presented. Then a new modeling procedure to obtain autonomous averaged circuits o PWM converters is outlined and illustrated through its application to the buck converter. The resulting averaged circuit covers a wide range o operation, i.e. DCM-CCM..1 Characteristics and State-Space Description o PWM Converters The PWM converters considered in this work consist o linear resistive and reactive elements, piece-wise linear switching elements with the externally controlled ones activated at a constant requency, and input and output power terminals that can exhibit ac or dc variables as depicted in Fig Continuous-time state-space equations The conditions imposed upon the elements o the power stage allow the converters to be described, in between certain switching instants t k,i, by linear timeinvariant ordinary dierential equations o the orm [V4] d dt x (t) A x(t) B u( t ) t < t t, (.1) = k,i + k,i k,i 1 k,i where state vector x(t) is n x 1, state transition matrix A k,i is n x n, input matrix B k.i is n x r and input vector u(t) is r x 1. Switching instants t k,i are determined by combinations o control parameters and/or state variables rom the power stage and control circuitry. Subscript k corresponds to switching cycle, whose duration is assumed constant and designated by T s, and subscript i corresponds to a time interval within each cycle during which the system maintains the same switch coniguration, Fig..3. Entries or matrices A k,i and B k.i depend upon switch conditions (on or o), which determine circuit structure in between switching instants, and component values. The combinations that determine the switching instants in the k-th cycle can be described by the set on m constraints c ( x(tk ), p(tk ), u( tk )) = 0, (.) where p(t k ) is a q x 1 vector o independent controlling parameters. 9

24 SOURCE (DC/AC) POWER STAGE LOAD (DC/AC) CONTROL Fig..1. PWM converter structure. 10

25 .1.. Sample-data state-space equations n general the change on the converter state-space vector x(t) over one switching cycle, i.e. rom t k to t k+1, can be expressed by the n sampled-data relations x (tk+ 1 ) = ( x(tk ), p(tk ), u( tk )), (.3) upon integration o (.1). (.,.,. ) represents a vector valued nonlinear unction that in our case can be simpliied to [V3, V4] x (tk+ 1 ) = F( p(tk )) x(tk ) + H( p(tk ), u( tk )), (.4) where F (. ) and H (. ) are n x n and n x 1 matrices respectively that involve matrix exponentials o A k,i and are easily computable in terms o A k,i, B k,i and u(t). When a dc-dc PWM converter is operating in steady state the state space vector returns at the end o the switching cycle to the same value it had at the beginning o it, i.e. x (tk + 1 ) = x(tk ) = F( p(tk )) x(tk ) + H( p(tk ), u( tk )) = X (.5) is a constant as well as p(t k )=P and u(t k )=U. As a result (.) and (.5) become and c ( X, P, U ) = 0 (.6) X = F( P ) X + H( P, U ). (.7) Small-signal dynamics o perturbations around an orbit can now be obtained by keeping up to linear terms o the Taylor series expansion o equations (.6) and (.7), i.e. and x(t k+ 1 ) = F( P + p(t k )) ( X + x(t k )) + H( P + p(t k ), U + u(t k )) X (.8) c X + x(t ), P + p(t ), U + u(t )) =, (.9) ( k k k 0 where x and p represent those perturbations. Ater carrying out some cancellations on the series expansions one obtains: 11

26 x(t k+ 1 ) = F( P ) x(t k ) + F( P ) p(t p + H( P, U ) p(t p k ) X k ) + H( P, U ) u(t u k ) (.10) and c( X, P, U ) x(t x k ) + c( X, P, U ) p(t p + c( X, P, U ) u(t u k ) k ) = 0. (.11) which are basically a discrete small-signal model in implicit orm and almost always needs to be solved numerically to compute the desired discrete transer unctions. Their continuous-time counterparts can then be computed numerically..1.3 Sampled-data modeling o a simple PWM converter Since this modeling process gets very involved or high-order systems, some simpliications based on practical converter characteristics are usually possible. To illustrate this process, the large-signal sampled-data model or the simple buck PWM converter, shown in Fig.., with the so-called peak current control and in CCM o operation is developed. n this system, in CCM operation, there are two state variables, inductor current and capacitor voltage, i.e. [ ] T x (t) = i L v C, (.1) and the two switching conigurations (circuit topologies), depicted in Fig..3, i.e. interval subscript i in (.1) takes the values 1 and. These switching conigurations are determined by the conduction state o the switch, i.e. on or o, and give origin to matrices A k,i and B k,i, 0 1 L A k,1 = Ak, = A = 1 C 1 R C, (.13) T 1 L B k,1 =, (.14) 0 and 1

27 The remaining term in (.1), input vector at ime t k, is given by 0 B k, =. (.15) 0 ( t ) v ( t ) u =. (.16) k Duration o the irst interval in transient regime is determined rom conditions represented in Fig..4 where inductor current waveorm, modulating ramp and current reerence are shown. From Fig..4 the switching constraint that determines d k (the duty ratio or interval i=1) is calculated as i k i * ( t k ) m d T = i ( t ) + m d T, (.17) r k s L k 1 k s * where i ( tk ) represents inductor current reerence (independent control parameter p(t k ) in (.)), il ( tk ) is the inductor current values at time t k, m r and m 1 correspond to modulating ramp slope and approximated inductor current slope during interval 1 respectively when capacitor voltage is assumed constant over one switching cycle, i.e. T s. The large signal sampled-data model or the buck converter, ater assumption o constant control during each interval can be described as and x(tk + dk Ts ) = F1(dk ) x(tk ) + H 1(dk ) u(tk ) (.18) x(tk + Ts ) = F( d k ) x(tk + dk Ts ) + H ( dk ) u(tk + dk Ts ), (.19) where d T = A d T A σ 1 k s s F 1( dk ) e, H ( d ) k 1 k e 1 B1 dσ = o (.0) and ( 1 d = A )T ( 1 d k s s F ( dk ) e, H ( d ) k k e B dσ = o ) T A σ. (.1) 13

28 S L v i C R i L Gate v G i Re Comp Ramp Fig.. Simple buck PWM converter with current eedback. 14

29 ON-state OFF-state S S L L V D C R V i C R i D nterval i=1 nterval i= < k t < t k d k T S t k d k T S t t k + 1 t + + < < Fig..3. Buck converter circuit topologies 15

30 nterval i=1 nterval i= nterval i=1 nterval i= V G On O On O i* i L m r m 1 m ramp i S v D v C t t k t k +d k. T s t k+1 t k+1 +d k+1. T s T S Fig..4 Relevant waveorms or duty-cycle calculation 16

31 17 Concatenation o (.8) and (.19) provides a cycle-to-cycle representation o the system that can describe the behavior either at the beginning o the cycles, (.), or at the switching instants, (.3). ( ) ). (t )) d ( ) d ( ) d ( ( ) (t ) d ( ) d ( t k k k 1 k k k 1 k 1 k u H H F x F F x + + = + (.) ( ) ). T d (t )) d ( ) d ( ) d ( ( ) T d (t ) d ( ) d ( T d t s k k k k 1 k s k k k k 1 s k 1 k = + + u H H F x F F x (.3) When control signals vary slowly as compared to switching period, the matrix exponentials can be approximated by keeping up to the linear terms in their series expansion. That is, σ σ + = i i i e A F A, (.4) and λ σ λ σ + + = i j i j i j e e A A F F A A, (.5) which are the same approximations made in the continuous-time state-space averaged method. Ater using these approximations in (.) the large-signal model becomes ( ) ) (t ) d ( ) (t ) d ( t k k k k 1 k u Ψ x Φ x + = + (.6) where ( ) ( ) S S k S k 1 k T T d 1 T d d + = + + = A A A Φ (.7)

32 and ( dk ) = ( + A TS ) B1 dk TS Ψ. (.8) Linearization o (.6), leads to an approximate discrete small-signal model o the ollowing orm x ( t ) = Φ( d ) x(t ) + ( + A T ) k + 1 k k S B T 1 S u( t Ψ( d k k ) d k ) u(t k + ). (.7) Similarly linearization o (.17) provides dk as * dk = il( tk ) /( m1 + mr ) Ts + i ( tk ) /( m1 + mr ) Ts, (.8) which when substituted in (.7) gives ater some manipulations the inal orm * ( t ) = Κ x(t ) + Λ i ( t ) + v (t ) x. (.9) k + 1 k k Μ in k Equations.1 through.7 show that large and small-signal sampled-data model can be easily and systematically obtained or simple PWM converters in open and closed loop operation. Unortunately modeling o interconnected converters rom their independent models is not a straightorward procedure and most o the time requires a complete new derivation... Generalized Method o Averaging or PWM Converters The main objective or applying the generalized method o averaging, also known as KBM (Krilov, Bogoliubov, Mitropolski), to time varying systems, such as PWM converters, is to obtain an autonomous model that closely describes a moving average o the variables in the original system. n other words, we are trying to derive a simpler model that retains some o the main properties, a slow dynamics maniold, o the initial system. 18

33 n this chapter a general description o this method ollowing the lines in [K5] and how to apply it to a simple PWM converter in CCM are presented. A simple way to estimate inormation about ripple o the variables is also discussed...1. Procedures o the method n order to apply the KBM method to a system it is necessary to cast it in the standard orm d dt x ( t ) = ε F( t, x ), x( t 0 ) = x, (.30) 0 where ε is a small non-dimensional parameter and F is a vector valued unction (see K5 and the reerences within or a rigorous justiication o averaging or (.30)). The integral 1 T G ( ) = lim F( s, )ds, (.3) T T 0 is deined as the time average o (.30) and leads to the new time-invariant averaged model () t G( y ), y( t ) y 0 0 y = ε =. (.33) When the system is periodic or quasi-periodic, as in PWM converters, the integral in (.3) is inite and hence the limit exists. The KBM method is based on the change o variables x() = y( t ) + ε ψ1( t, y ) + ε ψ ( t, y ) + ε ψ ( t, y ) +..., (.34) t 3 where ψ i are unctions o time with zero-average value, which transorms the original system, i.e (.30), into the time invariant system 19

34 d dt 3 y() t = ε G1( y ) + ε G ( y ) + ε G ( y ) +... (.35) 3 n order to obtain a set o equations in the new variable y, (.30), (.34) and (.35) need be used. First, (.34) gets dierentiated with respect to time, then (.30) is used to eliminate x&, (.35) to eliminate y&, and (.34) to eliminate x. Then terms with the same power o ε are equated to get a system o equations that can be sequentially solved or ψ i ( t, y ) and G i ( t, y ).... llustration o the generalized method o averaging or a simple PWM converter This process is presented here or single switch PWM converters in CCM operation, i.e. two intervals per switching cycle. n the next section the same process will be speciically used with the open loop buck converter. Equation.30 can be written as d dt x(t) = [ A + h( t,t + [ B s ) ( A 1 + h( t,t A s ) ( B )] x(t) 1 B )] u( t ) (.36) where matrices A i and B i correspond to those deined in (.1) or intervals 1 and ater dropping the index k, and h( t,t s ) = H [ d( t ) ramp( t,t )]. (.37) s where H(z) is the Heaviside or unit step unction, d(t) is the duty-cycle control signal and the unction ramp(t,t S ) corresponds to the PWM modulating signal. The latter is described by using the module operation t mod( T ) s ramp ( t,ts ) =. (.38) Ts Calculation o the parameter ε is perormed by selecting the largest absolute value o the entries in matrices A i and B i, designated by ξ in (.39), and multiplying it by T s, i.e. 0

35 time is scaled as { ai, j, bi, j } Ts = Ts ε = max ξ. (.39) i,j t, (.40) = T s τ equations (.36) and (.37) can be expressed in terms o ε and τ as d x( τ) = ε { dτ 1 [ A ξ [ B ξ h( τ,1 ) ( A ξ 1 h( τ,1 ) + ( B ξ A 1 B )] x( τ) )] u( τ )} (.41) and h( τ,1 ) = H [ d( τ ) ramp( τ,1 )] (.4) respectively. Thus application o the averaging operator (.3) to the right hand side (RHS) o (.41) produces 1 G( y) = [ A ξ d + ( A ξ [ B ξ A )] y d + ( B ξ 1 B )] U, (.43) where d is the average duty-cycle. The average model, ater returning to the original time scale, is given by d dt y( t) = [ A + d ( A1 A1 )] y( t ) + [ B + d ( B B )] U, 1 (.44) which is the same result obtained through state-space averaging. Estimates o variables ripple can now be computed by continuing with the KBM method. Manipulation o (.34), (.35) and (.43) leads to 1

36 ( ) [ ] ( ) ( ) ( ) ( ), ) h( 1... ) h( = G G ψ ψ G G ψ ψ G G G B B B ψ ψ y A A A ε ε τ τ ε ε ε τ τ ε ε ε ε ξ τ ξ ε ε ε ξ τ ξ ε (.45) rom where equating terms with the same power o ε gives ( ) ( ), ) h( 1 ) h( 1 : τ ξ τ ξ ξ τ ξ ε + = ψ 1 G B B B y A A A (.46) ( ) τ τ ξ τ ξ ε + + = ) h( 1 : ψ G ψ G ψ A A A 1 1, (.47) ( ) τ τ τ ξ τ ξ ε = ) h( 1 : ψ G ψ G ψ G ψ A A A 1.(.48) Equation (.46) is used to solve or G 1 by taking the average over one period with respect to τ and the result is the same as the RHS o (.44). Now G 1 is substituted in (.46) and then the constant o integration is selected to make 1 ψ zero-average and o period T s. Similarly the other unctions can be calculated to obtain a higher order approximation or variables ripple (see [K5] or modeling o the boost converter and its ripple estimation).

37 ..3. Generalized method o averaging or the open loop buck converter The converter in Fig..3 is considered here but in open loop and its continuoustime state-space equations, i.e. (.36), ater substituting (.13)-(.15) reduces to d dt x (t) = A x(t) + h( t,t ) B v ( t ), (.49) 1 s 1 in and h( t,t The average equation is then given by s ) = H [ d ramp( t,t )]. (.50) s d dt y (t) = A y(t) + d B v ( t ) (.51) 1 1 in and (.45) reduces to 1 h( τ ) ψ1 A1 y + B1 = G1 +, (.5) ξ ξ τ rom where ater some manipulations ψ 1 is obtained as 1 ψ ( ) = 1 [ h( ) d ] ramp( t,1) + [ 1 h( )] d + ( d d ) 1 τ B1 τ τ (.47) ξ and the remaining G i or i=, 3, are zero. 3

38 .3. Averaging Method or Two-Time Scale PWM Converters Most PWM converters can be classiied as one or two-time scale systems. A method or the latter, developed very similarly by dierent authors [N, S13, W3], is presented here. The ormer are already covered by the method in section State-space description or two-time scale PWM converters The two-time scale characteristics o a PWM converter can be explicitly shown by representing the system in the orm d dt () t ( t, x, y ), x( t 0 ) x0 x = ε =, (.48) d dt () t g( t, x, y ), y( t 0 ) y0 y = =, (.49) where ε is again a small non-dimensional parameter, x and y are state vectors o dimension n and m respectively, and and g are vector valued unctions. The average model or (.48) is deined as d dt () t 0 ( X ), X( t0 ) x0 X = ε =, (.50) with 1 t = Ts T + Ts ( τ, x, φ( τ, x,t, y0 )) dτ, t 0 0( x ) lim t t s, (.51) where φ ( τ, x,t, y0 ) is the solution o (.49) with initial value y ( t ) = y0 and ixed x. 4

39 When x is ixed switch patterns in PWM converters do not change, and hence, i φ, x,t, y ψ τ, x in a inite time (.51) can be ( τ ) converges to a periodic unction ( ) simpliied to 0 1 Ts 0( x ) = ( τ,, ( τ, )) dτ T x ψ x, (.5) 0 s whose value is inite as described in section.. Thus ψ (, X ) τ becomes the steady-state solution o y (t) or ixed X. For PWM converters (.48) and (.49) can be written as dx dt = A sx i x + A sy i y + B s i u, (.53) dy dt = A x i x + A y i y + B i u, (.54) where superscripts s and stand or slow and ast in A i and B i matrices, which are constant during interval i..3.. Practical procedure or the method Starting with the PWM converter equations in the orm o (.53) and (.54) the ollowing steps summarize the averaging procedure. 1. Assume slow variables x as ixed in the equations or ast variables y, (.54): dy dt = A y i y + x { A X + B u } i i. (.55) 5

40 . Compute steady-state solution y ss o ast variables in (.55); 3. Substitute y ss into (.53) to get dx dt = A sx i x + A sy i y ss + B s i u. (.57) 3. Compute the average o (.57), over one switching period, r 1 tk,i sx sy s 0( x ) = { i i ss i }dt T A x + A y + B u t, (.58) k,i 1 s i= 1 to obtain the average model dx = 0 ( X ). (.59) dt.4. Synthesis Method or Averaged Circuit Models o PWM Converters Development o autonomous averaged and small-signal circuit models according to [S4, V8] is presented in this section. Their intent is to reproduce state-space averaging results or single switch PWM converters. n [S4], an in-place circuit averaging is perormed and analytical support is given whereas in [V8] an equivalent 3-terminal circuit is sought or the so-called PWM switch n-place averaging When the moving average operation over one switching cycle given by 6

41 1 t y( t ) = y( σ ) dσ T t (.60) TS S is applied, in-place to each branch variable o PWM converters, in steady state operation, the transormed branch variables satisy the same node and mesh constraints as the original variables. Thereore the synthesis o an averaged circuit model can be oriented towards a circuit layout topologically equivalent to the original simple PWM converter. Since a requirement or linear reactive elements not to be altered by the moving average operator is that the latter and dierentiation with respect to time commute, i.e. d dt d 1 dt Ts t 1 T [ y( t )] = y( σ ) dσ = [ y() t y( t T )] t Ts s s = 1 T s t t Ts d d y σ d dt ( σ ) dσ = y( t ), (.61) which implies continuous dierentiability or the state variables, i.e. their irst time derivative to be continuous. Unortunately this is not the case or the PWM converters treated here as stated by (.1) and hence the moving average o the state variables do no satisy the converter s state equations in general. Application o the one cycle moving average operator in (.60) to the state-space representation o the PWM converter in (.1), and reproduced here or clarity, d dt x (t) < t t, (.6) = Ak,i x(t) + Bk,i u( t ) tk,i 1 k,i leads to the orm d dt x(t) = 1 T s t t Ts [ A x(s) + B u( s )][ H( s t ) H( s t )] ds, k,i k,i k,i 1 k,i (.63) 7

42 which is valid or all k,i since H(. ), the Heaviside step unction, in the last bracket selects the appropriate time intervals or matrices A k,i and B k.i. Direct computation o this moving average would require keeping track o intervals within each switching cycle, which is a terrible burden. nstead an approximated average per switching cycle described by d dt X(t) = 1 T t k tk Ts s [ A x(s) + B u( s )][ H( s t ) H( s t )]ds k,i k,i k,i 1 k,i (.64) is used, where X is the new averaged state and t k =t. n other words the moving average interval o width T s and the switching cycle are assumed to coincide. [S4] provides a theorem regarding the synthesis o an averaged circuit or a PWM converter with a single controlled and linear time invariant components. The converter must ulill the ollowing conditions: (a) be partitioned as shown in Fig..5, (b) (c) have unique solutions or voltage and currents o its branches, e.g. no capacitor-voltage source loop, etc., have a hybrid representation or the RESSTORS multiport in Fig..5 with controlling port variables taken as currents or those ports connected to current source or inductive ports and as voltage or those ports connected to voltage source or capacitive ports, with a single current-controlled switch port and a single voltage controlled switch port. Given all this it is possible to obtain an averaged circuit model by replacing the two-port switch network with a resistive two-port whose hybrid representation is H S d =, (.65) 1 d ( d ) H or d 1, where H is the hybrid immittance seen by the switch two-port when all current source and inductive branches are replaced by open circuits and all voltage source and capacitor branches are replaced by short circuits. 8

43 Since application o this theorem is restricted to single switch converters, a procedure introduced in [V8] or the PWM-switch and then complemented in [L11, X4, Y], which also leads, in a more direct way, to the synthesis o a valid circuit or the same hybrid representation is shown instead..4.. PWM-switch equivalent circuits This method was proposed in [V8] or dc and small-signal model. t starts by noting that simple PWM converters include one active switch (externally controlled device) and one passive switch (diode). The combination o these two switches, shown in Fig..6(a), is the so-called PWM switch. Because at most one switch is conducting at a time, some relationships or the instantaneous terminal variables o the PWM switch, depicted in Figs..6(b) remain invariant in simple PWM converters, i.e. ic( t ) ; 0 t d Ts i a( t ) = (.66) 0 ; d Ts t Ts and vap( t ) ; 0 t d Ts v cp( t ) =, (.67) 0 ; d Ts t Ts where i and v represent instantaneous port variables, subscripts a, p, c stand or active, passive and common respectively, and d. T s represents the interval within the switching cycle when the active switch is on. From here an average model or the PWM switch, valid in steady-state operation, i.e. ixed duty-ratio, is developed by computing, rom the waveorms in Fig..6(b), average current and average voltage at its terminals. That is, = d (.68) a c and V cp = d (V r (1 d )), (.69) ap c eq where, V and d represent average quantities and r eq is the equivalent resistor that causes the jump in v ap. That equivalent resistor is usually a combination o capacitor equivalent series resistor (esr) and/or load resistor. For instance in the boost and buck-boost converters r e is the parallel combination o output ilter capacitor s esr and load resistor. 9

44 An equivalent circuits or the average model o the PWM switch, i.e. (.68) and (.69), is shown in Fig..7. [V8] uses an ideal transormer instead o the controlled sources. Note that the circuit representation or the PWM switch is not unique but must have the same terminal variables relations. The small-signal model o the PWM switch can be obtained by linearizing equations (.68) and (.69). The inal result [V8] is i a = d i + d, (.69) c c v ap vap d = + ic req (1 d ) [Vap + c ( d 1) req ]. (.70) d d Computation o typical transer unctions such as control or input voltage to either state variables or output voltage can be carried out by placing the small-signal PWM model into the converter and then using node and mesh equations. DCM o operation is covered in [V8] or the same type o analysis. Similar works in [X4, Y] cover DCM and CCM operation respectively. nstead o transormer and equivalent resistor to replace the switch-diode pair the models exhibit a controlled current source and a controlled voltage source. The latter represents average switch current whereas the ormer represents average diode voltage. n [L11] a simpliied version o [Y], no capacitor esr included, is used to model simple PWM converters with a current eedback loop..5. Analysis o Strengths and Weaknesses o these Methods O all these methods or switching power converters generalized averaging (KBM) is the most systematic, can include any type o eedback loops but provides very little physical insight and becomes almost untraceable or high order systems. Even though state variables ripple can be approximated to an arbitrary degree it requires keeping track o phase relationships between PWM modulating signal perturbations in control and input signals. n other words time varying eects must be considered, which conlicts with the main purpose o averaging, i.e. obtaining an autonomous representation. Physical insight is incorporated into two-time scale averaging or switching power converters with the classiication o ast/slow state variables based on waveorms analysis. Moreover the procedure or this method o averaging is systematic and can handle PWM as well as several resonant converter types. Unortunately energy holding 30

45 i 0 REACTVES RESSTORS v 1 SWTCH SOURCES Fig..5. Partition o PWM converter structure. 31

46 c i a (t) i c (t ) c a current port s a T s 0 0 V ap i a (t ) i c (t ) d c v cp (t) v ap (t) ( ) d ap C r 1 V eq current port 1-d V cp v cp (t ) v ap (t ) 0 0 T s p d T s d T s a) Structure and terminal variables a) Terminal waveorms Fig..6. The PWM switch voltage port 3

47 a (1 d) d r e c i a ( t ) i c ( t ) d i c (t) d v ap ( t ) p Fig..7.PWM-switch equivalent average circuit. 33

48 elements, dealt with in more detail in Chapter 4, are not allowed within the ast state variables and steady-state conditions are used in some portions o the procedure. These steady-state conditions lead to unaccounted dynamic characteristics, g.e. input, control and ripple induced eects, which constrain model ranges, g.e. order, bandwidth. PWM switch models and their extensions to some types o resonant converters give very good physical insight and allow or straightorward dc and ac calculations through circuit analysis tools. However, constraints imposed on the switch-diode pair coniguration limit the set o converters that can be modeled. n-place circuit averaging preserves converter structure and hence provides strong physical insight. n addition a systematic and rigorous procedure leads to analytical hybrid representation or the switch-diode pair. Regrettably, this procedure can become very involved or high order systems and deals with CCM and DCM separately as it is also the case or all previous methods. Even though PWM switch modeling and its extensions deal with multiple switches in a systematic way there is no provision or ullbridge based converters or energy storage elements..6. A New Procedure or Averaged Circuit Models Strong eatures rom some o the methods discussed above are complemented with analog simulation and series expansion practices as well as heuristic guidelines to orm a new modeling procedure. A simpliied version o the so-called duo-mode average model [R5] that covers DCM and CCM or the buck converter with current eedback loop is developed to illustrate the new procedure and then simulation results rom switching and average models are presented Philosophy o the new average modeling procedure Representation o port characteristics, e.g. impedances, average variables, as well as transer characteristics, e.g. voltage conversion ratio, will be the major property sought or the average circuit model. The starting point or the procedure is the set o open-loop typical waveorms in transient regime and o switching structures through which the converter passes, Fig..8. nclusion o transient regime conditions overcomes limitations induced by steady-state conditions used in PWM-switch modeling and in two-time scale averaging methods. Then classiication o state variables into ast and slow types rom the two-time scale method is used together with circuit topologies and typical waveorms to select, at input and output ports, iltering networks (slow state variable components) whose structures do not get altered by switch transitions, i.e. linear time invariant (LT) networks, so that their contributions to open-loop input/output characteristics (impedances, dynamics) are preserved. 34

49 To keep consistency with this goal the equivalent driving and/or loading controlled sources or those LT iltering networks must be identiied and their moving average should be eiciently and accurately approximated (or this task one-cycle average has been heuristically selected). n other words we are trying to mimic the moving average properties stated in (.61), rom in-place averaging section, by applying the one-cycle average o those controlled sources to the LT networks in the previous paragraph. At this stage eedback loop eects, e.g. algebraic and dynamic constraints, can be incorporated or stability and transient analysis, and inally a simulator speciic implementation should be developed. n order to help with application o the procedure it gets described in a step-bystep ashion together with guidelines in the next section..6.. Steps o the new average modeling procedure and their guidelines Step 1: Classiy state variables according to slow/ast dynamics with respect to switching requency and select meaningul slow states or average circuit model. These states should have neither zero steady-state average nor a zero value during a signiicant amount o time within the switching cycle and their moving average main requency components should be much lower than the switching requency, Fig..9. Step : Select linear time invariant (LT) input and output parts, i.e. sub-networks made o sources and passive components whose structures do not get altered by switch and diode transitions, Fig..10. Step 3: dentiy dependent variable(s) drawn rom input network(s) and independent variable(s) delivered to output network(s), all rom the Step, to be represented as controlled sources. These variables should not create discontinuities in state variables regardless o initial conditions, i.e. no current sources in series with inductors or voltage sources in parallel with capacitors, Fig..11. Step 4: Derive expression or one-cycle average o controlled sources in Step 4 rom typical waveorms and circuit topologies. n most cases a ew low order terms o power series approximation or waveorm description will suice, Fig..1. Step 5: Derive algebraic constraints in transient regime, e.g. variable-state dependent switching instants, DCM-CCM boundary conditions; as a unction o input, control and ast dynamics variables. The latter should not be related to an energy holding component, described in detail in Chapter 4, since its state variable contributes with a dynamic constraint, i.e. an additional state, which usually requires a particular treatment. Here also low order terms in power series approximation o waveorms may suice, Fig..13. Step 6: ncorporate eedback-loop induced algebraic constraints and additional estates (e.g. control and state dependent switching instants, compensator own states). By starting 35

50 with an open loop system and later including eedback loops eects it is very likely that only this step will need modiications when changing control strategies, Fig..14. Step 7: Use common and reliable analog simulation practices to implement the average model in circuit simulators and to blend models or dierent operating modes (e.g. closing a loop around an operational ampliier to ind zeros or the inverse o a unction, manipulating equations to avoid undeined operations such a division by zero, detecting inadmissible variable values such as bipolar output rom a rectiier, on the ly state variables removal/addition etc.), Fig Application o the new procedure to the buck converter Figures.,.3 and.4 show the buck converter with current eedback loop, its circuit topologies and its typical waveorms respectively in CCM. Fig..16(a) exhibits an averaged circuit model or the same converter, which can be derived by applying the new procedure as detailed next Classiication o state variables in Step1, according to their dynamics speed, labels inductor current i L and capacitor voltage v C, shown in Figs..4 and.9, as slow type. n Step the voltage source gets easily identiied as linear time invariant input structure whereas the second order ilter becomes the output side counterpart, Fig..10. Step 3 identiies switch current and diode voltage as dependent variable drawn rom LT input part and independent variable delivered to LT output part in the previous step, Figs..8 and.11. n Step 4 the one-cycle average both or switch current i S and diode voltage v D, in Figs..8 and.1 are calculated as i = d (.71) S i L and v = d. (.7) D v in where d, i and L v i are duty-ratio command, average ilter inductor current and input voltage respectively. From Fig..8 peak and average inductor current, i pk and i L are related up to a irst order approximation by i pk [ i d + i ( 1 d )] 1 = il + up dwn, (.73) 36

51 where ( v v ) i C iup = m1 d Ts = d Ts, (.74) L and vc idwn = m ( 1 d ) Ts = (1 d ) Ts. (.75) L For later use d is deined as d i pk =. (.76) m T s Algebraic constraint derived in Step 5 corresponds to CCM-DCM boundary condition, Fig Typical operating waveorms and circuit topologies or the buck converter in DCM operation are shown in Fig..17. Development details or the average model in DCM shown in Fig..18 will be presented ater completing derivation in CCM. Step 6 derives the algebraic constraint induced by current eedback loop incorporation, Fig..14, which determines switching time in terms o current reerence and state variables, i.e. * i mr d TS = i (.76) pk Circuit simulator oriented implementation o average model in Step 7, includes eedback loop around an operational ampliier to ind the root (zero) o a unction, Fig..15(a), as well as selection o a root within an admissible interval (duty-cycle between zero and one) and equation manipulation to avoid zero divisor condition, Fig..15(b). Beore applying the new modeling procedure to DCM operation a ew observations about the average circuit models or CCM in Fig..16 are included. Even though Model is the only one derived so ar, it can be transormed into the others through well-known controlled-source manipulation rules orm circuit theory. As a result all three models exhibit the same input, output and transer characteristics, and obviously any one can be transormed into the other two. Note that in Figs..16(b) and (c) the controlled sources represent in place average voltage or current or the switch or the diode and are labeled as such. The papers mentioned in the PWM switch model section replace switch and diode by average controlled sources and they arrive to average circuit models and in Fig..16. From all o this it is clear that an input-output description o a switching power converter may have multiple average circuit representations and that sometimes several 37

52 or even all o them can be generated by a single procedure. However our goal is to have a modeling procedure that can handle as many types o PWM converters as possible, and some resonant converters as a byproduct, without trying to derive multiple average model structures or the same converter. Figure.17 shows circuit topologies and typical waveorms or the buck converter in DCM operation. The corresponding average model, presented in Fig..18, can be derived by ollowing the new procedure. Classiication o variables according to their dynamics speed, Step 1, labels capacitor voltage as the only slow variable since ilter inductor current stays at zero during a signiicant portion o the switching cycle. Thereore its one-cycle average solely depends on present switching cycle conditions, i.e. its own dynamic history does not directly matter. n Step only output capacitor is selected as the LT part in that side whereas the voltage source gets selected or the input counterpart since the ilter inductor is ruled out because o the diode, which by being connected in series with it during the second interval, prevents the current rom becoming negative, i.e. makes the inductor look nonlinear. From Step 3 switch current and ilter inductor current get respectively identiied as dependent variable drawn rom the input LT part and independent variable delivered to the LT output part. Calculation o one cycle average or the variables in Step3 is carried out in Step 4 with help rom Fig..17(b) where average switch current is clearly given by i S i pk = d, (.77) with i pk = m d T = m d T, (.78) 1 S S where d remains consistent with its deinition in.76. Similarly one-cycle average ilter inductor current is expressed as i = ( d d ), (.79) pk i L + which can be combined with.74,.75 and.78 to obtain 38

53 ( v v ) i C vi i = L d TS. (.80) L vc The latter is consistent with the claim that one-cycle average ilter inductor current is completely determined by present cycle conditions and hence classiies as a ast variable. The CCM-DCM boundary condition, illustrated in Fig..13, leads to the expression ipk il = (.81) or which to check during the simulation when both average models, i.e. CCM and DCM version, get combined below by ollowing the approach called duo-mode model presented in [R5] and shown in Fig..19(a), which uses an ideal transormer representation, to cover CCM and DCM operation. Fig..19(b) shows the controlled source equivalent version o the model. The transormer on the let with turns ratio 1:d represents CCM operation whereas the other transormer, with turns ratio ( d + d ): 1, makes adjustments or DCM operation. Notice that i the constraint d 1 d (.8) is enorced ater calculating d, according to (.76), the turns ratio or the right transormer reduces to 1:1 during CCM, which makes it irrelevant as ar as input-output transer characteristics concerns and the correct model is seen. However during DCM operation d must be adjusted to enorce (.80), i.e. average inductor current. The analog implementation diagram shown in Fig..1 satisies both CCM and DCM constraints. Application o simple controlled-source manipulation practices rom network theory transorms the average circuits in Fig..19 into those in Fig..0 while keeping the same input-output characteristics and all the relevant inormation avilable. The model in Fig..0(b) can be covered by the new procedure i the circuit simulation oriented implementation in Step 7 is expanded to search or versatile analog circuit representations that can change the number o state variables (ilter inductor current state removed during DCM) in real time during the simulation in a smooth and reliable ashion, i.e. no convergence prone or discontinuity inducing structures. Current eedback loop incorporation in Step 6 deals with (.76) again but i pk is now given by (.78) instead o (.73). This illustrates another situation with which the versatile analog circuit representations in the previous paragraph must cope. Regarding Step 7, Fig.. shows an analog circuit schematic to implement the calculation, in real time during the simulation, o d and d to allow or smooth transitions between CCM and DCM. 39

54 .6.4. Model veriication and comments Veriication o the average model was conducted through Saber simulations. Schematics and template listings or these simulations are included in Appendix A. Figure.3 shows duty ratios, inductor current and output voltage waveorms rom switch and average model. A zoom-in on these waveorms is shown in Fig..4. t is apparent that average model waveorms very closely track those moving averages rom the switch model or large transients, both in CCM and DCM operation even when the converter moves back and orth between those modes. t is important to point out that there were no convergence problems or the average model and that waveorm tracking was very good or simulation step size more than one order o magnitude larger than the step used with the switch model. This close tracking indicates that the average model can be used to predict startup transients and eedback loops eects and hence it can help in power stage and control design. n these simulations good amiliarity with the speciic circuit simulator and reliable simulation practices is a must. 40

55 On O On O ON-state VG S L V D C R i i* m r i L m 1 m i L ramp i S OFF-state S L v D V C R v i D C dt S T S a) Switch structures (circuit topologies) b) Operating waveorms Fig..8. Starting point or new average modeling procedure t 41

56 T S i L v C Slow Variables t T S t Fast Variables Fig..9. Step 1: Slow/ast variables separation t t 4

57 Power v i i i L T nput Part L T Output Part Load x Load z Converter L F v i CF RLoad Fig..10. dentiication o Linear Time nvariant nput/output parts. 43

58 v i i i Power L T nput Part i a v x v b i y Converter L T Output Part Load w Load z L F v i nternal Slow States i a v x C F R Load Fig..11. Step 3: dentiication o dependent variable drawn rom input and independent variable delivered to output LT parts 44

59 VG i L i S v D * On O On O i L i S i = d S i L v D v in t v = d D v in dt S T S a) Dependent and independent waveorms b) One-cycle average Fig..1. Step 4: Calculation o controlled source one-cycle average 45

60 V G i * i L On O m = = 1 d 1 T S m d T S i pk T S i pk m m 1 i L t k t k+1 d.t s d 1.T s t i ( + ) d 1 d = i = L pk i pk a) Typical waveorms b) Algebraic constraint derivation Fig..13. Step 5: Calculation o algebraic constraints 46

61 VG i* i L On O On O m r ramp * i m d T = r 1 S i pk m 1 m dt S T S i L [ m ( ) ] 1 d + m 1 d pk T i + = S L i a) Waveorms with eedback loop b) Loop-induced constraint derivation Fig..14. Step 6: ncorporation o eedback loop 47

62 zero X (X,Y) = 0 R Y _ C Z Zero divisor potential problem Known input vector = i *,i,v,v L in o d = [ ] m 1 m d 1 1-d 1 d m d 1 m 1 = ( d + d ) i 0 i 1 L = pk i * m d T i = r 1 s pk 0 Root interval constraint through limiter d 0 zero zero Out R R n _ + C C _ OP + OP + OP i pk = d 1 i + L d n Zero divisor potential problem Root interval constraint through limiter d 1 1 Out a) Root inder through loop around operational ampliier b) Robust treatment o equation and root selection Fig..15. Step 7: implementation o circuit simulator oriented average model 48

63 L V R Load i i S v D C i L a) Averaged circuit model i S L v S L i L V R Load i V C R Load i C v D i D i L b) Averaged circuit model c) Averaged circuit model Fig..16. Average circuit model or buck converter in CCM operation 49

64 i L L V G V R Load i C On O a) Switch on interval i * m r ramp m m 1 L i L i L V R Load i C i L i S b) Diode conducting interval L v D v C v in i L =0 V R Load i C dt S d T S T S t c) dling interval d) DCM operation waveorms Fig..17. Buck converter in DCM operation 50

65 L V i i R Load S i L C Fig..18..Average circuit model or buck converter in DCM. 51

66 L V i 1 d d+d R 1 Load C i i L a) Transormer based average circuit model i x i L L v d i x d v i v i x L ( + ) ( d + d ) d i d v x R Load C b) Controlled-source based average circuit model Fig..19. Average circuit models or buck converter in CCM and DCM operation 5

67 L d + d d V R Load i C i i L a) Transormer based average circuit model L F V i L i d d + d i d d + d v i i L C F R Load b) Controlled-source based average circuit model Fig..0. nput/output structure average circuit models or buck converter in CCM and DCM operation 53

68 Limiter Out d 1-d n Y = d d V V L in o Eqn (.73) Eqn (.75) d m Ts i pk = 0 Eqn (.79) i pk m zero R C _ OP +... Fig..1. Analog computation o d. 54

69 Limiter Out d 1-d n Eqn (.73) i pk Z = * i d L v i v o Eqn (.75) d m Ts i pk = 0... m zero R C _ OP + C i * m r d T s i pk = 0 zero R _ + OP d Out 1 n Limiter Fig... Analog computation o d and d with eedback loop. 55

70 Fig..3. Simulation results rom average (red-dashed) and switch (greensolid) mode. Top: duty ratios, middle: inductor current, bottom: output voltage. 56

71 Fig..4. Simulation results rom average (red-dashed) and switch (greensolid) mode. Top: duty ratios, middle: inductor current, bottom: output voltage. 57

72 3. MODELNG OF THE ZVS-FB-PWM DC-DC CONVERTER The new procedure or the derivation o autonomous average circuit models given in the previous chapter is complemented here and then applied to the ZVS-FB-PWM converter to get a new model. Previous averaged models were based on steady-state operation and neglected variables ripple eects. As a result their range o validity, i.e. requency, large signal excursions, was limited and could not make a smooth transition between CCM and DCM operation. Comparison o simulation results between new and previous model shows that most o those limitations have been overcome. Furthermore a small-signal model is derived through linearization o the new average model and within the circuit simulator; whereas previous small signal models were obtained through graphical approximations o perturbations evolution. 3.1 ZVS-FB-PWM Converter Operation The ZVS-FB PWM dc-dc converter and its typical switch structures (circuit topologies) in CCM operation are shown in Fig. 3.1(a) and (b) whereas its typical waveorms are depicted in Fig. 3.. t operates with zero-voltage switching in both legs and it is widely used in high power applications. ts complete analysis and design considerations as well as its small signal models can be ound in [S1] whereas some large and small-signal models are provided in [T4, V5] CCM operation Figure 3.1(b) and 3. describe CCM operation o the converter through equivalent circuit structures or each major switch coniguration interval, i.e. Charging, Transer and Circulating, whose characteristics are summarized below [S1, V5], and waveorms or bridge voltage, V ab, blocking capacitor voltage, V ab, primary current, p, bus current, bus, ilter inductor current,, rectiier s output voltage, V s, and output voltage, V 0. Blocking capacitor voltage is assumed negligible with respect to both input and relected output voltage as Fig. 3. suggests. Charging Stage. Starts at t 0 when input voltage V in is applied between nodes a and b, and ends at t 1 when primary current equals relected ilter inductor current. On the primary side, ater neglecting transormer s magnetizing current and second and higher order terms in Taylor s series expansion, input voltage determines the rate o change o current in the leakage inductor L Lk, i.e. m1 in Fig. 3. and given by V in m 1 =, (3.1) Llk 58

73 while rectiier diodes short circuit transormer s secondary winding and hence the output voltage V 0, whose changes over a switching cycle are assumed negligible, determines the rate o change o current in the ilter inductor L, i.e. m4 in Fig. 3. and given by V 0 m 4 =. (3.) L According to (3.1) the change in primary current during this stage is approximately given by V ( t t ) = ( m1) ( D ), (3.3) p p in 1 0 = 1 0 ch Ts L lk rom where duty ratio or this stage, D ch, is given by m1 p p 1 0 = Dch Ts. (3.4) Similarly rom (3.) the change in the ilter inductor current during this stage is approximately given by V ( t t ) = ( m4) ( D ). (3.7) = 1 0 ch T s L Current changes in (3.3) and (3.7) are related by the transormer s turns ratio N, i.e. p p ( ) 1 0 = N 1 0. (3.5) Transer Stage. Starts at t 1 ater primary current equals relected ilter inductor current with transormer in normal operation and hence instantaneous primary current and ilter inductor current are related by the transormer s turns ratio and ends at t when V ab becomes zero. Relection o input voltage and transormer s leakage inductance to the secondary side gives, or this stage, the equivalent circuit shown in Fig From here the rate o change o primary current, m in Fig. 3., is given by V L and rom Fig. 3. the duty ratio or this stage is lk N V0 + N L in = m, (3.6) D tr p p 1 0 = Don. (3.7) m1 T s 59

74 bus Vin + - S1 S S3 L + Cb Vs Llk - a + - Vcb b p N:1 + C R Vo L _ V in /N V in V in /N V in L lk /N L bus /N Vs V L lk /N L bus /N V s bus Charging V 0 Transer R L V 0 R L S4 V in /N V in bus /N bus L lk /N L V s Circulating V 0 R L a) Circuit schematic b) Switch structures in CCM Fig ZVS-FB PWM converter 60

75 S 1, S 4 S, S 4 S, S 3 V ab Charging Transer D on T s Circulating Charging V in D tr T s V Cb p m1 p 1 m p m3 p 3 bus p 0 0 m4 N m 1 N m3 3 V s V o t 0 t 1 t t 3 t o t + o T s t Fig. 3.. Typical ZVS-FB PWM converter waveorms in CCM. 61

76 Change in ilter inductor current is given by V / N V ( t t ) = ( N m) ( D T ) 1 in 0 = 1 tr s, (3.8) Llk / N + L where m is deined by the irst bracket and D tr t t T 1 =. s Circulating stage starts when bridge voltage V ab becomes zero, primary current and ilter inductor current are related by the transormer s turns ration, and the change in inductor current or this interval is expressed as = V ( t t ) = ( N m3) [ ( 1 D ) ], (3.9) on T s Llk / N + L where m3 is deined by the irst bracket, and the commanded duty-ratio, D on, is given by D = D + D. (3.10) on ch tr Equations (3.1) through (3.6) together with Fig. 3.3 can now be used to calculate the one-cycle average o ilter inductor current, i.e. ( ) ( ) ( 1 + ) ( 1 + ) D D + D + ( 1 D ) = on tr tr on. (3.11) The set (3.1) through (3.11) represents the algebraic constraint set needed to develop the average circuit model DCM operation Typical waveorms or DCM operation are shown in Fig Clearly there is no charging stage and hence commanded duty cycle determines duration o transer stage. Peak ilter inductor current is given by and by pk V / N V ( t t ) = ( N m) ( D T ) in 0 = 1 0 on s (3.1) Llk / N + L pk V 0 = ( t t1) = ( N m3) ( D Ts ). (3.13) Llk / N L + 6

77 One-cycle average inductor current is calculated rom (3.8) and (3.9) as ( D + D) pk on =, (3.14) which gives the same DCM-CCM boundary condition as in the buck converter, i.e. Equating (3.1) and (3.13) gives pk =. (3.15) D D m = (3.16) m3 and its substitution together with (3.1) into (3.14) gives the algebraic constraint on onecycle average inductor current, i.e. ( D ) on m on Ts m = 1 +. (3.17) m3 The same as in the buck converter, this constraint indicates that one-cycle average ilter inductor current is not an independent state. 3.. New Average Circuit Model or the ZVS-FB Converter Systematic application o the new procedure leads to the input-output structure average model o the ZVS-FB PWM dc-dc converter shown in Fig. 3.4(a) as detailed next Step 1: Fast/slow classiication o state variables From Figs. 3.1 and 3., ilter inductor current and output capacitor voltage qualiy as slow variables in CCM to be used as states in the average circuit model. However in DCM only the output capacitor remains as a slow state. Filter inductor current stays at zero during a signiicant amount o time within a switching cycle, which leads to having its one-cycle average ully determined by present switching cycle condition and hence being converted to a ast variable. Primary current is not considered a relevant average state variable, even though it corresponds to leakage inductor state variable, because its moving average is zero in steady state operation and exhibits large components at one hal the switching requency and higher harmonics during transient regime. n other words no new inormation would 63

78 be provided in steady state and time varying eects would have to be included in the model Step : LT input/output parts Output ilter and input voltage source get selected as LT networks according to circuit topologies in Fig. 3.1(b) Step 3: ndependent variable drawn rom LT input network and dependent variable delivered to LT output network Average bus current is the dependent variable drawn rom input voltage source whereas secondary rectiier s output voltage is the independent variable applied to the output ilter during CCM operation. On the other hand one cycle average inductor current becomes the sought independent variable ed to the output section during DCM operation the same as in the buck converter Step 4: Calculation o one-cycle average or the variables in the previous step CCM. According to Figs. 3.1(b), 3. and 3.4(c) rectiier voltage is equal to zero during charging stage; it becomes a unction o input source voltage and output capacitor voltage, during transer stage ater neglecting blocking capacitor voltage, i.e. Vin Llk L + V0 = N N, t1 t t, (3.18) Llk + L N Vs and only a unction o capacitor voltage during circulating stage given by V s Llk V0 = N, t t t1. (3.19) Llk + L N From (3.18), (319) and Fig. 3. the one-cycle average rectiier voltage given to controlled source V can be expressed as V L L L + V V V =. (3.0) in lk lk 0 0 Vs = N N Dtr + Don lk L N L lk + L + L N N ( 1 ) 64

79 S 1, S 4 S, S 4 S, S 3 V ab Transer D T on s Circulating dling Transer V in D T s V Cb p m1 pk p m bus N m1 pk N m V s V 0 t 0 t 1 t t 3 t o t + T o s t Fig Typical ZVS-FB PWM converter waveorms in DCM. 65

80 The average circuit model shown in Fig. 3.4(b) includes transormer s leakage inductance relected to the secondary side to highlight its dynamic eects, which are implicitly included in (3.0). The model becomes equivalent to that in Fig. 3.4(a) i V eq is computed to make V appear in between the two inductors, that is, to have the same average voltage delivered to the output ilter. Thereore V eq is given by V eq L V lk V 0 in = Dtr + N ( 1 Dch ). (3.1) N L Fig. 3.4 indicates that controlled current source 1 corresponds to one cycle average bus current. From Figs. 3.1(b) and 3., 1 can be computed as 1 p p p p ( + ) ( + ) = bus = Dch + Dtr. (3.) Calculation o D tr is again carried out on line in the simulator by closing the loop around operational ampliiers to ind the root located between 0 and D on. Equations (3.1) through (3.) can be combined to ind the expression with D tr as the only unknown or they can be arranged to solve or as many o the unknown quantities as desired. DCM. One-cycle average ilter inductor current is now given by (3.14) and the average circuit model is shown in Fig. 3.5(a). Since this situation its very similar to that ound in the buck converter model the value may be enorced by adjusting, in the average circuit model shown in Fig. 3.4, controlled source V, which in turn depends on D. Thereore ilter inductor current can be treated the same as in the buck converter model, i.e. a loop around an operation ampliier that enorces algebraic constraint (3.14). Bus current, according to (3.1) and Figs. 3. and 3.4 is given by Step 5: Calculation o algebraic constraints ( D ) pk Don m on Ts = =. (3.3) These constraints are already described in (3.1) through (3.3) both or CCM and DCM operation Step 7: mplementation o circuit oriented simulation Fig. 3.6 shows the same technique used in Chapter to compute, in real time during the simulation, D tr and D both in CCM and DCM or the average model. 66

81 3.3. Previous Average Models or the ZVS-FB Converter Models presented in [T4, V5] used the PWM switching model in [V8]. However [T4, V5] neglects some eects o transormer s leakage inductance upon rectiier s output voltage and upon ilter inductor current slopes. As a result this average model neither makes a smooth transition between CCM and DCM nor gives an accurate smallsignal model through linearization. [V5] does not provide a large signal average model but only a DC (steady-state) model and a small-signal model is developed by adding some controlled sources to the small-signal model, derived through the PWM switching model in [V8], or the Buck converter. t also neglects some eects o transormer s leakage inductance upon rectiier s output voltage and upon ilter inductor current slopes. None o these models ollows the correct introduction order or perturbation and steady-state constraints pointed out in [V3] and hence validity-range o derived smallsignal models gets compromised Simulation Results New and previous [T4] average models o the ZVS-FB PWM dc-dc converter get compared to its switching model through transient simulations. These simulations are carried out or several sets o parameter values similar to those used in [V5], which are listed in Table 1. Commanded duty-ratio D on or all simulation is shown on top graph o Fig Appendix B contains templates or the Saber simulator. State variables rom the new average model very closely ollow moving average o their respective counterparts in the switching model or all parameter sets, Figs. 3.7 through 3.0, whereas state variables rom previous model can only exhibit good tracking under special conditions, Figs. 3.14, 3.17 and 3.19, and can present aster or slower dynamics than that o the switching model depending o operating conditions, Figs. 3.9, 3.11, 3.14 and Furthermore the new average model maintains excellent tracking during transient regimes that go back and orth between CCM and DCM as Figs. 3.8, 3.9, 3.10, 3.13, 3.16, 3.17 and 3.18 show Transient simulations or parameter set 1 Simulations results or this set are shown in Fig. 3.8 through Even though the ratio o ilter inductance to transormer s leakage inductance is 60 and hence eects o the latter upon average behavior might be assumed negligible, as the previous model [T4] does, Figs. 3.8 through 3.10 indicate that those eects are still relevant. The new model maintains excellent state variables tracking or back and orth transitions between CCM and DCM operating modes whereas the previous model [T4] lacks it due to the loose approximation to model leakage inductor inluence as Fig. 3.7, 3.9 and 3.10 clearly show. The large in-rush current shown in Figs. 3.7 and 3.8, not allowed in practice by the 67

82 start-up sequence, was used here to solely illustrate average circuit model tracking properties. Commanded duty-ratio D on or all simulation is shown on top graph o Fig Figs. 3.7 and 3.8 show responses to zero initial conditions or all models. Table 1 Parameter value sets or transient response o ZVS-FB converter. Parameter Set 1 Set Set 3 Set 4 Set 5 Turns Ratio Leakage nduc. [ µ H ] Filter nduc. [ µ H ] Filter Cap. [ µ F] Load Resist. [ Ω ] L /(L lk /N ) Vin [ V ] Transient simulations or parameter set Simulation results or this set are shown in Fig through The ratio o ilter inductance to transormer s leakage inductance is 1 and hence eects o the latter upon average behavior are very strong, contrary to what the previous model assumes. Fig. 3.1 clearly shows three dierent slopes on inductor current waveorms, as considered by the new model derivation above, and very close tracking characteristics o the new model or transitions between CCM and DCM operating modes. n contrast to this the previous model completely lacks tracking. Furthermore the previous model exhibits slower dynamics than the correct one or certain operating conditions during the transient and aster dynamics than the correct one or other operating conditions. As a result the previous model cannot be used either or transient or stability analysis. 68

83 Transient simulations or parameter set 3 Figures 3.14 through 3.16 show simulation results or this special set o parameter values. The latter were selected so that the steady state part o the simulation rom the previous average model matched very well results rom the other two models but the ast transients show not so good an agreement. Since results rom previous average model or set showed aster and slower than correct dynamics it seemed possible to get a correct response or certain range o parameter values and operating conditions. Obviously this example warns about apparent good results when the ratio ilter inductance to relected leakage inductance is relatively low. The same excellent tracking is observed or the new model Transient simulations or parameter set 4 Figures 3.0 and 3.1 show simulation results or another special set o parameter values. The latter were selected very similar to set 1, i.e. large ratio o ilter inductance to relected leakage inductance, but to provide smooth transition between CCM and DCM or the previous average model and to coincide with the other two models. These results highlight the region o validity or the previous model. Once again the new model shows excellent tracking. Table. Parameter value set or small-signal model and transient response o Buck, ZVS-FB and ZVZCS-FB converters. Parameter Buck ZVS ZVZCS Turns Ratio NA 6 6 Leakage nduct. [ µ H ] NA 1 1 Blocking Cap. [ µ F] NA 0 1 Filter nduc. [ µ H ] Filter Cap. [ µ F] Load Resist. Ω Saturable Reactor [ µ V sec] NA NA 60 Vin [ V ]

84 Table 3. Parameter value set or small-signal model and transient response o Buck, ZVS-FB and ZVZCS-FB converters. Parameter Buck ZVS ZVZCS Turns Ratio NA 1 1 Leakage nduct. [ µ H ] NA 1 1 Blocking Cap. [ µ F] NA 0 1 Filter nduc. [ µ H ] Filter Cap. [ µ F] Load Resist. Ω... Saturable Reactor [ µ V sec] NA NA 60 Vin [ V ] Transient simulations or parameter set 5 Figures 3. and 3.3 show simulation results or another special set o parameter values. Now the latter were selected very similar to set, i.e. low ratio o ilter inductance to leakage inductance. However the results look quite dierent rom those or set since good tracking is seem rom the previous average model. Here the new average model also exhibited excellent tracking Transient and small-signal simulation results. Results rom transient and linearization, within the same circuit simulator, or the average model with two dierent resistive load values are shown in Figs. 3.1 through 3.4 or Buck, ZVS and ZVZCS converters. The latter, thoroughly analyzed in chapter 4, is included here to highlight the contrast between the two sot-switched converters with respect to the damping added to the output ilter. The transer unctions shown in Figs. 3. and 3.4, are D on to ilter inductor current and D on to capacitor voltage. n the buck 70

85 converter these transer unctions have the same shape, i.e. pole requency and damping, as those rom output low pass ilter except or a dierent gain actor. Both ZVS-FB and ZVZCS-FB converters alter output ilter damping coeicient and pole requency. These changes depend on parameters values and/or operating conditions or both ZVS-FB and ZVZCS-FB converters. With parameter value Set in Table both sot-switched converters change the damping actor by a airly large amount albeit in opposite directions. For the other parameter value set the ZVZCS-FB converter exerts a very small reduction in damping whereas the ZVS-FB converter introduces a large increment. 71

86 Vin + 1 V V V L - o RL bus 1 a) nput-output structure model V s V L lk /N L t o t t o + T s t + Vin + V V 1 V eq - o RL = () t V = ( t ) 1 bus V s b) Mixed input-output-internal structure model c) Waveorms or controlled-source average calculation Fig.3.4. ZVS converter equivalent average models and waveorms in CCM. t 7

87 bus 1 Vin + 1 V + - o RL V s v o t o t t + s o T s = 1 () t = () t bus a) nput-output structure model c) Waveorms or controlled-source average calculation Fig.3.5. ZVS converter equivalent average model and waveorms in DCM. t 73

88 Limiter D Out 1 D tr n Eqn (3.4) m Z = D V On in V o Eqn (3.16) pk D m Ts i = 0... m 3 zero R C _ OP + C Don Dch Dtr = 0 zero R _ OP + D tr Out D on n Limiter Fig Analog schematic or computation o D tr and D. 74

89 Proposed Model Previous Model Previous Model Switching and Proposed Model (Overlapped) L N L lk = 60 Fig Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average(black) models or parameter set 1 with zero initial state or all models. 75

90 Previous Model Proposed Model Proposed Model Previous Model Switching Model L N L lk = 60 Fig Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 1 with zero initial state or all models. 76

91 Proposed Model Previous Model Previous Model Switching and Proposed Model (Overlapped) L N L lk = 60 Fig Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 1 with zero initial state or all models. 77

92 Previous Model Proposed Model Previous Model Switching and Proposed Model (Overlapped) L N L lk = 60 Fig Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 1 with zero initial state or all models. 78

93 Previous Model Proposed Model Previous Model Switching and Proposed Model (Overlapped) L N L lk = 1 Fig Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set with zero initial state or all models. 79

94 Previous Model Proposed Model Switching Model Previous Model Proposed Model Switching Model L N L lk = 1 Fig Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set with zero initial state or all models. 80

95 Previous Model Proposed Model Previous Model L N L lk = 1 Switching and Proposed Model (Overlapped) Fig Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set with zero initial state or all models. 81

96 Proposed Model Previous Model Switching and Proposed Model (Overlapped) Previous Model L N L lk =.4 Fig Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 3 with zero initial state or all models. 8

97 Proposed Model Switching Model Previous Model Proposed Model L N L lk =.4 Previous Model Previous Model Fig Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 3 with zero initial state or all models. 83

98 Previous Model Proposed Model L N L lk =.4 Proposed Model Switching and Proposed Model (Overlapped) Fig Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 3 with zero initial state or all models. 84

99 Previous and Proposed Model (Overlapped) Previous, Proposed and Switching Model (Overlapped) L N L lk = 60 Fig Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 4 with zero initial state or all models. 85

100 Previous and Proposed Model (Overlapped) Previous, Proposed and Switching Model (Overlapped) L N L lk = 60 Fig Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 4 with zero initial state or all models. 86

101 Commanded Duty Cyacle) Proposed Model D tr Proposed Model D Proposed Model Previous Model Switching and Proposed Model (Overlapped) Previous Model L N L lk = 3.3 Fig Duty ratios (top), ilter inductor current (middle) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 5 with zero initial state or all models. 87

102 Commanded Duty Cyacle) Proposed Model D tr Previous Model Proposed Model Switching and Proposed Model (Overlapped) L N L lk = 3.3 Previous Model Fig Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), new average (pink) and previous average (black) models or parameter set 5 with zero initial state or all models. 88

103 ZVS-FB Buck ZVZCS-FB ZVZCS-FB Buck ZVS-FB Fig Capacitor voltage (top) and ilter inductor current (bottom) transient response rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set. 89

104 ZVZCS-FB Buck ZVS-FB Buck ZVS-FB ZVZCS-FB ZVZCS-FB Buck ZVS-FB Buck ZVS-FB ZVZCS-FB Fig. 3.. Capacitor voltage (top) and ilter inductor current (bottom) transer unctions rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set. 90

105 Buck ZVZCS-FB ZVS-FB Buck ZVZCS-FB ZVS-FB Fig Capacitor voltage (top) and ilter inductor current (bottom) transient response rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set. 91

106 ZVZCS-FB Buck ZVS-FB Buck ZVS-FB ZVZCS-FB ZVZCS-FB Buck ZVS-FB Buck ZVS-FB ZVZCS-FB Fig Capacitor voltage (top) and ilter inductor current (bottom) transer unctions rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set. 9

107 4. MODELNG OF THE SATURABLE NDUCTOR BASED ZVZCS-FB-PWM DC-DC CONVERTER The new procedure or the derivation o autonomous average circuit models given in Chapter is again complemented here and then applied to the ZVZCS-FB-PWM converter to get its circuit average model, which is a new result. Comparison o simulation results between average and switching model shows that most o the average dynamics is preserved. Furthermore a small-signal model is derived through linearization o the new average model within the circuit simulator and compared to those or buck and ZVS models. 4.1 ZVZCS-FB-PWM Converter Operation The ZVZCS-FB topology introduced in [C11], Fig. 4.1(a), and whose switch structures and typical waveorms or CCM operation are shown in Fig. 4.1(b) and 4., respectively, operates with zero-voltage switching in the leading leg and zero-current switching in the lagging leg or very wide load and line ranges. Although initially intended to have its lagging leg built with GBTs, the latter s switching speed limitations prevent their application at very high requencies, where MOSFETs become the only choice. However, by having conduction losses in the primary side strongly reduced through almost complete elimination o reewheeling stage in that side, the ZVZCS topology can still provide high eiciency or wide line range even with MOSFETs. Appendix C provides detailed design procedure or the converter as well as its waveorms and their exact describing equations or CCM operation. n this chapter only brie descriptions o waveorms relevant to the development o the averaged circuit model and their simpliied expressions are presented CCM operation Fig. 4.1(b) shows major topological stages or CCM operation o the ZVZCS converter, i.e. Blocking, Charging, Transer, Resetting and O, whose characteristics are summarized below [C11]. Fig. 4. shows typical waveorms or bridge voltage, V ab, primary current, p, bus current, bus, blocking capacitor voltage, V cb, ilter inductor current,, rectiier s output voltage, V s and output voltage, V 0. Assume the switching cycle starts with the blocking stage at t o, when bridge voltage V ab becomes positive and saturable reactor blocks any primary current, and ends at t 1 when the reactor gets saturated. The sum o input voltage and blocking capacitor voltage determines the rate o change o lux in the saturable reactor. The change o lux during this stage amounts to 93

108 Vin + - S1 S V + in cb NV + in NV V VSA Llk L /N L bus /N V s L Blocking V0 V 0 V 0 R RL L L Ls S3 L Cb Vs Llk a b Vcb p N: V Vo o V + in cb NV + in NV V + in cb NV + in NV V + in cb NV + in NV Llk L /N L /N Llk L /N L bus /N /N L bus /N V s V s Llk L /N L bus /N V s L L Charging V V0 0 RL L Transer V0 V 0 V RL L Resetting V V0 0 R R L L 0 0 R RL L L S4 V + in cb NV NV + in NV V VSA Llk L /N L bus /N V s L V V0 0 O 0 R RL L L a) Circuit schematic b) Switch structures in CCM Fig.4.1. ZVZCS converter 94

109 Vin + Vcpk Vin + Vcpk ( ) ( ) φ = = blk t1 t0 Dblk Ts, (4.1) N sr N sr where D blk, N sr and V cpk are blocking stage duty-ratio, saturable reactor number o turns and peak blocking capacitor voltage, respectively. On the secondary side output voltage determines rate o change in ilter inductor current, m4 in Fig. 4., as V 0 m 4 =. (4.) L During charging stage, (t 1,t ), the same rate o change applies to ilter inductor current whereas the change in primary current, ater neglecting transormer s magnetizing current and second order terms in Taylor s series expansion, is approximately given by V = + V ( t t ) = ( m1) ( D ), (4.) p in cpk 1 ch Ts L Lk where slope m1, shown in Fig. 4.3, is deined by the irst bracket, D ch corresponds to charging stage duty ratio and the remaining quantities are deined in Fig. 4.. At time instant t primary current and ilter inductor current are related by transormer s turns ratio, i.e. p = N, (4.3) and they remain so through transer stage, which ends at t 3 with commanded duty-cycle D on. D on s ( t3 t0 ) = ( Dblk + Dch + Dtr ) TS T =. (4.4) Relection o input voltage and transormer leakage inductance to the secondary side leads to the equivalent circuit or this stage, Fig. 4.1(b). Change in the ilter inductor current, ater neglecting blocking capacitor eects, is approximately given by V V ( t t ) = ( N m) ( D ), (4.5) N in O 3 = N 3 tr Ts L lk + L where slope N m is deined by the irst bracket and the other terms by Fig. 4.. Blocking capacitor voltage, V cb, is neglected here to simpliy the derivation and because its contribution is very small as later simulation results conirm. 95

110 S 1, S 4 S, S 4 S, S 3 Blocking Charging Transer Resetting O V ab D D on T s on T s V in V cb Vcpk p m1 p m p 3 m3 bus N m 3 m4 m4 4 V s V o t 0 t 1 t t 3 t 4 t 5 t t o t + o T s Figure 4.. ZVZCS-FB PWM primary and ilter inductor current waveorms in CCM. 96

111 Resetting stage starts at t 3 when bridge voltage V ab becomes zero and it ends when primary current does the same at t 4. Duration o this stage is given by p 1 3 Llk t = = 4 t3 Dres TS arcsin. (4.6) L lk Cblk Vcpk Cblk O stage begins at t 4 when saturable reactor blocks any primary current by taking V cpk as its lux rate o change and it ends at (t o +T s ) with hal o primary switching cycle when V ab becomes negative as shown in Fig. 4.. During this stage the change in lux across the saturable reactor is given by V = ( 1 D D ) T cpk on res s φo, (4.7) Nsr which together with saturable reactor volt-second blocking capability determines blocking stage duration, i.e. φ Blk φsat φo =, (4.8) where φblk is given by (4.1) and φsat is the volt-second blocking capability o the saturable reactor. Expressions or peak blocking capacitor voltage, V cpk, ilter inductor current average and ripple values, L and are calculated next to complete the set o equations. An approximation to V cpk value is obtained by looking at converter s steadystate operation and by taking into consideration the relevance o each stage s duration upon change in the capacitor voltage. These voltage changes during transer and resetting stages are respectively approximated by and V = D T L tr s c tr (4.9) N Cb V = ( ) D T 3 res s c res. (4.10) N Cb From Figs. 4. and 4.5, ater neglecting voltage change during charging stage, V is given by cpk 97

112 S 1, S 4 S, S 4 S, S 3 Blocking Transer Resetting O dling V ab D on T s D T s D on T s V in V cb Vcpk p m pk p m3 bus N m pk m4 V s V o t 0 t 1 t t 3 t 4 t 5 t o t + o T s t Figure 4.3. ZVZCS-FB PWM primary and ilter inductor current waveorms in DCM. 98

113 V cpk V = c tr + V c res. (4.11) On the other hand is calculated as tr ( ) + ( 1 D ) ( ) = D, (4.1) 3 tr 4 3 where V ( 1 Dtr ) Ts = m4 ( 1 Dtr ) s. (4.13) O 4 3 = T L DCM operation Typical waveorms or DCM operation are shown in Fig Clearly there is no charging stage and hence commanded duty cycle equals the sum o blocking and transer stages, i.e. D = D + D. (4.14) on blk tr Peak ilter inductor current is given by pk V / N V ( t t ) = ( N m) ( D T ) in 0 = 1 tr s (4.15) Llk / N + L and by pk V 0 = ( t3 t ) = ( m4) ( D Ts ). (4.16) Llk / N L + One cycle average inductor current is calculated rom (4.15) and (4.16) as L ( D + D) pk tr = =, (4.17) which gives the same DCM-CCM boundary condition as in the buck converter, i.e. pk =. (4.18) 99

114 Equating (4.15) and (4.16) gives Dtr N m D = (4.19) m4 and its substitution into (4.17) gives the algebraic constraint on one-cycle average inductor current, i.e. ( D ) N m tr Ts N m = 1+. (4.0) m4 As in the Buck converter, this constraint indicates that one-cycle average ilter inductor current is not an independent average state. Equation (4.1) still applies during blocking stage and (4.7) now represents the change in lux across the saturable reactor during the sum o intervals or o and idling stages. On the other hand expressions or capacitor voltage, i.e. (4.9), (4.10) become D T pk tr s Vc tr =, (4.1) N Cb and pk Dres Ts Vc res =, (4.) N C cb whereas (4.11) remains the same. 4.. New Average Circuit Model or the ZVZCS-FB Converter Systematic application o the new procedure leads to the input-output structure average model o the ZVZCS-FB PWM dc-dc converter shown in Fig. 4.4(a) as detailed next Step 1: Fast/slow classiication o state variables Figure 4. indicates that ilter inductor current and output capacitor voltage qualiy as slow variables in CCM to be used as states in the average circuit model. However in DCM only the output capacitor remains as a slow state. Similarly to the situation in Chapter 3 ilter inductor current stays at zero during a signiicant amount o time within a switching cycle, which leads to having its one-cycle average ully determined by present switching cycle condition and hence being converted to a ast variable. 100

115 Vin + L 1 V - o RL V L V Vin ab bus 1 a) nput output structure L lk /N + L Vin V V - o RL 1 V eq L V s t o t t 1 bus V t o + T s t + = () t V = () t V s b) Mixed input-output-internal structure c) Typical waveorms Fig.4.4. ZVZCS converter equivalent average models and waveorms in CCM. 101

116 Again primary current is discarded as a relevant average state variable, even though it corresponds to leakage inductor state variable, because its moving average is zero in steady state operation and exhibits large components at one hal the switching requency and higher harmonics during transient regime. n other words no new inormation would be provided in steady state and time varying eects would have to be included in the model. Blocking capacitor voltage gets classiied as a ast variable and its waveorm in Fig. 4. indicates that it is an energy holding element. ts treatment is presented later in this chapter Step : LT input/output parts Output ilter and input voltage source get selected as LT networks according to circuit topologies in Fig. 4.1(b) Step 3: ndependent variable drawn rom LT input network and Dependent variable delivered to LT output network From Fig. 4.1(b) it looks apparent that average bus current is the Dependent variable drawn rom input voltage source whereas secondary rectiier s output voltage is the ndependent variable applied to the output ilter during CCM operation. On the other hand rom Fig. 4.3 it is clear that one cycle-average inductor current becomes the sought ndependent variable ed to the output section during DCM operation the same as in the ZVS-FB converter Step 4: Calculation o one-cycle average or the variables in the previous step CCM. According to Figs. 4.1(b), 4. and 4.4(c) rectiier s voltage is a unction o input, blocking capacitor and output voltages during transer stage, i.e. V s Vin + Vcb Llk L + V0 = N N, (4.3) Llk + L N whereas the rest o the switching cycle it becomes zero. From (4.3) and Fig. 4. the one cycle average rectiier voltage can be expressed as ( V + V ) in cb Llk L + V0 Vs = N N Dtr (4.4) Llk + L N 10

117 V cpk V cb 0 m cb A A1 A3 -V cpk Dtr T s m cb L N C b V cb 1 = A -- A D tr T s Figure 4.5. Calculation o average blocking capacitor voltage. 103

118 where V cb is the average o blocking capacitor voltage during transer stage. According to Fig. 4.5 V cb is directly proportional to the dierence between areas A and A1, i.e. V cb tr s ( A + A3) ( A1 + A3) A A1 = = (4.5.a) D T D T tr s V cb ( V D T ) D T L tr cpk tr s N Cb L Dtr Ts = = Vcpk, (4.5.b) Dtr Ts N Cb where the slope o blocking capacitor voltage during transer stage is approximated by m cb N C L. (4.6) b The average circuit model shown in Fig. 4.4(b) includes transormer s leakage inductance relected to the secondary side to highlight its dynamic eects, implicitly included in (4.5). As in the ZVS-FB converter case V eq can be computed to make V appear in between the two inductors, that is, to have the same average voltage delivered to output ilter. Thereore V eq is given by V eq V + V V L ( 1 D ) in cb 0 lk = Dtr tr. (4.7) N N L Fig. 4.5 indicates that controlled current source 1 corresponds to one cycle average bus current. From Figs. 4., and 4.4(c) 1 can be computed as 1 3 ( + ) P P P = bus = Dch + Dtr. (4.8) DCM. One-cycle average ilter inductor current is now given by (4.17). Since this situation is the same as that ound both in the buck and ZVS-FB converter models the value must be enorced by adjusting, in the average circuit model, controlled source V, which in turn depends on D. Thereore ilter inductor current can be treated the same as in the previous two converter models, i.e. a loop around an operation ampliier that enorces algebraic constraint (4.17). Calculation o D tr is again carried out on line in the simulator by closing the loop around operational ampliiers to ind the root located between 0 and D on. Equations (4.1) 104

119 through (4.9) can be combined to ind an expression with D tr as the only unknown or they can be arranged to solve or as many o unknown quantities as desired. Bus current, according to (4.15) and Fig. 4.3 is given by ( D ) pk F DTr m Tr Ts 1 = =. (4.9) N Step 5: Calculation o algebraic constraints These constraints are already described in (4.1) through (4.) both or CCM and DCM operation Step 7: mplementation o circuit oriented simulation Fig. 4.6 shows the same technique used in the previous two chapters to compute, in real time during the simulation, D tr and D both in CCM and DCM or the average model dentiication and modeling o energy holding elements in ast dynamic subsystems An energy holding element is a reactive component that does not appear as a relevant state in the average model and its state variable (voltage or capacitors, current or inductors): a) gets classiied as ast type. b) has zero moving average in steady state operation and exhibits large components at one hal the switching requency and higher harmonics during transient regime. c) exhibits relatively large peak-to-peak excursions. d) exhibits nonzero and relatively large constant value during a signiicant time interval within a switching cycle. e) exerts a signiicant inluence upon switching instants and/or Dependent/ndependent controlled sources one-cycle average value. Since this state variable is the integral o a piece-wise continuous unction it is continuous and rom (a) and (b) its temporary nonzero constant value depends on the history o that integrand, in general a unction o some state variables. Because o (d) this nonzero constant value is a critical parameter in the converter constraint equations and its dynamics must be appropriately modeled. Sample data models can very easily and accurately describe these eects whereas high order average continuous models need be used or the same accuracy. 105

120 Limiter D Out 1-D Tr n Eqn (4.) m 1 Z = D V V On in C Eqn (4.5) D m Ts ilpk = 0... m zero R C _ OP + C D On D Blk D Ch D Tr = 0 zero R _ OP + D Tr Out 1 n Limiter Figure 4.6. Analog computation o D tr and D. 106

121 L R Ts R = C C _ OP + L slow D Out 1-D Tr Limiter n Z = D V V On L in C L slow D tr T /N C ( 3 ) Dres Ts / N Cb D m Ts ilpk = 0 L slow + s L / b Vc tr Vc Res zero 3 R C _ OP + C D On D Blk D Ch D Tr zero R _ OP + D Tr Out 1 n Limiter Figure 4.7. Analog implementation o dynamic relationship between ilter inductor current an blocking-capacitor peak voltage. 107

122 Here a heuristic approach is ollowed to obtain a simple and eective representation o this energy holding element eects. Circuit simulations veriy useulness o this representation. n our ZVZCS-FB converter blocking capacitor reaches V cpk at the end o resetting stage and holds it constant until the end o blocking stage. Duration o the latter is inversely related to V cpk and hence to the long history o L whereas that o charging stage is directly related to L in the present switching cycle. As a consequence, an intricate relation among circuit parameters determines whether positive or negative damping is added to the output ilter as summarized next and explained in more detail in Appendix C or steady-state operation. The change in damping is directly related to the loss o duty-cycle, D D = D + D, (4.30) on tr blk ch and hence inversely related to the change in transer stage duty ratio. Since duration o the charging stage, i.e. D ch, is proportional to L the change in duration o blocking stage with respect to L has to overcome that in D ch or damping o the output ilter to get reduced (intrinsic positive eedback). A low C blk value in the ZVZCS converter, as compared to that in the ZVS converter, leads to a large change in V cpk with L. This in turn makes the product Vcpk Do Ts bigger, which produces a reduction in blocking stage duration, since saturable-reactor volt-second blocking capability is constant. The size o that reduction will strongly depend on blocking capacitor value and saturable reactor volt-second blocking capability. Furthermore, it is possible to have an increase in dutycycle loss or some component values, especially when they resemble those used in the ZVS converter. Moreover, the amount o damping added to the output ilter in the average model is strongly dependent on the type o relationship representation, i.e. algebraic o dynamic, between V cpk and L as transient simulation results in Figs. 4.8 through 4.10 show. These results, or parameter value Set 1 in Table 4, correspond to a switching model, a simpliied average model and the proposed average model. The simpliied average model uses a standard algebraic equation whereas the proposed average model approximates the relationship between V cpk and L as dynamic through a single time constant equal to a switching semi-cycle, T s as shown in Fig. 4.7, i.e. L is modiied by a irst order low pass ilter, whose output is labeled L-slow in Fig. 4.7, beore been used in the computation o V cpk according to (4.9) through (4.11). Clearly the simulation results in Fig. 4.8 through 4.10 indicate that the proposed average model closely tracks moving average o switching model state variables whereas the simpliied model presents poor tracking due to its aster dynamics, i.e. equivalent pole requency and damping actor higher than actual ones. Only useulness o the average model with the dynamic constraint will be thoroughly veriied through transient simulations or dierent parameter set values. 108

123 Standard Approach Proposed Model Figure 4.8. Filter inductor current (top) and capacitor voltage (bottom) rom switching (green), irst average (blue) and second average (pink) models or parameter set 1 with zero initial state or all models. 109

124 Standard Approach Proposed Model Standard Approach Proposed and Switching Model Standard Approach Proposed Model Standard Approach Proposed and Switching Model Figure 4.9. Zoom in o ilter inductor current and capacitor voltage rom switching (green), irst average (blue) and second average (pink) models or parameter set 1 with zero initial state or all models. 110

125 Standard Approach Proposed Model Figure Zoom in o ilter inductor current and capacitor voltage rom switching (green), irst average (blue) and second average (pink) models or parameter set 1 with zero initial state or all models. 111

126 4.3. Simulation Results State variables rom the average model with the dynamic constraint very closely ollow moving average o their respective counterparts in the switching model or dierent parameter value sets (Table 4) as Figs through 4.5 show. Table 4. Parameter set values or transient simulations. Parameter Set 1 Set Set 3 Set 4 Set 5 Set 6 Turns Ratio Leakage nductance Blocking Capacitor Filter nductance Filter Capacitor Load Resistance Saturable Reactor uh uh uh uh 1uH 1uH 1uF 0.5uF 0.5uF 0.5u 1uF uf uh 8uH 8uH 3uH uh uh 00uF 50uF 50uF 33uF 00uF 50uF 1.1Ω 1.1Ω 3Ω 1.8Ω 0.3Ω 1.1Ω 60µ V-s 60µ V-s 60µ V-s 60µ V-s 60µ V-s 60µ V-s Transient simulations or parameter set 1 Simulations results or set 1 are shown in Figs through This set o parameters was calculated in a speciic application design [0]. The load here was selected to obtain a very lightly damped response with large oscillation amplitude while still maintaining CCM operation since these conditions ully test the CCM model. State variables o the proposed average model almost perectly match the dynamics, i.e. pole requency and damping actor, o switching-model state-variable moving average or a time interval over twenty times larger than the oscillation period, which is around 150µ s. The oscillation amplitude o the average ilter inductor current over the same interval changes rom 15A to 0.mA, i.e. attenuation o 97dB. t is important to point out that simulation time or the average model is still less than one tenth o that required by the switching model or this type o agreement. The dierence in pole oscillation requency between average model and switching model is around 1% according to the phase dierence seen at the end o the simulation interval in Fig. 4.14, i.e. phase shit less than one quarter o a cycle ater 0 cycles. 11

127 Average Model Average Model Average and Switching Model Figure Whole transient and zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 1 with zero initial state or both models. 113

128 Average Model Average and Switching Model Average Model Average and Switching Model Figure 4.1. Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 1 with zero initial state or both models. 114

129 Average Model Average and Switching Model Average Model Average and Switching Model Figure Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 1 with zero initial state or both models. 115

130 Switching Model Crest Envelope Average Model Switching Model Valley Envelope Switching Model Crest Envelope Average Model Switching Model Valley Envelope Figure Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 1 with zero initial state or both models. 116

131 Moving average o ilter inductor current was not calculated because o the excellent agreement in output voltage. n other words, the only way or the capacitor voltage in the average model to almost perectly ollow the moving average o the capacitor voltage in the switching model is by receiving the same average ilter inductor current since the resistive loads are equal Transient simulations or parameter set Simulations results or set are shown in Figs and All the parameter values are dierent rom those in set 1 but the load, which remained at 1.1 ohms. Moreover these parameters were selected to produce a less lightly damped response than the previous one with the same pole requency. Consequently deep CCM operation is seen. Again state variables o the proposed average model very closely match the dynamics, i.e. pole requency and damping actor, and steady state o switching-model state-variable moving average over the transient interval and the subsequent time respectively. Simulation time or the average model is again less than one tenth o that required by the switching model or this type o agreement. Dierence in output-voltage steady-state values between models is less than 1% Transient simulations or parameter set 3 Simulations results or set 3 are shown in Figs through All the parameter values are the same as those in set but the load, which changed to 3 ohms. Naturally a more lightly damped response than the previous one is obtained but deep CCM operation is still seen. Once again state variables o the proposed average model very closely match the dynamics, i.e. pole requency and damping actor, and steady state o switching-model state-variable moving average or a time interval over twenty times larger than the oscillation period, which is around 150µ s. t is important to point out that simulation time or the average model is still less than one tenth o that required by the switching model or this type o agreement. The dierence in pole oscillation requency between average model and switching model is around 1% according to the phase dierence seen at the end o the simulation interval in Fig. 4.19, i.e. phase shit less than one quarter o a cycle ater 0 cycles Transient simulations or parameter set 4 Simulations results or set 4 are shown in Figs. 4.0 and 4.1. Output ilter component values and load resistor value are reduced with respect to those in set 3 so that the response is almost critically damped. Similarly to the previous cases average dynamics is very closely matched and simulation time or the average model is still less than one tenth o that required by the switching model or this type o agreement. Output voltage steady state error is again less than 1%. 117

132 Average Model Average and Switching Model Figure Whole transient ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set with zero initial state or both models. 118

133 Average Model Average and Switching Model Average Model Switching Model Switching Model Average Model Figure Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set with zero initial state or both models. 119

134 Average Model Average and Switching Model Figure Whole transient o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 3 with zero initial state or both models. 10

135 Average Model Average and Switching Model Average Model Switching Model Average Model Figure Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 3 with zero initial state or both models. 11

136 Average Model Switching Model Average Model Average Model Average Model Figure Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 3 with zero initial state or both models. 1

137 Average Model Average and Switching Model Average Model Average and Switching Model Figure 4.0. Whole transient and zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 4 with zero initial state or both models. 13

138 Average Model Switching Model Average Model Average Model Switching Model Switching Model Average Model Figure 4.1. Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 4 with zero initial state or both models. 14

139 Transient simulations or parameter set 5 Simulations results or set 5 are shown in Figs. 4. and 4.3. All the parameter values are the same as in set 1 except or load resistor which gets reduced to 0.3 ohms. The same as or set 1 average dynamics is almost perectly matched and simulation time or the average model is still less than one tenth o that required by the switching model or this type o agreement Transient simulations or parameter set 6 Simulations results or set 5 are shown in Figs. 4.4 and 4.5. Except or leakage and ilter inductance values all the parameter values are changed. The same as or set 6 average dynamics is almost perectly matched and simulation time or the average model is still less than one tenth o that required by the switching model or this type o agreement Dynamics Comparison among Buck, ZVS-FB and ZVZCS-FB Converters Transient response and small-signal transer unction rom new average model and its linearization Results rom linearization and their respective transient simulations, already presented in Chapter 3, are reproduced here in Figs. 4.6 through 4.9 or urther analysis. As already pointed out in Chapter 3 transer unctions in Figs. 4.7 and 4.9 show that the amount o damping added to output ilter and o reduction in its pole requency depends on parameters values and/or operating conditions or both ZVS-FB and ZVZCS- FB converters. With parameter value Set both sot-switched converters change the damping actor by a airly large amount albeit in opposite directions. For the other parameter value set the ZVZCS-FB converter exerts a very small reduction in damping whereas the ZVS-FB converter introduces a large increment. Transient responses in Fig. 4.6 or parameter Set show that voltage conversion ratio, i.e. output voltage, is larger in the ZVS-FB converter whereas Fig. 4.8 shows the opposite or parameter Set. From these observations it looks likely or the ZVZCS-FB converter to add either positive or negative damping to the output ilter depending on parameter values and operating conditions as Appendix C explains in more detail. 15

140 4.4.. Small-signal experimental results Figure 4.30 shows experimental voltage to output transer unction or Buck and ZVZCS-FB converters or parameter value Set. Peaking or ZVZCS-FB converter is higher than that or the Buck converter as predicted by the small-signal average model. Dierences between experimental and simulation results are mostly due to idealization o components, i.e. neglect o parasitics, hysteresis and tolerances. 16

141 Average Model Average and Switching Model Average Model Average and Switching Model Figure 4.. Whole transient and zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 5 with zero initial state or both models. 17

142 Average Model Switching Model Average Model Switching Model Average Model Switching Model Average Model Figure 4.3. Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 5 with zero initial state or both models. 18

143 Average Model Average and Switching Model Average Model Average and Switching Model Figure 4.4. Whole transient and zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 6 with zero initial state or both models. 19

144 Average Model Switching Model Average Model Switching Model Average Model Switching Model Average Model Figure 4.5. Zoom in o ilter inductor current and capacitor voltage rom switching (green) and second average (pink) models or parameter set 6 with zero initial state or both models. 130

145 ZVS-FB Buck ZVZCS-FB ZVZCS-FB Buck ZVS-FB Figure 4.6. Capacitor voltage (top) and ilter inductor current (bottom) transient response rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set. 131

146 ZVZCS-FB Buck ZVS-FB Buck ZVS-FB ZVZCS-FB ZVZCS-FB Buck ZVS-FB Buck ZVS-FB ZVZCS-FB Figure 4.7. Control to capacitor voltage (top) and control to ilter inductor current (bottom) transer unctions rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set. 13

147 Buck ZVZCS-FB ZVS-FB Buck ZVZCS-FB ZVS-FB Figure 4.8. Capacitor voltage (top) and ilter inductor current (bottom) transient response rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set. 133

148 ZVZCS-FB Buck ZVS-FB Buck ZVS-FB ZVZCS-FB ZVZCS-FB Buck ZVS-FB Buck ZVS-FB ZVZCS-FB Figure 4.9. Control to capacitor voltage (top) and control to ilter inductor current (bottom) transer unctions rom new average models or Buck (red), ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set. 134

149 50 ZVZCS 40 Magnitude (db) BUCK 0 60 Phase (deg) BUCK ZVZCS Frequency (khz) Figure Experimental control to capacitor voltage (top) transer or Buck and ZVZCS-FB converters with parameter set. 135

150 5. MODELNG AND MODULATON FOR QSS-ZVZCS THREE-PHASE BUCK RECTFER The new procedure and the average model or the ZVZCS-FB-PWM dc-dc converter rom the previous chapter are extended here to develop a counterpart or the Quasi-Single-Stage (QSS) ZVZCS three-phase buck rectiier shown in Fig. 5.1(a). Average steady-state operation occurs over one line voltage cycle, e.g. 60Hz, and hence average along the switching requency orbit to obtain autonomous average model, as in previous chapters, no longer applies. Nevertheless, the average model still can represent most o the rectiier s dynamics and can be used or stability analysis. Assuming that closed-loop bandwidth dynamics is much aster than line requency allows us to consider the QSS-ZVZCS rectiier as operating in a quasi-steadystate tracking condition. This new average model revealed strong nonlinear relations between applied and eective duty-cycles o standard space vector modulation (SVM). Those nonlinearities are the source o increased input current distortion and output voltage ripple. these were let to be solely counteracted by the eedback loop, the latter would have to exhibit very large bandwidth, which is already constrained by the switching requency. Based on insight provided by the development o the average model, a new modulation scheme together with eed-orward duty-cycle compensation is proposed to eectively minimize output voltage ripple with slight ac current distortion, while allowing use o the same single-loop control strategy. Experimental results veriy average model predictions as well as modulation and duty-cycle compensation scheme eicacy. 5.1 Three-Phase Buck Rectiier Operation o the three-phase PWM buck rectiier, Fig. 5.(a) is reviewed irst to help desription o its synchronization with the ZVZCS-FB converter. According to the nature o the input and output variables (currents and voltages) and the direction o energy low, three phase converters can be classiied as current source or voltage source rectiiers or inverters. The input variables o the buck rectiier are the three phase input voltages and the dc current source. The output variables are the dc link voltage and the three-phase AC input currents. Hence the buck rectiier can be also viewed as a Voltage Source Rectiier. The process o synthesizing the low requency output variables o the converters could be described as ollows [H3, N3]: 136

151 S1 Sap Sbp Scp C blk p L lk L sa S3 N : 1 D1 + V s - x y p San Sbn Scn S S4 D n Va Vb Vc Buck Rectiier (SVM) ZVZCS- FB Converter (Phase Shited Modulation) Fig.5.1. QSS-ZVZCS three-phase rectiier L L + - Vo 137

152 V a V b V c S ap S bp S cp i a i b i c S bn S cn S an a) Simpliied three-phase buck rectiier structure p n S bn S ap S cn S bp S an S cp v a v b v c Sector 6 Sector 1 Sector Sector 3 Sector 4 Sector 5 b) nput phase voltage determines 60 0 electric sectors and the corresponding switch that is always-on throughout the sector Fig. 5.. Three-phase buck rectiier and electric sectors. 138

153 output current, For a set o input voltages, v v v a b c = V = V = V m m m cos( ωt + ϕ ), cos( ωt π 3 + ϕ ), cos( ωt 4π 3 + ϕ ), (5.1) i o =, (5.) desired set o input currents, i i i a b c = = = m m m cos( ωt + θ ), cos( ωt π 3 + θ ), cos( ωt 4π 3 + θ ), (5.3) and desired dc link voltage, Vout = Vpn, (5.4) determine the control law requirements or the switches o the ront-end rectiier. The six-step modulation o the three-phase PWM buck rectiier is described in the ollowing with reerence to Fig Due to voltage sources on the AC side and current sources on the DC side o the rectiier, the converter switches can assume only six allowable combinations that yield non-zero phase currents and three combinations that yield zero phase currents. n space vector representation, the input phase currents are thereore synthesized rom 7 discrete current vectors 0 to 6, also called current switching state vectors (SSVs). The set o SSVs that yield non-zero phase currents orm the VSR hexagon as shown in Figure 5.3(a). The parenthesized symbols in the VSR Hexagon represent the switches that are conducting during the synthesis o the respective current vector. The triangular area between two adjacent space vectors is called a sector and it is analog to the sectors in Fig. 5. (b). The space vector o the desired phase currents i re, called the reerence vector, can be synthesized as a time weighted average o the two adjacent non-zero SSVs and an appropriate zero SSV over a switching cycle T s. Since the operation o the converter within the sectors has circular symmetry, the duty cycles o the three SSVs belonging to a sector that are used or the synthesis o the reerence vector over a switching cycle are given by: d d d 1 0 = m sin( 60 = m sinθ, = 1 d 1 i d 0 θ ), i (5.5) 139

154 3 (S bp, S cn ) d 4 (S bp, S an ) o (S ap, S cn ) d (S cp, S an ) (S cp, S bn ) 1 i re 1 (S ap, S bn ) θ i i re duty cycle ii duty cycle i θ i a) SVM hexagon and vector synthesis b) Normalized duty-cycle variation within electric sector 1 V a V b V c S ap S an 1 S bp S cp p i a i V a i a i a i V a b i i b c V b i b c V b i c S bn S cn S bn S cn an bn cn V c V c S S S n S ap S an S bp S cp p n S ap 0 S bp S cp p n a) Circuit topologies or electric sector 1 Fig.5.3. Three-phase buck rectiier with standard SVM 140

155 Phase Currents d 1 d ib i c L i a b) deal phase currents (Amp) and output voltage ripple (Volt) Vo d 1 d Rail Voltage V pn V ab Vac a) Normalized duty cycles c) Pulsed waveorms Fig.5.4. Three-phase buck rectiier ideal SVM operation 141

156 where d 1, d and θ i are shown in Figure 5.3(a) and (b) and 0<m<1 is the modulation index. n this standard SVM operation, the same SSV is applied irst throughout the sixty-degree sector as indicated in Figs. 5.3(b) and (c). The major advantage o this modulation scheme is smooth moving average o the phase currents and output voltage. With these duty cycles and ixed m and the current source value, the local averages o the phase currents are sinusoidal (5.3), and the average voltage V pn is dc as desired, Fig. 5.4(a), V 3 = m. (5.6) pn V m The sectors o the VSR hexagon shown in Figure 5.3(a) correspond directly to the sector within the period o the desired phase currents. The angle θ i in (5.5) and Fig. 5.3(a) and (b) is the angle within the sector, and the duty cycles d 1 and d can then be expressed as: d d 1 = m = m i1, i, (5.7) where i 1 and i are the two phase currents that have the same sign within the current 60 0 segment. t should be noted that SSV duty cycles given by (5.7) are not the duty cycles o the individual switches but o the switching combinations that realize the same. Also the term normalized duty-cycles used in Figs. 5.3, 5.4 and 5.6 denotes duty-cycles with m = Three-phase buck rectiier average model The average circuit model or the three-phase buck rectiier shown in Fig. 5.5 [H3, N3] can also be easily obtained with the procedure given above by starting with the circuit topologies and pulsed waveorms shown in Figs. 5.3 and 5.4. The current source is assumed constant during a switching cycle, i.e. no ripple, and the sector duty-cycles are given by (5.5). The quantities d a, d b and d c represent ac phase-current duty-cycles, da = dap dan, db = dbp dbn, dc = dcp dcn, whereas d ab, d bc and d ca correspond to linevoltage duty-cycles, dab = dap dbp, dbc = dbp dcp, dca = dcp dap. The ormer are the individual contributions o to i a, i b and i c and the latter are the individual contributions o instantaneous V ab, V bc and V ca to the rail voltage, Normalized values or phase current and line voltage duty-cycles are represented by the solid traces in Fig. 5.13(a) and (b) respectively or a whole line cycle with SVM operation. Since there is no neutral connection, the sum o the three-phase currents is zero at any time and hence the sum o their duty-cycles must equal zero. 14

157 v a v + b v c d a d b d c v N d ab ab v N d bc bc v N d ca ca v pn Fig.5.5. Three-phase buck rectiier average model structure 143

158 duty cycle ii duty cycle i duty cycle i 0 0 θ duty cycle ii θ 60 0 i i a) Normalized duty-cycle variation and SSV sequence within electric sector 1 or standard SVM b) Normalized duty-cycle variation and SSV sequence within electric sector 1 or SVM with swapping Fig.5.6. Three-phase buck rectiier SVM with and without swapping 144

159 5.1.. Three-phase buck rectiier with single-loop control According to (5.5) and (5.7) the modulation index can be varied to control phase currents and rail voltage. When only the modulation index is changed to regulate the output voltage, the control becomes single-loop type, which is the one used in our application. The other parameter that can be changed in the sector duty-cycles, or our control scheme, while still producing sinusoidal phase currents, is the phase shit, i.e. o o instead o 60 and 0 in (5.5) a eedback dependent angle may be added to the argument in the sine unction. This allows control o input displacement actor and turns the control into a two-loop type Modiied SVM (swapping) A modiied SVM operation, named duty-cycle swapping rom here on, and shown in Fig. 5.6, swaps the order o application o the duty-cycles in the middle o the o 60 electric sector so that the larger duty-cycle always appears irst in a switching period. Eects o this modulation scheme on the phase currents and output voltage are discussed later in the chapter. 5.. QSS-ZVZCS Three-Phase Buck Rectiier Operation Three-phase buck rectiier and ZVZCS-FB converter synchronization When the three-phase buck rectiier and the ZVZCS-FB converter get directly connected (no energy storage components in between them) to orm the QSS rectiier shown in Fig. 5.1, the switching transitions must be careully synchronized to obtain proper operation o the whole system. According to Fig. 5.3(c), when non-zero SSVs are selected, the current source is connected between two phase-voltages. The ZVZCS-FB converter simulates this current source by connecting relected ilter inductor current, L, to the rails p and n when diagonally opposed ull-bridge switches get activated, Fig. 5.7(a). For the zero SSVs interval either top or bottom switches in the ull-bridge are activated, Fig. 5.7(b). This disconnects the current source rom the ac voltages and takes ull advantage o ZVZCS- FB converter characteristics [W], e.g. reduced conduction losses since ewer switches are connected in series, zero-current switching or some devices in the ront-end buck. Furthermore, to produce balanced driving o the transormer duty cycles o switch combinations in the ront-end buck rectiier are kept the same or positive and negative primary-side semi-cycles, as shown in Fig QSS-ZVZCS three-phase buck rectiier operation with standard SVM Figure 5.8 shows QSS-ZVZCS three-phase rectiier s typical waveorms when the ZVZCS-FB converter section operates in CCM. These waveorms correspond to Sector 1 145

160 d 1 d d 0 p p p V a V b V c V a V b V c V c V a V b n n n p L S N : V + s - - Vo p D1 L S 1 S N : V s - - n p p S 4 D D1 S N : Vs - L + Vo - n p p N : 1 D D1 L + V s p S n p S S4 n D a) Non-zero phase current vectors a) Zero phase current vectors Fig.5.7. Synchronization between three-phase buck rectiier and ZVZCS-FB converter Vo Vo 146

161 o input phase voltages in Fig. 5.(b). n this chapter, only a brie description o CCM waveorms relevant to the development o the averaged circuit model and its simpliied expressions or use in the duty-cycle compensation scheme are derived. From Figs. 5.7 and 5.8 it is apparent that only 6 o the 10 switches are active during a 60 0 sector. The 4 switches o the ZVZCS ull-bridge are activated during every sector and their sequence remains unchanged throughout the entire operating duration o the converter. The switching sequence o the devices in the ront-end buck rectiier is decided by the respective SSVs that have to be made active to synthesize the reerence current vector Topological stages and analytical description Figure 5.8 describes the CCM operation o the converter through equivalent circuit structure or each switch coniguration interval as well as waveorms or bus and bridge voltage, V pn and V ab, primary current, p, bus current, bus, blocking capacitor voltage, v cb, ilter inductor current, and, output and secondary rectiier s voltage, V 0 and V s. Assume the switching cycle starts with the blocking stage at t o (beginning o d 1 ) when bridge voltage V xy becomes positive and the saturable reactor blocks any primary current, and ends at t 1 when the reactor gets saturated. The sum o input line voltage V ab (or Sector 1 in Fig. 5.) and blocking capacitor voltage determines the rate o change o the lux in the saturable reactor. The change o lux is Vline1 + Vcpk Vline + Vcpk ( ) ( ) φ = = blk t1 t0 Dblk Ts, (5.8) N sr N sr where D blk, N sr and V cpk are the blocking stage duty-ratio, saturable reactor number o turns and peak blocking capacitor voltage. On the secondary side, the rectiier output voltage determines the rate o change in the ilter inductor current. During charging stage, (t 1,t ), the same rate o change applies to ilter inductor current, whereas the change in primary current, ater neglecting transormer s magnetizing current, p Vline1 + Vcpk = ( t t1 ) = ( m1) ( Dch Ts ) L, (5.9) Lk where slope m1, shown in Fig. 5.8(a), is deined by the irst bracket, D ch corresponds to the charging stage duty ratio and the remaining quantities are deined in Fig. 5.8(a). 147

162 Blocking Charging Transer 1 Transer Resetting O V xy p Vo Vs V 1 /N V SA L lk /N L /N bus V s Blocking V 0 R L d 1 Ts d Ts dots p p 3 4 m1 m m3 V 1 V 1 /N /N L lk /N L L lk /N L /N bus V s Charging bus /N V s V 0 R L Transer-1 V 0 R L m4 N m 3 4 m4 5 V V Cblk /N /N L lk /N L /N bus L lk /N L /N V s Cir V s Transer- V 0 R L Resetting V 0 R L V Line1 N N V Line t 0 t 1 t t 3 t 4 t 5 t 6 t 0 +T S t V SA V Cblk /N /N L lk /N L Cir V s O V 0 R L a) Typical waveorms in CCM Case 1 b) Switch structures in CCM Case 1 Fig.5.8. QSS-ZVZCS rectiier typical waveorms and switch structures 148

163 At time instant t, primary current and ilter inductor current are related by transormer s turns ratio, i.e. p = N, (5.10) and they remain so through transer stage 1. The latter ends at t 3 with irst commanded duty-cycle d 1, when the buck rectiier selects line voltage V ac, or sector 1 in Fig. 5.(b) i.e. d ( t3 t0 ) = ( Dblk + Dch + Dtr 1 ) s 1 Ts = T. (5.11) Relection o input line voltage and transormer leakage inductance to the secondary side leads to the equivalent circuits shown in Fig. 5.1(b) or this transer stage. Change in the ilter inductor current, ater neglecting blocking capacitor eects, is approximately given by V V ( t t ) = ( N m) ( D ), (5.1) N line1 0 3 = N 3 tr 1 Ts Llk + L where slope N m is deined by the irst bracket and the other terms by Fig Duration o transer stage is directly second commanded duty-cycle d and the change in the ilter inductor current is given by V V ( t t ) = ( N m3) ( d ) (5.13) N line = N 4 3 Ts Llk + L where slope N m3 is deined by the irst bracket and the other terms by Fig. 5.8(a). Resetting stage starts at t 4, when bridge voltage V xy becomes zero and it ends when primary current does the same at t 5. Duration o this stage is given by p 1 4 Llk t = = 5 t4 Dres Ts arcsin. (5.14) L Lk CBlk VCpk Cblk O stage begins at t 5 when saturable reactor blocks any primary current by taking V cpk as its lux rate o change and it ends at (t o + T s ) the with primary switching semicycle when V xy becomes negative as shown in Fig. 5.8(a). 149

164 i dˆ L a N v d ~ L ab ab N + i i dˆ L + L b v N ~ b v d bc v bc S N i dˆ L + V c Cx N v c v d ~ ca ca + N v a v + b v o + Fig.5.9. QSS-ZVZCS PWM rectiier average model structure C R L 150

165 During this stage the change in lux across the saturable reactor is given by ( 1 d d D ) Vcpk 1 res Ts φo =, (5.15) N which together with saturable reactor volt-second blocking capability determines blocking stage duration, i.e. φ blk φsat φo sr =, (5.16) where φblk is given by (5.8). Expressions or peak blocking capacitor voltage, V cpk, and average ilter inductor current L, are calculated next to complete the set o equations and the same approximation to calculate V Cpk value ollowed in Chapter 4 is used here. That is, looking at converter s steady-state operation and taking into consideration relevance o stage s duration upon change in capacitor voltage. These voltage changes during transer and resetting stages are respectively given by and ( D + d ) L tr 1 Ts Vc tr = (5.17) N C L blk ( 4 ) Llk ( Dtr 1 + d ) Ts Vc res =, (5.18) N From Fig. 5.8, ater neglecting the voltage change during charging stage, V Cpk is given by V cpk V = c tr + V c res. (5.19) On the other hand, L is calculated as [ D ( + ) + d ( + ) + ( 1 D d ) ( )] 1 L = tr tr where V0 ( 5 4 ) = ( 1 Dtr 1 d ) Ts = m4 ( 1 Dtr 1 d ) Ts 4, (5.0), (5.1) L with slope m4 deined by the term in the irst bracket and Fig. 5.8(a). 151

166 V cpk 0 A A1 -V cpk (D tr1 + D ) T S V cb = A 1 -- A (D tr1 + D ) T S Fig Calculation o average blocking capacitor voltage. 15

167 5.3. New Average Circuit Model or the QSS-ZVZCS Rectiier An input-output structure or the average model o the QSS-ZVZCS rectiier is shown in Fig This structure has been obtained by ollowing the new procedure as in Chapter 4 and in Section together with the assumption o quasi-steady state operation. The starting point is the circuit topologies and pulsed waveorms shown in Fig A detailed derivation is presented below Step 1: Fast/slow classiication o state variables Figures 5.8 indicates that ilter inductor current and output capacitor voltage should be considered slow variables in CCM and used as states in the average circuit model, similarly to Chapter 4. Once again, the primary current is discarded as a relevant average state variable because its moving average is zero in steady state operation and exhibits large components at one hal the switching requency and higher harmonics during transient regime. The blocking capacitor voltage waveorm in Fig. 5.8 indicates that it must be classiied as a ast variable that belongs to an energy holding element. ts treatment here is the same as is the previous chapter, i.e. its eect on peak blocking capacitor voltage is modiied by a time constant Step : LT input/output parts Output ilter and three-phase input phase voltage sources get selected as LT networks according to circuit topologies in Fig. 5.8(b) Step 3: ndependent variable drawn rom LT input network and Dependent variable delivered to LT output network From Figs. 5.1 and 5.8 it looks apparent that average phase currents are the dependent variables drawn rom the three-phase voltage sources, whereas secondary rectiier s output voltage is the independent variable applied to the output ilter during CCM operation Step 4: Calculation o one-cycle average or the variables in the previous step For the average model in Fig. 5.9 the quantities dˆ a, dˆ b and dˆ c represent ac phase-current duty-cycles or equivalent primary duty-cycles as deined in Fig. 5.1, whereas d ~ ab, d ~ bc and d ~ ca correspond to line-voltage duty-cycles or equivalent secondary duty-cycles as deined in Fig The ormer are the individual contributions o relected ilter inductor current to i a, i b and i c and the latter are the individual contributions o relected instantaneous V ab, V bc and V ca to the secondary rectiier voltage. 153

168 10 A 0-10 A 10 A 0-10 A 0.5 V V 1.0 V V d 1 d ia ib d1 - pri ic V o V s d 1 - sec a) Waveorms or ideal buck and experimental ZVZCS rectiiers b) Applied and eective dutycycles or ZVZCS rectiier Fig QSS-ZVZCS rectiier desired and experimental waveorms with typical SVM operation 154