Chapter 6: Converter circuits

Transcription

1 hapter 6. onerter ircuits 6.. ircuit manipulations 6.. A short list of conerters 6.3. Transformer isolation 6.4. onerter ealuation and design 6.5. Summary of key points Where do the boost, buck-boost, and other conerters originate? How can we obtain a conerter haing gien desired properties? What conerters are possible? How can we obtain transformer isolation in a conerter? For a gien application, which conerter is best? 6.. ircuit Manipulations Begin with buck conerter: deried in hapter from first principles Switch changes dc component, low-pass filter remoes switching harmonics onersion ratio is M = 6... Inersion of source and load Interchange power input and output ports of a conerter Buck conerter example = Port Port Power flow 3

2 Inersion of source and load Interchange power source and load: Port Port Power flow = = 4 ealization of switches as in hapter 4 eersal of power flow requires new realization of switches Transistor conducts when switch is in position Interchange of and Port Port Power flow = ' Inersion of buck conerter yields boost conerter ascade connection of conerters onerter onerter = M () = M g () = M () g = M()=M ()M () = M () 6

3 Example: buck cascaded by boost { { Buck conerter Boost conerter = = = g 7 Buck cascaded by boost: simplification of internal filter emoe capacitor ombine inductors and i Noninerting buck-boost conerter 8 Noninerting buck-boost conerter i subinteral subinteral i i 9

4 eersal of output oltage polarity subinteral subinteral i noninerting buck-boost i i i inerting buck-boost eduction of number of switches: inerting buck-boost Subinteral Subinteral i i One side of inductor always connected to ground hence, only one SPT switch needed: i = g iscussion: cascade connections Properties of buck-boost conerter follow from its deriation as buck cascaded by boost Equialent circuit model: buck : transformer cascaded by boost : transformer Pulsating input current of buck conerter Pulsating output current of boost conerter Other cascade connections are possible uk conerter: boost cascaded by buck

5 6..3. otation of three-terminal cell Treat inductor and SPT switch as threeterminal cell: Three-terminal cell A a b B c Three-terminal cell can be connected between source and load in three nontriial distinct ways: a-a b-b c- buck conerter a- b-a c-b boost conerter a-a b- c-b buck-boost conerter 3 otation of a dual three-terminal network A capacitor and SPT switch as a threeterminal cell: A a Three-terminal cell b B c Three-terminal cell can be connected between source and load in three nontriial distinct ways: a-a b-b c- buck conerter with - input filter a- b-a c-b boost conerter with - output filter a-a b- c-b uk conerter ifferential connection of load to obtain bipolar output oltage dc source load onerter = M() onerter ifferential load oltage is = The outputs and may both be positie, but the differential output oltage can be positie or negatie. = M(') ' 5

6 Buck conerter } Buck conerter } ifferential connection using two buck conerters onerter # transistor drien with duty cycle onerter # transistor drien with duty cycle complement ifferential load oltage is = ' Simplify: Buck conerter { 6 =( ) onersion ratio M(), differentially-connected buck conerters =( ) M().5 7 Simplification of filter circuit, differentially-connected buck conerters Original circuit Bypass load directly with capacitor Buck conerter { 8

7 Simplification of filter circuit, differentially-connected buck conerters ombine series-connected inductors e-draw for clarity g i H-bridge, or bridge inerter ommonly used in single-phase inerter applications and in sero amplifier applications 9 ifferential connection to obtain 3ø inerter dc source onerter 3øac load With balanced 3ø load, neutral oltage is = M( ) n = 3 3 onerter = M( ) an n bn cn Phase oltages are an = n bn = n cn = 3 n onerter 3 3 = M( 3) 3 3 ontrol conerters such that their output oltages contain the same dc biases. This dc bias will appear at the neutral point n. It then cancels out, so phase oltages contain no dc bias. 3ø differential connection of three buck conerters dc source 3φac load an bn cn n 3

8 3ø differential connection of three buck conerters e-draw for clarity: dc source 3φac load an bn cn n oltage-source inerter or buck-deried three-phase inerter The 3ø current-source inerter dc source 3φac load an bn cn n Exhibits a boost-type conersion characteristic A short list of conerters An infinite number of conerters are possible, which contain switches embedded in a network of inductors and capacitors Two simple classes of conerters are listed here: Single-input single-output conerters containing a single inductor. The switching period is diided into two subinterals. This class contains eight conerters. Single-input single-output conerters containing two inductors. The switching period is diided into two subinterals. Seeral of the more interesting members of this class are listed. 4

9 Single-input single-output conerters containing one inductor Use switches to connect inductor between source and load, in one manner during first subinteral and in another during second subinteral There are a limited number of ways to do this, so all possible combinations can be found After elimination of degenerate and redundant cases, eight conerters are found: dc-dc conerters buck boost buck-boost noninerting buck-boost dc-ac conerters bridge Watkins-Johnson ac-dc conerters current-fed bridge inerse of Watkins-Johnson 5 onerters producing a unipolar output oltage. Buck M()= M().5.5. Boost M()= M() onerters producing a unipolar output oltage 3. Buck-boost M()= M() 4. Noninerting buck-boost M()= M()

10 onerters producing a bipolar output oltage suitable as dc-ac inerters 5. Bridge M()= M() g.5 6. Watkins-Johnson g or M()= M() onerters producing a bipolar output oltage suitable as ac-dc rectifiers 7. urrent-fed bridge M()= M() g.5 8. Inerse of Watkins-Johnson g or M()= M().5 9 Seeral members of the class of two-inductor conerters. uk M()= M(). SEPI M()= M() 4 3 g.5 3

11 Seeral members of the class of two-inductor conerters 3. Inerse of SEPI M()= M() Buck M()= M() Transformer isolation Objecties: Isolation of input and output ground connections, to meet safety requirements eduction of transformer size by incorporating high frequency isolation transformer inside conerter Minimization of current and oltage stresses when a large step-up or step-down conersion ratio is needed use transformer turns ratio Obtain multiple output oltages ia multiple transformer secondary windings and multiple conerter secondary circuits 3 A simple transformer model Multiple winding transformer i (t) n : n i (t) (t) (t) i 3 (t) 3 (t) : n 3 Equialent circuit model i (t) i '(t) n : n i M (t) (t) M (t) n = (t) n = 3(t) n =... 3 =n i '(t)n i (t)n 3 i 3 (t)... : n 3 Ideal transformer i (t) (t) i 3 (t) 3 (t) 33

12 The magnetizing inductance M Models magnetization of transformer core material Appears effectiely in parallel with windings If all secondary windings are disconnected, then primary winding behaes as an inductor, equal to the magnetizing inductance At dc: magnetizing inductance tends to short-circuit. Transformers cannot pass dc oltages Transformer saturates when magnetizing current i M is too large Transformer core B-H characteristic B(t) (t) dt saturation slope M H(t) i M(t) 34 olt-second balance in M The magnetizing inductance is a real inductor, obeying di (t)= M (t) M dt integrate: (t) i M (t)i M () = t (τ)dτ M Magnetizing current is determined by integral of the applied winding oltage. The magnetizing current and the winding currents are independent quantities. olt-second balance applies: in steady-state, i M (T s ) = i M (), and hence i (t) i M (t) M i '(t) n : n : n 3 i (t) (t) i 3 (t) 3 (t) = T T s (t)dt s Ideal transformer 35 Transformer reset Transformer reset is the mechanism by which magnetizing inductance olt-second balance is obtained The need to reset the transformer olt-seconds to zero by the end of each switching period adds considerable complexity to conerters To understand operation of transformer-isolated conerters: replace transformer by equialent circuit model containing magnetizing inductance analyze conerter as usual, treating magnetizing inductance as any other inductor apply olt-second balance to all conerter inductors, including magnetizing inductance 36

13 6.3.. Full-bridge and half-bridge isolated buck conerters Full-bridge isolated buck conerter Q Q 3 3 i (t) : n 5 i 5 (t) i(t) T (t) s (t) : n Q Q Full-bridge, with transformer equialent circuit Q Q 3 3 i (t) i '(t) i M (t) : n 5 i 5 (t) i(t) T (t) M s (t) Q Q4 4 : n Ideal 6 i 6 (t) Transformer model 38 Full-bridge: waeforms i M (t) T (t) i(t) s (t) i 5 (t) I conducting deices: n i M i M n.5 i.5 i T s T s T s T s T s Q Q 5 5 Q 4 Q t uring first switching period: transistors Q and Q 4 conduct for time T s, applying oltseconds T s to primary winding uring next switching period: transistors Q and Q 3 conduct for time T s, applying oltseconds T s to primary winding Transformer olt-second balance is obtained oer two switching periods Effect of nonidealities? 39

14 Effect of nonidealities on transformer olt-second balance olt-seconds applied to primary winding during first switching period: ( (Q and Q 4 forward oltage drops))( Q and Q 4 conduction time) olt-seconds applied to primary winding during next switching period: ( (Q and Q 3 forward oltage drops))( Q and Q 3 conduction time) These olt-seconds neer add to exactly zero. Net olt-seconds are applied to primary winding Magnetizing current slowly increases in magnitude Saturation can be preented by placing a capacitor in series with primary, or by use of current programmed mode (hapter ) 4 Operation of secondary-side diodes s (t) i 5 (t) : n : n conducting deices: n i 5 6 i 5 (t) s (t) n i(t).5 i.5 i t T s T s T s T s T s Q 5 Q 5 Q 4 6 Q uring second ( ) subinteral, both secondary-side diodes conduct Output filter inductor current diides approximately equally between diodes Secondary amp-turns add to approximately zero Essentially no net magnetization of transformer core by secondary winding currents 4 olt-second balance on output filter inductor : n 5 i 5 (t) i(t) i(t) I i s (t) s (t) n n : n 6 i 5 (t) i.5 i.5 i t T s T s T s T s T s = s = n conducting deices: Q 5 Q 5 Q 4 6 Q M() = n buck conerter with turns ratio 4

15 Half-bridge isolated buck conerter Q a i (t) : n 3 i 3 (t) i(t) T (t) s (t) b : n Q 4 eplace transistors Q 3 and Q 4 with large capacitors oltage at capacitor centerpoint is.5 s (t) is reduced by a factor of two M =.5 n Forward conerter n : n : n 3 3 Q Buck-deried transformer-isolated conerter Single-transistor and two-transistor ersions Maximum duty cycle is limited Transformer is reset while transistor is off 44 Forward conerter with transformer equialent circuit n : n : n 3 i M i ' M Q i i i 3 Q 45

16 Forward conerter: waeforms i M 3 n 3 n M n n n n M Magnetizing current, in conjunction with diode, operates in discontinuous conduction mode Output filter inductor, in conjunction with diode 3, may operate in either M or M T s T s 3 T s t T s onducting deices: Q Subinteral : transistor conducts i M n : n : n 3 i ' on M 3 3 i i i 3 Q on off 47 Subinteral : transformer reset n : n : n 3 i M i ' M 3 3 on 3 i i 3 i = i M n /n Q off on 48

17 Subinteral 3 n : n : n 3 i M = M i ' 3 3 on 3 i i i 3 Q off off 49 Magnetizing inductance olt-second balance n n i M n g M n M = n /n 3 = 5 Transformer reset From magnetizing current olt-second balance: Sole for : = n /n 3 = = n n 3 cannot be negatie. But 3 =. Hence 3 = 3 = n n Sole for n n for n = n : 5

18 What happens when >.5 i magnetizing current M (t) waeforms, <.5 for n = n T s T s 3 T s t i M (t) >.5 T s T s t T s 5 onersion ratio M() : n n 3 n T s T s 3 T s T s t 3 = = n 3 n onducting deices: Q Maximum duty cycle s. transistor oltage stress Maximum duty cycle limited to which can be increased by increasing the turns ratio n / n. But this increases the peak transistor oltage: For n = n n n max Q = n n and max( Q ) = 54

19 The two-transistor forward conerter Q : n 3 4 Q = n max( Q ) = max( Q ) = Push-pull isolated buck conerter Q T (t) : n i (t) i(t) s (t) T (t) Q = n 56 Waeforms: push-pull i M (t) T (t) i(t) s (t) i (t) I n i M i M n.5 i.5 i T s T s T s T s T s onducting Q Q deices: t Used with low-oltage inputs Secondary-side circuit identical to full bridge As in full bridge, transformer olt-second balance is obtained oer two switching periods Effect of nonidealities on transformer olt-second balance? urrent programmed control can be used to mitigate transformer saturation problems. uty cycle control not recommended. 57

20 Flyback conerter buck-boost conerter: Q construct inductor winding using two parallel wires: Q : 58 eriation of flyback conerter, cont. Isolate inductor windings: the flyback conerter M Q : Flyback conerter haing a :n turns ratio and positie output: M :n Q 59 The flyback transformer Transformer model i g i :n M Q i A two-winding inductor Symbol is same as transformer, but function differs significantly from ideal transformer Energy is stored in magnetizing inductance Magnetizing inductance is relatiely small urrent does not simultaneously flow in primary and secondary windings Instantaneous winding oltages follow turns ratio Instantaneous (and rms) winding currents do not follow turns ratio Model as (small) magnetizing inductance in parallel with ideal transformer 6

21 Subinteral Transformer model i g i :n i = M i = i g = i M: small ripple approximation leads to Q on, off = i = i g = I 6 Subinteral i g = Transformer model i /n :n i/n i = n i = i n i g = M: small ripple approximation leads to Q off, on = n i = I n i g = 6 M Flyback waeforms and solution olt-second balance: i /n I/n / = ' n = onersion ratio is M()= = n ' harge balance: i g / I T s 'T s t i = ' I n = c component of magnetizing current is I = ' n c component of source current is I g = i g = I ' onducting deices: T s Q 63

22 Equialent circuit model: M Flyback = ' n = I g I i = ' I n = I g = i g = I ' I ' 'I n n : ' : n I g I 64 iscussion: Flyback conerter Widely used in low power and/or high oltage applications ow parts count Multiple outputs are easily obtained, with minimum additional parts ross regulation is inferior to buck-deried isolated conerters Often operated in discontinuous conduction mode M analysis: M buck-boost with turns ratio Boost-deried isolated conerters A wide ariety of boost-deried isolated dc-dc conerters can be deried, by inersion of source and load of buck-deried isolated conerters: full-bridge and half-bridge isolated boost conerters inerse of forward conerter: the reerse conerter push-pull boost-deried conerter Of these, the full-bridge and push-pull boost-deried isolated conerters are the most popular, and are briefly discussed here. 66

23 Full-bridge transformer-isolated boost-deried conerter i(t) (t) Q Q 3 : n i o (t) T (t) : n Q Q 4 ircuit topologies are equialent to those of nonisolated boost conerter With : turns ratio, inductor current i(t) and output current i o (t) waeforms are identical to nonisolated boost conerter 67 Transformer reset mechanism T (t) (t) /n /n As in full-bridge buck topology, transformer oltsecond balance is obtained oer two switching periods. i(t) I /n /n uring first switching period: transistors Q and Q 4 conduct for time T s, applying olt-seconds T s to secondary winding. i o (t) onducting deices: T s Q Q I/n I/n T s 'T s T s T s 'T s Q Q Q Q 4 Q Q 3 t uring next switching period: transistors Q and Q 3 conduct for time T s, applying olt-seconds T s to secondary winding. Q 3 Q 3 Q 4 Q 4 68 onersion ratio M() (t) i(t) I /n /n Application of olt-second balance to inductor oltage waeform: = ' n = Sole for M(): onducting deices: T s Q Q Q 3 Q 4 T s 'T s 'T s T s T s Q Q Q Q 4 Q Q 3 Q 3 Q 4 t M()= = n ' boost with turns ratio n 69

24 Push-pull boost-deried conerter i o (t) T (t) i(t) (t) Q : n T (t) Q M()= = n ' 7 Push-pull conerter based on Watkins-Johnson conerter Q : n Q Isolated ersions of the SEPI and uk conerter Basic nonisolated SEPI Q Isolated SEPI i i p : n i s Q 7

25 Isolated SEPI i p (t) i i p i i : n i s Q M = i s (t) Ideal Transformer model i (t) i (i i ) / n I M()= = n ' i (t) I onducting deices: T s 'T s T s Q t 73 Inerse SEPI Nonisolated inerse SEPI Isolated inerse SEPI : n Q 74 Obtaining isolation in the uk conerter Nonisolated uk conerter Q Split capacitor into series capacitors a and b a b Q 75

26 Isolated uk conerter Insert transformer between capacitors a and b a b Q M()= = n ' : n iscussion apacitors a and b ensure that no dc oltage is applied to transformer primary or secondary windings Transformer functions in conentional manner, with small magnetizing current and negligible energy storage within the magnetizing inductance onerter ealuation and design For a gien application, which conerter topology is best? There is no ultimate conerter, perfectly suited for all possible applications Trade studies ough designs of seeral conerter topologies to meet the gien specifications An unbiased quantitatie comparison of worst-case transistor currents and oltages, transformer size, etc. omparison ia switch stress, switch utilization, and semiconductor cost Spreadsheet design Switch stress and switch utilization argest single cost in a conerter is usually the cost of the actie semiconductor deices onduction and switching losses associated with the actie semiconductor deices often dominate the other sources of loss This suggests ealuating candidate conerter approaches by comparing the oltage and current stresses imposed on the actie semiconductor deices. Minimization of total switch stresses leads to reduced loss, and to minimization of the total silicon area required to realize the power deices of the conerter. 78

27 Total actie switch stress S In a conerter haing k actie semiconductor deices, the total actie switch stress S is defined as k S = Σ j I j j = where j is the peak oltage applied to switch j, I j is the rms current applied to switch j (peak current is also sometimes used). In a good design, the total actie switch stress is minimized. 79 Actie switch utilization U It is desired to minimize the total actie switch stress, while maximizing the output power P load. The actie switch utilization U is defined as U = P load S The actie switch utilization is the conerter output power obtained per unit of actie switch stress. It is a conerter figure-of-merit, which measures how well a conerter utilizes its semiconductor deices. Actie switch utilization is less than in transformer-isolated conerters, and is a quantity to be maximized. onerters haing low switch utilizations require extra actie silicon area, and operate with relatiely low efficiency. Actie switch utilization is a function of conerter operating point. 8 M flyback example: etermination of S uring subinteral, the transistor blocks oltage Q,pk equal to plus the reflected load oltage: Q,pk = n = ' Transistor current coincides with i g (t). MS alue is I Q,rms = I Switch stress S is = P load S = Q,pk I Q,rms = n I 8 i g onducting deices: M Q I T s :n T s 'T s Q t

28 M flyback example: etermination of U Express load power P load in terms of and I: P load = ' I n Preiously-deried expression for S: S = Q,pk I Q,rms = n I Hence switch utilization U is U = P load S = ' : ' : n I g I M flyback model 8 Flyback example: switch utilization U() For gien,, P load, the designer can arbitrarily choose. The turns ratio n must then be chosen according to n = ' g U.4.3. max U =.385 at = /3 Single operating point design: choose = /3. small leads to large transistor current large leads to large transistor oltage omparison of switch utilizations of some common conerters Table 6.. Actie switch utilizations of some common dc-dc conerters, single operating point. onerter U() max U() max U() occurs at = Buck Boost Buck-boost, flyback, nonisolated SEPI, isolated SEPI, nonisolated uk, isolated uk Forward, n = n Other isolated buck-deried conerters (fullbridge, half-bridge, push-pull) Isolated boost-deried conerters (full bridge, push-pull) ' ' ' 3 3 =.385 =.353 =

29 Switch utilization : iscussion Increasing the range of operating points leads to reduced switch utilization Buck conerter can operate with high switch utilization (U approaching ) when is close to Boost conerter can operate with high switch utilization (U approaching ) when is close to Transformer isolation leads to reduced switch utilization Buck-deried transformer-isolated conerters U.353 should be designed to operate with as large as other considerations allow transformer turns ratio can be chosen to optimize design 85 Switch utilization: iscussion Nonisolated and isolated ersions of buck-boost, SEPI, and uk conerters U.385 Single-operating-point optimum occurs at = /3 Nonisolated conerters hae lower switch utilizations than buck or boost Isolation can be obtained without penalizing switch utilization 86 Actie semiconductor cost s. switch utilization semiconductor cost = per kw output power semiconductordeice cost per rated ka oltage derating factor current derating factor conerter switch utilization (semiconductor deice cost per rated ka) = cost of deice, diided by product of rated blocking oltage and rms current, in $/ka. Typical alues are less than $/ka (oltage derating factor) and (current derating factor) are required to obtain reliable operation. Typical derating factors are Typical cost of actie semiconductor deices in an isolated dc-dc conerter: $ - $ per kw of output power. 87

30 6.4.. onerter design using computer spreadsheet Gien ranges of and P load, as well as desired alue of and other quantities such as switching frequency, ripple, etc., there are two basic engineering design tasks: ompare conerter topologies and select the best for the gien specifications Optimize the design of a gien conerter A computer spreadsheet is a ery useful tool for this job. The results of the steady-state conerter analyses of hapters -6 can be entered, and detailed design inestigations can be quickly performed: Ealuation of worst-case stresses oer a range of operating points Ealuation of design tradeoffs 88 Spreadsheet design example Specifications Maximum input oltage Minimum input oltage Output oltage Maximum load power P load Minimum load power P load Switching frequency f s Maximum output ripple W W khz. Input oltage: rectified 3 rms ±% egulated output of 5 ated load power W Must operate at % load Select switching frequency of khz Output oltage ripple. ompare single-transistor forward and flyback conerters in this application Specifications are entered at top of spreadsheet 89 Forward conerter design, M n : n : n 3 3 Q esign ariables eset winding turns ratio n /n Turns ratio n 3 /n.5 Inductor current ripple i A ref to sec esign for M at full load; may operate in M at light load 9

31 Flyback conerter design, M :n M Q esign ariables Turns ratio n /n.5 Inductor current ripple i 3 A ref to sec esign for M at full load; may operate in M at light load 9 Enter results of conerter analysis into spreadsheet (Forward conerter example) Maximum duty cycle occurs at minimum and maximum P load. onerter then operates in M, with = n n g 3 Inductor current ripple is i = 'T s Sole for : = 'T s i i is a design ariable. For a gien i, the equation aboe can be used to determine. To ensure M operation at full load, i should be less than the full-load output current. can be found in a similar manner. 9 Forward conerter example, continued heck for M at light load. The solution of the buck conerter operating in M is = n 3 n g 4K with K = / T s, and = / P load These equations apply equally well to the forward conerter, proided that all quantities are referred to the transformer secondary side. Sole for : = K n 3 n in M 93 = n n g 3 in M at a gien operating point, the actual duty cycle is the small of the alues calculated by the M and M equations aboe. Minimum occurs at minimum P load and maximum.

32 More regarding forward conerter example Worst-case component stresses can now be ealuated. Peak transistor oltage is max Q = n n MS transistor current is I Q,rms = n 3 I i n 3 I n 3 n (this neglects transformer magnetizing current) Other component stresses can be found in a similar manner. Magnetics design is left for a later chapter. 94 esults: forward and flyback conerter spreadsheets Forward conerter design, M Flyback conerter design, M esign ariables esign ariables eset winding turns ratio n /n Turns ratio n /n.5 Turns ratio n 3/n.5 Inductor current ripple i 3 A ref to sec Inductor current ripple i A ref to sec esults esults Maximum duty cycle.46 Maximum duty cycle.36 Minimum, at full load.38 Minimum, at full load.35 Minimum, at minimum load.5 Minimum, at minimum load.79 Worst-case stresses Worst-case stresses Q Q Peak transistor oltage 78 Peak transistor oltage 5 Q Q ms transistor current i.3 A ms transistor current i.38 A Transistor utilization U.6 Transistor utilization U.84 Peak diode oltage 49 Peak diode oltage 64 ms diode current i 9. A ms diode current i 6.3 A 3 Peak diode oltage 49 Peak diode current i. A ms diode current i 3. A ms output capacitor current i.5 A ms output capacitor current i 9. A 95 iscussion: transistor oltage Flyback conerter Ideal peak transistor oltage: 5 Actual peak oltage will be higher, due to ringing causes by transformer leakage inductance An 8 or MOSFET would hae an adequate design margin Forward conerter Ideal peak transistor oltage: 78, 53% greater than flyback Few MOSFETs haing oltage rating of oer are aailable when ringing due to transformer leakage inductance is accounted for, this design will hae an inadequate design margin Fix: use two-transistor forward conerter, or change reset winding turns ratio A conclusion: reset mechanism of flyback is superior to forward 96

33 iscussion: rms transistor current Forward.3A worst-case transistor utilization.6 Flyback.38A worst case, % higher than forward transistor utilization.84 M flyback exhibits higher peak and rms currents. urrents in M flyback are een higher 97 iscussion: secondary-side diode and capacitor stresses Forward peak diode oltage 49 rms diode current 9.A /.A rms capacitor current.5a Flyback peak diode oltage 64 rms diode current 6.3A peak diode current.a rms capacitor current 9.A Secondary-side currents, especially capacitor currents, limit the practical application of the flyback conerter to situations where the load current is not too great. 98 Summary of key points. The boost conerter can be iewed as an inerse buck conerter, while the buck-boost and uk conerters arise from cascade connections of buck and boost conerters. The properties of these conerters are consistent with their origins. Ac outputs can be obtained by differential connection of the load. An infinite number of conerters are possible, and seeral are listed in this chapter.. For understanding the operation of most conerters containing transformers, the transformer can be modeled as a magnetizing inductance in parallel with an ideal transformer. The magnetizing inductance must obey all of the usual rules for inductors, including the principle of olt-second balance. 99

34 Summary of key points 3. The steady-state behaior of transformer-isolated conerters may be understood by first replacing the transformer with the magnetizing-inductance-plus-ideal-transformer equialent circuit. The techniques deeloped in the preious chapters can then be applied, including use of inductor olt-second balance and capacitor charge balance to find dc currents and oltages, use of equialent circuits to model losses and efficiency, and analysis of the discontinuous conduction mode. 4. In the full-bridge, half-bridge, and push-pull isolated ersions of the buck and/or boost conerters, the transformer frequency is twice the output ripple frequency. The transformer is reset while it transfers energy: the applied oltage polarity alternates on successie switching periods. Summary of key points 5. In the conentional forward conerter, the transformer is reset while the transistor is off. The transformer magnetizing inductance operates in the discontinuous conduction mode, and the maximum duty cycle is limited. 6. The flyback conerter is based on the buck-boost conerter. The flyback transformer is actually a two-winding inductor, which stores and transfers energy. 7. The transformer turns ratio is an extra degree-of-freedom which the designer can choose to optimize the conerter design. Use of a computer spreadsheet is an effectie way to determine how the choice of turns ratio affects the component oltage and current stresses. 8. Total actie switch stress, and actie switch utilization, are two simplified figures-of-merit which can be used to compare the arious conerter circuits.