Digital AudioAmplifiers: Methods for High-Fidelity Fully Digital Class D Systems

Transcription

1 Digital AudioAmplifiers: Methods for High-Fidelity Fully Digital Class D Systems P. T. Krein, Director Grainger Center for Electric Machinery and Electromechanics Dept. of Electrical and Computer Engineering University of Illinois at Urbana-Champaign C. Pascual, Z. Song, P. Midya, R. Roeckner, D. Sarwate

2 Preview Ideal amplifier objectives. Vision of a fully digital amplifier. The switching amplifier and pulse width modulation. Uniform vs. natural sampling. Sampling rate and clock problems. Upsampling. Natural sampling conversion. Noise shaping. 2

3 Preview The system approach. Some comments about sigma-delta. Perfecting the image compensation as compared to feedback. Results from an early prototype. Demo. 3

4 The Linear Amplifier Analog Source Analog Linear Digital Source Digital DAC Linear Noise susceptible Poor efficiency 4

5 The Ideal Amplifier No power consumption from the signal. No loss. No distortion. Response over the full audio bandwidth. Able to drive arbitrary loads. 5

6 The Ideal Amplifier No loss requires lossless devices. Primary choices: energy storage elements and switches. Most conveniently: switches connect to fixed power supplies to deliver energy to a load without loss. 6

7 Vision of a Fully Digital Amplifier The input signal is a digital data stream. All processing is strictly by means of digital computation, in real time. The results of computation govern operation of switches which constitute the output stage. The switches feed the load directly there is no obvious analog process anywhere in the system. The ultimate is a digital loudspeaker. Can this be done? 7

8 The Switching Amplifier Since the output stage comprises switching devices connected to fixed power supplies, the only freedom is in switch timing. Suitable approach: pulse width modulation (PWM). But, what about fidelity? PWM waveform and intended content 8

9 The Switching Amplifier Not All-Digital Digital DAC Comp Class-D Amp LC Low Pass Filter Switching Amplifier All-Digital Digital PCM to PWM Class-D Amp LC Low Pass Filter All-Digital Digital Direct Digital Amplifier Fiber Optic Digital Speaker 9

10 Equivalent Fidelity The need is a switched waveform in which a lossless low-pass filter can recover the signal. Based on bit resolution, noise plus distortion levels to maintain full fidelity: Bits db for LSB db PWM is known in communications to be associated with distortion. Can these levels be achieved? 10

11 PWM Concerns Effects of distortion can be avoided when the switching frequency is relatively high. This is the usual practice in power electronics. Based on natural sampling: Frequency ratio In-band distortion 9-70 db db db db db Our objective becomes: how to do really precise PWM in the digital domain? Analog compare piecewise-linear carrier to signal. 11

12 The General PWM Process 12

13 The General PWM Process Relative component amplitude Fourier results for PWM with a switching ratio of 15: Frequency ratio relative to signal The Fourier spectrum for a naturally-sampled PWM signal implies that a low-pass filter can indeed recover the signal. 13

14 Uniform vs. Natural Sampling Comparison waveform Original analog signal UPWM NPWM 14

15 Sampling and Rates Uniform sampling generates the desired baseband signal, harmonic distortion, and switching frequency distortion. Natural sampling generates only the baseband signal and switching frequency distortion. Required step: The incoming sample stream is based on uniform samples. Compute natural samples instead. CD audio stream: 44.1 khz, 16 bit. PWM: sample value converts to widths. 15

16 The PWM Clock Problem PCM PWM 44.1 ksa/s 16 bit different possible heights 16 bit different possible widths 2.9 GHz needed. (Impractical) How to overcome this problem, and still have "16-bit like" quality? 16

17 PWM Challenges Even if we could directly convert the incoming 16-bit data stream to pulse widths, there would be three problems: The switching frequency is too low. At 44.1 khz, a 10 khz signal has a ratio of just 4.4:1. The samples are uniform, so there would be harmonic distortion in the results. PWM clock problem. Need time resolution of 2-16 times the switching interval. Here 0.35 ns. Now create digital processes to solve these problems. 17

18 Resolving the Problems Switching frequency: use upsampling to compute samples at a higher effective rate. Sampling: find a computational method for conversion to natural samples. Clock problem: use less precise time resolution and figure out how to make it work. 18

19 Upsampling First step: perform upsampling to provide effective information content for the sample conversion process. Here we use a switching frequency of 8x44.1 khz = khz. (Could have used 4x.) Upsampling is well established, and there are a few techniques available. Can be achieved with a digital filter, and works because the signals are bandlimited. Now the clock problem is worse: 43 ps. 19

20 Natural Sampling Conversion An interpolation process. Need relatively high order interpolation for good results. Use Lagrange interpolation. Four-point interpolation gives about -100 db worst-case distortion. 20

21 Noise Shaping At this point we have a sequence of numbers that represent natural sampling times. To manage the clock problem, allow just 256 different pulse widths rather than With khz switching, the time resolution is 11 ns, and the necessary clock rate is a very reasonable 90.3 MHz. Recall that switching will be at khz. Two ways to do this: Truncate the numbers to 8 bits. Use a noise shaping process. 21

22 Noise Shaping Any process we can provide generates quantization noise. A noise-shaping process directs this noise into a particular frequency band. Here a multi-bit sigma-delta modulator provides a high-pass function, and moves quantization noise into the ultrasonic range. The effect on waveforms resembles dithering. 22

23 Noise Shaping Quantization noise Quantization noise 0 20 f (khz) 0 20 f (khz) x(n) u(n) Quantizer y(n) Delta-Sigma Modulator H(z) -1 e(n) 23

24 The System Approach At this point, the computation provides a list of switching times, with 8-bit resolution, and a master clock at khz for switching. All processing has been digital, and the switch timing is precise and constrained to clock boundaries. The timing values are used with counters to command the actual switch operation. 24

25 The System Approach An important detail: the switches must operate with a break-before-make function to prevent momentary short circuits. This is provided by adding 32 extra clock pulses to support dead time. In principle, if the switches now deliver pulses to a loudspeaker, the inertia and our inability to hear high frequencies will yield only the desired signal. 25

26 The System Approach In practice, a khz square wave imposed on a loudspeaker will generate significant power loss. A simple alternative is to provide a lossless LC filter stack between the switches and the speaker, to give the low-pass signal recovery and smooth the loudspeaker drive. 26

27 The System Approach Digital Source Stereo 44.1 khz 16 bit 8x Upsampling khz 16 bit Uniform to Natural Sampling DSP Board PWM Generation PWM Signals Break Before Make Class-D Push-Pull Stage khz 256 possible widths khz 16 bit 4 th order Noise Shaping Butterworth 4 th order LC Low Pass Filter Back-End Stereo khz 8 bits/pulse Stereo 27

28 Power Stage and Low-Pass Filter V SUP D X R X R X D X D F D F V EXC Speaker V EXC B C X T P L 1 L 2 L 2 L 1 T P C X A A T N D F C 1 C 2 / 2 C 1 D F T N B MD 1 MD 2 Break Before Make IN A B 28

29 Comments about Sigma-Delta There are many publications about 1-bit sigma-delta modulators for class-d audio. The switching rate is linked to the oversampling level. Claim is made that sigma-delta has the advantage of noise shaping compared to PWM. We have seen instead that noise shaping is a separate process to be added. 29

30 Comments about Sigma-Delta Typical example from a 2005 paper (Fujimoto, Lo Re, Miyamoto, IEEE J. SSC) uses 128x oversampling to reach 111 db signal-to-noise ratio for 1 khz modulation at essentially 0 output power. This uses 5 to 10 times as much switching and gives much worse SNR than PWM. The result appears to be general: for a given power loss level and given target distortion level, PWM improves over 1-bit sigma-delta methods by a wide margin. 30

31 Comments about Sigma-Delta Not surprising, since this system in effect can be thought of as related to an 8-bit sigmadelta modulator Conventional sigma-delta modulators apply uniform sampling, but with natural sampling. Other publications list THD+N for 1 khz input, an easy case for PWM. (Estimated SNR for this modulation is about 160 db.) We use worst-case 6.7 khz input instead (about 60 db higher THD+N). 31

32 Perfecting the Image It is tempting to use output feedback to improve the results. But the bandwidth is inherently high why risk distortion or other effects? Instead, a compensation approach is a good alternative. Are the switching edges computed by the process the same (with only delay) as those achieved? In other words, does the system meet its open-loop objectives? 32

33 Perfecting the Image Two different approaches are possible The first involves edge detection. Provide a discrete signal from the output that merely detects when edges were observed. Make adjustments of a bit or two in the natural sample computation to correct for any errors. In effect, this provides a digital feedback process, but can be slow. The second involves an integrator. Confirm that the delivered energy, represented in terms of volt-seconds, matches the command. Make a few bits of adjustment to compensate. 33

34 Laboratory Results Uncompensated power stage Input signal Level Output power Efficiency SFDR THD+N > 6.66 khz sinusoid -1 dbfs 55.0 W 88.0% 53 db 0.22% 0 dbfs 68.9 W 89.0% 54 db 0.20% 0 dbfs 84.1 W 87.6% 48 db 0.40% 0 dbfs 90.1 W 87.1% 45 db 0.56% Compensated power stage Input signal Level Output power Efficiency SFDR THD+N > 6.66 khz sinusoid -1 dbfs 50.6 W 81.7% 73 db 0.022% 0 dbfs 63.8 W 83.4% 65 db 0.056% -1 dbfs 51.3 W 79.7% 74 db 0.020% 0 dbfs 64.8 W 82.3% 66 db 0.050% -1 dbfs 54.4 W 79.9% 72 db 0.025% 34

35 Prototype Unit 15 W unit (power stage on the right). No heat sink, surface mount parts. Has been scaled up to about 100 W. 35

36 Demo The fully digital unit is the basis for a Motorola OEM chip set, now in pilot production. The production parts yield THD+N=0.006% at full power. For today, we have an analog naturallysampled PWM amplifier to demonstrate the fundamental process. Nominal switching frequency is 160 khz. Natural sampling performed with LM311 comparator. No noise shaping or extra processes. 36

37 Conclusion The process discussed here begins with a digital audio data stream, processes it computationally, and delivers digital timing signals to a set of switches. For best results, a discrete timing compensation is applied, simply to ensure that the delivered waveforms match those that were commanded. The results, when delivered to a loudspeaker, sound like full fidelity audio. 37

38 Conclusion Is there anything analog here? Was there any conversion? The results work. This demonstrates that natural sampled PWM can provide effectively undistorted output relative to the input digital audio. The design acts to enforce this process as accurately as possible (given practical algorithm limits), with noise shaping added to overcome timing limitations. 38