Multi-bit Sigma-Delta TDC Architecture for Digital Signal Timing Measurement

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1 IEEE International ixed-signals, Sensors, and Systems Test Workshop, Taipei, 22 ulti-bit Sigma-Delta TDC Architecture for Digital Signal Timing easurement S. emori,. Ishii, H. Kobayashi, O. Kobayashi T. atsuura, K. Niitsu, F. Abe, D. Hirabayashi Gunma niversity STARC Gunma niversity Kobayashi-Lab

2 Presented by Daiki HIRABAYASHI ( 平林大樹 ) 2

3 Outline 3 Research Objective Single-Bit & ulti-bit ΣΔ TDCs ulti-bit ΣΔ TDC with DWA ulti-bit ΣΔ TDC with Self-Calibration Circuit Design Conclusion

4 Outline 4 Research Objective Single-Bit & ulti-bit ΣΔ TDCs ulti-bit ΣΔ TDC with DWA ulti-bit ΣΔ TDC with Self-Calibration Circuit Design Conclusion

5 Research Purpose 5 Testing timing difference between two repetitive digital signals. Ex. Data and clock in Double Data Rate (DDR) memory CLK CLK2 T T Short testing time Good accuracy CLK Command コマンド DQS READ Implemented with small circuitry データ Data

6 Our Work 6 sing ulti-bit ΣΔ Time-to-Digital Converter (TDC) Repetitive digital signals ΣΔ TDC can be used Simple circuit Fine time resolution Testing time Linearity Single-bit Long Good ulti-bit Short Bad due to delay elements mismatches Two methods for their compensation Data-weighted-averaging (DWA) Self-calibration

7 Outline 7 Research Objective Single-Bit & ulti-bit ΣΔ TDCs ulti-bit ΣΔ TDC with DWA ulti-bit ΣΔ TDC with Self-Calibration Circuit Design Conclusion

8 Single-Bit ΣΔ TDC 8 CLK T CLK2 CLKa CLK2a Phase CLK in INT out CK Detector CP INT out > : INT out < : D out easurement of timing T between repetitive CLK and CLK2. Number of s at Dout is proportional to T. Time resolution becomes finer as measurement time becomes longer.

9 ulti-bit ΣΔ TDC 9 CLK CLK2 位相 PD 比較器 +Δ +Δ 2 +Δ 7 Phase Detector CK Flash ADC D out 3-bit : =7 comparators and delays Fine time resolution with a given measurement time 7 Shorter measurement time with a given time resolution TDC non-linearity due to mismatches among delay cells.

10 ulti-bit ΣΔ TDC CLK CLK2 INT out Vref 位相 PD 比較器 +Δ +Δ 2 +Δ Phase Detector D 7 D 6 CK Flash ADC D out 3-bit : =7 comparators and delays Fine time resolution with a given measurement time Shorter measurement time with a given time resolution TDC non-linearity due to mismatches 7 among comparators delay cells D 7

11 ulti-bit ΣΔ TDC CLK CLK2 7 delays 位相 PD 比較器 +Δ +Δ 2 +Δ 7 Phase Detector CK Flash ADC D out 3-bit : =7 comparators and delays Fine time resolution with a given measurement time 7 Shorter measurement time with a given time resolution TDC non-linearity due to mismatches among delay cells.

12 ulti-bit ΣΔ TDC 2 CLK CLK2 位相 PD 比較器 +Δ +Δ 2 +Δ 7 Phase Detector CK Flash ADC D out 3-bit : =7 comparators and delays Fine time resolution with a given measurement time 7 Shorter measurement time with a given time resolution TDC non-linearity due to mismatches among delay cells.

13 # of # of Difference in easurement Time Simulation conditions Rising timing edge difference (T) -bit ΣΔ TDC -.9 ~.9ns (Resolution :.4ns) 3-bit ΣΔ TDC -.9 ~.9ns (Resolution :.4ns) Delay time () ns.45ns The number of digital outputs A rising number of outputs for the interval T T[ns] x T[ns] x -9 ulti-bit takes short measurement time for a given time resolution Low cost

14 Outline 4 Research Objective Single-Bit & ulti-bit ΣΔ TDCs ulti-bit ΣΔ TDC with DWA ulti-bit ΣΔ TDC with Self-Calibration Circuit Design Conclusion

15 DWA (Data Weighted Averaging) 5 CLK CK 位相 PD 比較器 Flash ADC D out CLK2 Flash ADC outputs shuffled by DWA logic, fed into s as select signals 7 DWA logic Element Rotation 7 Delay mismatch effects moved to high-frequency (noise-shaping)

16 Noise-Shaping 6 7 Digital input δ Delay DAC cell Analog output Y Digital integrator /z /z Analog differentiator Y( z) ( z) ( / Z) ( z)

17 Digital input DWA & Noise Shaping Cell number delay cell mismatch effects Power Without DWA delay cell mismatch effects Power With DWA f f

Digital input DWA Operation 8 4 3 2 2 5 3 4 6

18 Digital input DWA Operation Cell number Passing a baton in relay race!

19 DWA Effect 9 T T T T CLK CLK2 easure T T is DC signal. delay cell mismatch effects Power Without DWA delay cell mismatch effects Power With DWA f f ismatch effects reduction at DC

20 Difference from ideal line [ps] Difference from ideal line [ps] Simulation of ΣΔ TDC with DWA 2 Output : 99 points Output : 599 points 8 8 x x x -9 T[ns] x -9 T[ns] ΔΣ TDC(with DWA) ΔΣ TDC(without DWA) Reduce the effect of delay mismatches. ΣΔ TDC linearity is improved.

21 Outline 2 Research Objective Single-Bit & ulti-bit ΣΔ TDCs ulti-bit ΣΔ TDC with DWA ulti-bit ΣΔ TDC with Self-Calibration Circuit Design Conclusion

22 ΣΔ TDC with Self-Calibration 22 Enable Self-calibration circuit: inverter,, counter, memory easure delay values and store them in memory.

23 Self-easurement of Delay 23 easurement : +Δ CLKref +Δ +Δ 2 +Δ N Counter Enable CLKosc CLKref CLKosc Ring oscillator with a delay cell to be measured. Counter measure the number of the pulses. Δ can be calculated. easured delay values are stored in memory.

24 Time Signal & Ring Oscillator 24 easurement : +Δ CLKref +Δ +Δ 2 +Δ N Counter Enable Ring oscillator CLKosc öbius strip

25 Self-easurement of Delay 25 easurement : +Δ CLKref +Δ +Δ 2 +Δ N Counter Enable CLKosc Oscillation frequency f 2

26 Essence of Proposed ethod 26 CLKref +Δ +Δ 2 +Δ N Counter Enable CLKosc Time flies like an arrow!

27 Proposed Error Correction Scheme 27 CLK in CK INT out Flash ADC D out D out D out D out Δ +Δ 2 +Δ 3 4+Δ +Δ 2 +Δ 3 +Δ T Obtain TDC raw output (Dout) for two input clocks. Read delay values from memory, and compensate for the output based on them.

28 Difference from ideal line [ps] Difference from ideal line [ps] Simulation of Self-Calibration 28 Output : 99 points Output : 599 points x x -9 T[ns] x x -9 T[ns] ΔΣ TDC(with Self-Calibration) ΔΣ TDC(without Self-Calibration) ΣΔ TDC linearity is improved.

29 Outline 29 Research Objective Single-Bit & ulti-bit ΣΔ TDCs ulti-bit ΣΔ TDC with DWA ulti-bit ΣΔ TDC with Self-Calibration Circuit Design Conclusion

30 Single-Bit ΣΔ TDC 3 PFD + Integrator p Down Phase Frequency Detector Charge Pump with Operational Amplifier

31 ulti-bit ΣΔ TDC 3 Delay cell array

32 Circuit Design of ulti-bit ΣΔ TDC 32 Array of comparators whose outputs are connected to select signals.

33 DWA Logic 33 Simple digital circuit: Two Registers, Encoder, Adder, Barrel Shifter

34 Outline 34 Research Objective Single-Bit & ulti-bit ΣΔ TDCs ulti-bit ΣΔ TDC with DWA ulti-bit ΣΔ TDC with Self-Calibration Circuit Design Conclusion

35 Circuit Performance Comparison 35 Flash TDC -bit ΣΔ TDC ulti-bit ΣΔ TDC (without correction) ulti-bit ΣΔ TDC (with correction) Circuitry 〇〇 Resolution Accuracy 〇 Time 〇〇

36 Conclusion 36 We propose to use ΣΔ TDC for digital signal timing measurement. ulti-bit ΣΔ TDC. Short measurement time Fine time resolution. Non-linearity due to mismatches among delay cells. Two techniques to improve linearity DWA Self-Calibration (signal is time ) Low cost, high quality digital timing test can be realized.

37 37

38 Appendix 38

39 Flash TDC Flash TDC 39 Start T D Q D Q D Q Stop Encoder Dout Arbitrary digital timing signals can be measured one input. Circuitry is large. Time resolution is. easured repetitive digital signals. High quality testing is required. Arbitrary signals T is changed. Repeatitive signals T is constant.

40 How to Calculate the Delay Time 4 f k OSC T k ref 2 k k k f OSC T ref 2 k 2 f k f T ref 2 k k=, 2,, 2 N - T ref CLKref CLKosc Number of Pulses : k

41 ΣΔ TDC with Self-Calibration 4 外部回路 CLKref カウンタメモリー 4 2 +Δ +Δ 2 +Δ 3 位相比較器積分器 Flash ADC エンコーダ DSP 3-bit ΔΣ TDC 3 各遅延値に重みをもたせる測定には N-bit で N ステップかかる

42 A difference with an ideal line [ps] Comparison of Linearity 42 3-bit ΔΣ TDC (Delay Time(Ideal) : =.45ns) 22 x ΔΣ TDC (with Element Rotation) ΔΣ TDC (with Self-Calibration) x -9 Output pulses : 99 T[ns] Ideal state : The error is from -2ps to +2ps. After calibration : The error is from -2.5ps to +2.5ps. The linearity is improved.

43 シグマデルタ型 TDC 回路の動作 43 Timing Gen CK CLK CLK2 CLKa CLK2a ask CLKb CLK2b - + CLK in INT out CP > : D out = = CLK CLKa CLK2 CLK2a CLK と CLK2 を入力比較器出力により経路選択 CLKa, CLK2a を得る

44 シグマデルタ型 TDC 回路の動作 2 44 Timing Gen CK CLK CLK2 CLKa CLK2a ask CLKb CLK2b - + CLK in INT out CP > : D out CLKa CLKb CLK2a=ask CLK2b タイミングジェネレータにより ask 信号 (= 速い方の信号 ) を発生させる ask 信号と CLKa, CLK2a との論理積をとり立下りを合わせる CLKb, CLK2b を得る

45 シグマデルタ型 TDC 回路の動作 3 45 Timing Gen CK CLK CLK2 CLKa CLK2a ask CLKb CLK2b - + CLK in INT out CP > : D out CLKb CLK2b CLK in INT out - CLKb と CLK2b との差をとり結果の CLK in を積分比較器で INT out をと比較し出力 D out を得る次のクロックでの経路を制御

46 タイミングチャート (D out = のとき ) 46 CLK CLK2 T CLKa CLK2a ask=clk2a CLKb CLK2b CLK in - INT out CK T d

47 タイミングチャート (D out = のとき ) 47 CLK CLK2 T CLKa CLK2a ask=clka CLKb CLK2b CLK in + INT out CK T d

Phase Noise Measurement Techniques Using Delta-Sigma TDC

19 th IEEE IMS3TW, Porto Alegre, Brazil Sept. 17, 2014 Phase Noise Measurement Techniques Using Delta-Sigma TDC Yusuke Osawa Daiki Hirabayashi Naohiro Harigai Haruo Kobayashi Kiichi Niitsu Osamu Kobayashi