Design of Tunable Continuous-Time Quadrature Bandpass Delta-Sigma Modulators

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1 Design of Tunable Continuous-Time Quadrature Bandpass Delta-Sigma Modulators Khaled Sakr, Mohamed Dessouky, Abd-El Halim Zekry Electronics and Communications Engineering Department Ain Shams University Cairo, Egypt Abstract This paper presents a systematic design technique for a tunable continuous-time quadrature bandpass delta-sigma modulator. The tuning range of the modulator covers from 0.05 to 0.45 of the sampling frequency. The design procedure is applied to the design of a second-order modulator. Results show that the Signal-to-Noise Ratio (SNR) is almost constant and no stability problem occurs over the whole tuning range thanks to a Digital-to-Analog Converter (DAC) compensation scheme. Keywords Delta-Sigma, Complex, Tunable, Continuous Time. I. INTRODUCTION Channel selection in RF transceivers is often achieved by an analog mixer and a variable local oscillator (synthesizer) to translate the desired signal around the fixed low IF. Another possible approach is through a fixed local oscillator to translate all RF channels to their IF counterparts, then using a tunable bandpass delta-sigma (BPDS) modulator to select the desired channel while digitizing it in the same time, as shown in Fig. 1. The down-conversion of the digitized channel to the base band is done in the digital domain (digital mixer). This either eliminates the analog synthesizer or move it to the IF stage, which would consume less power [1]. Most receivers use complex IF signal down conversion to eliminate the effect of image signal into the desired band [2]. The ability to place noise-shaping zeros in a complex configuration, and thereby perform asymmetric noise shaping, proves highly beneficial in the modulator of complex inputs versus a real band pass modulator pair. The underlying reason for the superior performance of the quadrature modulator in converting complex inputs is that the half numbers of zeros of each real band pass modulator are wasteful, shaping noise away from negative frequencies; they do not improve noise shaping within the desired band at positive frequencies, and in fact, they degrade it. This is because forcing attenuation on one half of the unit circle hurts attenuation on the other half. The freedom to place notches on only one half of the unit circle means that quadrature modulators provide superior noise shaping for complex inputs [2]. To combine the benefits of tunable BPDS modulators with those of quadrature ones, our motivation here is to explore a systematic design technique for a tunable Continuous-time Quadrature Band-Pass Delta-Sigma (QBPDS) modulator targeting GSM mobile applications. Figure 1. RF receiver with a tunable QuadraturBPΣΔ modulator In section II, system overview and design steps are presented. Section III discusses the method of tuning. Finally, results and conclusions are presented in sections IV and V respectively. II. SYSTEM DESIGN This section discusses the chosen modulator architecture. Part B introduces the basic building block of the modulator, i.e. complex filter. In part C the 2 nd order continuous-time QPBDS modulator is analyzed to get the Noise Transfer Function (NTF). Design steps of continuous-time QPBDS NTF is introduced in part D. Finally the Digital-to-Analog Converter (DAC) compensation block is used to improve the Signal-to-Noise Ratio (SNR). A. Architecture Choice There are two types of Delta-Sigma architectures, Feed- Forward and Feed-Back. A major drawback of the feed-back filter architecture is that the outputs of the integrators contain, besides filtered quantization noise, a substantial part of the input signal. The unity gain frequencies of the lower order integrators (especially the first one) in a feed-back filter have to be much lower than in the case of a feed-forward one, in order to keep the output signal swing within the available /11/$ IEEE 99

2 supply range. However, choosing a unity Signal Transfer Function (STF=1) would solve this issue as will be shown later. Thus, noise and distortion of the higher-order integrators cannot be neglected as they are not heavily suppressed by a high gain of previous integrator stages. This can be a serious problem, especially if the oversampling ratio is low. As a result, power consumption of the feed-back architecture tends to be higher than that of a feed-forward one. As the proposed system is working with high over sampling ratio (OSR), the feed-back architecture was chosen where its STF has no peaking like it would have been in a feed-forward one [4]. B. Complex Filter Structure The main building block in Delta-Sigma Modulators is the loop filter. It consists of a chain of first-order filters whose poles construct the zeros of the modulator NTF. In Complex modulators a complex filter is used to construct the loop filter. As shown in Fig. 2-a the complex filter is composed of two real cross-coupled integrators whose transfer function is given by I(s)=ω u /s, (1) where ω u is the unity gain frequency of the integrator and the pole of the corresponding complex filter [3]. The complex filter transfer function is given by H(s)= ω u /(s-jω u ). (2) Fig. 2-b plots the filter transfer function. Due to its complex nature, the frequency response is not symmetrical around the vertical axis, C. System analysis Any single bit Delta-Sigma Modulator can be modeled as shown in Fig. 3 [3], in which L1 is the transfer function seen by feed-back signal V to the loop filter output Y, and L0 is the transfer function seen by input signal U to the loop filter output Y. So, L1=Y/V and L0=Y/U. The quantizer can be modeled by V=Y+E, where E is the quantization noise. Since the noise and signal transfer functions are defined by NTF=V/E and STF=V/U respectively, so NTF=1/(1-L1), STF= L0/(1-L1). (3) Fig. 4 shows the second-order complex delta-sigma modulator of feed-back architecture. The system contains complex filters with distributed feed-back complex coefficients ai as well as distributed input coupling complex coefficients bi. From (2) and (3) we can get the NTF of the continuous time complex modulator as: NTFn= (s-jω u1 )(s-jω u2 ) NTFd=( (s-jω u1 )(s-jω u2 )+a 1 ω u1 ω u2 +a 2 ω u2 (s-jω u1 )) NTF=NTFn/NTFd (4) Choosing ai=bi and b3=1 will make the STF=1. In addition, the input of any complex filter will not contain any input signal component U, which will reduce the output swing of the integrator Op-Amp [3]. This overcomes the drawback of choosing feed-back architecture mentioned in section II-A. Figure 3. General Model of single bit Delta-Sigma Modulator. Figure 4. a 2nd order Continuous Time Quadrature Delta-Sigma Modulator. H(s) frequency Hz Figure 2. a-complex Filter Architecture b- Complex Filter Transfer function where ω u=2π 0.3Fs. D. Design Steps To complete the system design we have to evaluate ai, bi, ω ui. As mentioned above ω u s are the poles of the complex filters and the zeros of the modulator s NTF. Since the zeros of the NTF must be at the selected channel frequency, Fc, then ω u1 =ω u2 =ω c. The NTF will be synthesized to satisfy the modulator s specifications. By equating the synthesized NTF to the system s NTF concluded from (4), we obtain the proper values of a1 and a2, while STF=1, b1=a1, b2=a2 and b3=1. Next, we will show how to synthesize the Continuous Time Quadrature Delta-Sigma Modulator (CTQDSM) NTF. 1-Synthesizing of CTQDSM will be started by synthesizing of the Discrete Time Low-Pass Delta-Sigma Modulator (DTLPDSM) with the same specs of the required CTQDSM using MATLAB DeLSIG toolbox function

3 synthesizentf [5]. Used specs for the second-order architecture are: an OSR of 155, optimization placement of NTF zeros inside the band of interest and out of band gain 1.5 to maintain the stability of the modulator [3]. 2-Using the MATLAB function d2cm will convert DTLPDSM to CTLPDSM with the same specs of DT. (9). Equation (8) is approximately valid for low values of F c 0.1F s, while it will show system instability for higher values of F c as shown for the SNR simulated in Fig. 6. It s clear that the difference between (8) and (9) is that frequency shifting is achieved also for the feed-back DAC transfer function. Therefore, to solve the problem of high F c SNR degradation we have to apply the frequency shifting to the DAC, by adding a DAC compensation block as shown in Fig. 7 in the path [7],where t on and t off are the on time and off time of the DAC respectively. For a NRZ DAC pulse t on =0 and t off =T s where T s =1/F s Figure 5. Low Pass Continuous Tim NTF and Quadrature NTF at F=0.3Fs. 3-In the resulting CTLPDSM replace each (s) by (s-j*ωc), where ω c is the frequency of selected channel and so the CTLP NTF zeros will be shifted in S domain from DC to ω c resulting in asymmetric CT NTF with zeros around ω c [6]. The resulting CTQ NTF is shown in Fig Equate the obtained CTQ NTF to the model s NTF in (4) to get the proper values of a s and b s. E. SNR Improvement for High Center Frequencies Transforming from Z domain to S domain i.e. from discrete time to continuous time of any Delta-Sigma modulator is ruled by the general relation of Impulse Invariant Transform IIT and so L1(z)=IIT{L1(s) HDAC(s)}, (5) QL1(z)=IIT{QL1(s) HDAC(s)}, (6) where QL1, LPL1 are the L1 function of the quadrature and low pass modulators respectively and HDAC is the DAC transfer function. From the previous section, shifting the LP NTF(s) results in a quadrature NTF(s) as follows: QL1(s)=LPL1(s-jω c ) (7) and by substituting (7) into (6) we get QL1(z)=IIT{ LPL1(s-jω c ) HDAC(s)}. (8) Applying the concept of frequency shifting to (6) yields QL1(z)=IIT{LPL1(s-jω c ) HDAC(s-jω c )}. (9) Equation (8) represents the case we already have using the previous design method and doesn t satisfy the accurate one in Input Amplitude Input Amplitude Figure 6. a-snr Vs. input Amplitude Fc=0.1Fs b-snr Vs. input Amplitude Fc=0.2Fs. 101

4 Figure 7. DAC compensation block. III. TUNABLE DESIGN To maintain the same SNR while changing the selected channel F c, we have to re-compute all loop coefficients a s and b s using the above method for each center frequency. For GSM application we have 125 channels each of which has a bandwidth of 0 khz. a s and b s of each tuning frequency must be set to the proper values that reflect the designed NTF in section II-D. In [1], the curves of all coefficients versus the tuning frequency had been calculated. Then, using a MATLB curve-fitting function, the polynomial functions of such coefficients are obtained in frequency. This method implies that each coefficient will be represented by multiple subcoefficients as an implementation of a polynomial function [1]. However, this is not-practical in our case since each complex coefficient is actually composed of a real and an imaginary part, which will render a non-manageable large number of sub-coefficients. In this design, we used digital approach for coefficient tuning as follows; for an active-rc implementation, coefficients are mainly controlled by resistor values. So, each coefficient is represented by a bank of resistors which will be controlled by a 7-bits digital word to determine the proper value of each resistor. Tuning range will be from 0.05F s to 0.45F s with OSR=155 and sampling Frequency F s =62MHz. Fig. 8 shows the variation of some coefficients with the tuning frequency. The most common issue of any quadrature delta-sigma modulator is the mismatch in the complex filter parameters. This causes signals at image band to leak into the band of interest causing SNR degradation. Many techniques are proposed to solve this issue; either using Dynamic Element Matching [4], or insertion of a zero at the image band in the NTF [2]. To investigate the mismatch effect, system simulation was performed 0 times on Simulink with the insertion of a normally distributed random mismatch with a maximum of 0.5% between filter parameters using MATLAB random function. The mismatch of each parameter is also normally distributed along all the runs. As shown in the histogram of SNR Fig. 11-a, 95% of SNR values are larger than 75, which is sufficient for GSM application, so no need to insert 3rd zero in the image band. From Fig. 11-b, 90% of image-rejection ratio (IRR) values are larger than 38. As shown from table 1, this work achieves the maximum and stable SNR along tuning frequency range with just 2 nd order modulator thanks to using complex configuration and tunable modulator s coefficients. TABLE I. COMPARISON WITH TUNABLE RELATED WORKS This Work [1] [8] [9] [10] Order Quantizer number of bits DT/CT CT CT DT CT DT Archetecture type Feedforward Complex/Real Complex Real Real Real Real Max SNR Sampling 62MHz 90MHz MHz 1MHz 70MHz Frequency Band width 0KHz 0KHz 310KHz 10KHz 0KHz Tuning Range 0.05Fs- 0.45Fs 0.1Fs- 0.4Fs DC- 0.31Fs 0.025Fs- 0.25Fs 0.071Fs- 0.42Fs SNR Variation on tuning range Constant 90 Constant 75 variable variable - Variable Figure 8. Variation of real a 1and real a 2 with the tuning frequency 50 IV. SIMULATION RESULTS Fig.9 shows simulated SNR at different tuning frequencies with maximum SNR at 90 and Effective Number of Bits (ENOB) of 14 bits, while Fig.10 shows power spectrum density for different tuning frequencies. The stable behavior of SNR along the tuning range is due to tunable modulator coefficients and the DAC compensation block Input Amplitude Figure 9. SNR for 0.05F S, 0.1Fs, 0.2Fs, 0.3Fs, 0.4Fs, 0.45Fs 102

5 V. CONCLUSION In this paper, the design of a Tunable Continuous-time Quadrature Delta-Sigma modulator is investigated. In order to obtain stable performance over the whole tuning range, loop coefficients must be changed to satisfy the designed NTF. In addition, taking into account the DAC transfer function during frequency shifting is crucial for uniform SNR. Simulations of a second order system are shown to achieve the noise shaping characteristics of CT Quadrature modulator with ENOB of 14 bits. Figure 10. Power Spectrum Density for 0.05Fs, 0.3Fs, 0.45Fs. Figure 11. a) SNR Histogram Fc=0.45Fs, input amplitude=0.99. b) IRR Histogram Fc=0.45Fs, input amplitude =0.99. REFERENCES [1] Mohamed El-Nozahi, Mohamed Dessouky and Hani Ragai, Tunable bandpass sigma delta modulators, IEEE International Midwest Symp. on Circuits and Systems (MWCAS 03), Cairo, Egypt, December 03. [2] Stephen A. Jantzi, Kenneth W. Martin, and Adel S. Sedra, Quadrature bandpass delta sigma modulation for digital radio IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997, pp [3] Richard Schreier, and Gabor C.Temes, Understandnig Delta-Sigma Data Converters. IEEE Press,WILEY & SONS, November 04, pp [4] Lucien Breems, and Johan H. Huijsing, ContinuousTime Sigma-Delta Modulation For A/D Conversion in Radio Receivers. Kluwer Academic Publishers, 02, pp [5] Richard Schreier, The Delta-Sigma ToolBox Version 7.3, July 3, 09. [6] Stefan Joeres, Song-Bok Kim, and Stefan Heinen, Simulation of quadrature-bandpass sigma-delta analog to digital converters using state space descriptions 18th European Conference on Circuit Theory and Design, 07, pp [7] S. Reekmans, J. De Maeyer, P. Rombouts, and L. Weyten, Improved design method for continuous time quadrature band pass sigma delta ADCs ELECTRONICS LETTERS 14th April 05 Vol. 41 No. 8. [8] K.Yamamoto, A.C.Carusone, F.P.Dawson, A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82 Peak SNDR IEEE Journal of Solid-State Circuits, vol.43,issue 8, Aug.08, pp [9] D. Bisbal, J. San Pablo, J. Arias, L. Quintanilla, J. Vicente, and J. Barbolla, A 3-30 MHz Tunable Continuous-Time Bandpass Sigma- Delta A/D Converter for Direct Conversion of Radio Signals XIX Conference on Design of Circuits and Integrated System, Bordeaux, France November 24-26, 04. DCIS 04. [10] Chien-Hung Kuo, Chang-Hung Chen, Huang-Shih Lin, Shen-Iuan Liu A tunable bandpass ΔΣ modulator using double sampling IEEE International Symposium on Circuits and Systems, 05. ISCAS 05, pp Vol