AN ABSTRACT OF THE DISSERTATION OF. Nima Maghari for the degree of Doctor of Philosophy in

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2 AN ABSTRACT OF THE DISSERTATION OF Nima Maghari for the degree of Doctor of Philosophy in Electrical and Computer Engineering presented on September 15, Title: Architectural Compensation Techniques for Analog Inaccuracies in Σ Analog-to-Digital Converters. Abstract approved: Un-Ku Moon Delta-sigma analog-to-digital converters (ADCs) are suitable for many applications due to several advantages such as relaxed anti-aliasing filter, high signal-tonoise and distortion ratio (SNDR) and most important of all, reduced sensitivity to analog imperfections.this thesis introduces several structures to overcome loop imperfections and stability issues in delta-sigma modulators. First, a new multi-loop delta-sigma modulator is proposed to combine the relaxed circuit requirements of single-loop modulators with the stability of traditional multi-loop modulators. Measurement results of the prototype IC confirmed with opamps with loop gain of less than 30dB, SNDR of over 74dB can be achieved. Also proposed is a new singleloop modulator using a delay-free two-step quantizer enabling the input signals beyond the full-scale range to be processed by the loop. The fabricated prototype IC achieves over 75dB SNDR by allowing signals up to +5dBFS input signals. Third, is a modified dual-slope ADC which achieves first-order quantization noise-shaping. Combined as the quantizer of a second-order delta-sigma loop, the fabricated prototype IC achieves third-order noise shaping with 78dB peak SNDR.

3 c Copyright by Nima Maghari September 15, 2010 All Rights Reserved

4 Architectural Compensation Techniques for Analog Inaccuracies in Σ Analog-to-Digital Converters by Nima Maghari A DISSERTATION submitted to Oregon State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy Presented September 15, 2010 Commencement June 2011

5 Doctor of Philosophy dissertation of Nima Maghari presented on September 15, 2010 APPROVED: Major Professor, representing Electrical and Computer Engineering Director of the School of Electrical Engineering and Computer Science Dean of the Graduate School I understand that my dissertation will become part of the permanent collection of Oregon State University libraries. My signature below authorizes release of my dissertation to any reader upon request. Nima Maghari, Author

6 ACKNOWLEDGMENTS I would first like to thank my advisor, Professor Un-Ku Moon, for his endless efforts and support during my PhD program. His technical excellence as well supportive personality not only helped me throughout these years, but also thought me how to continue on my personal as well as technical life and keep growing in the right path. I would also like to thank my committee members, Professors Gabor Temes, Pavan Kumar Hanumolu and Karti Mayaram for their advice and instruction. Their council has been a clarifying force in my research. I would like to especially thank Sunwoo Kwon for support and friendship. I enjoyed many good discussion we had. I would also like to thank David Gubbins, Rob Gregoire, Omid Rajaee, Tawfiq Musah, Brian Young, Skyler Weaver, Ben Hershberg, Hoyoung Lee, Taehwan Oh, Amr Elshazly, Peter Kurahashi, Abhijith Arakali, Kenyoung Lee, Naga Sasidhar, Igor Vytyaz, and Matthew Brown for their friendship, useful discussions and support. Also, I would want to thank my brother Amin for his continues support during these years. Lastly, I would like to thank my beloved Parisa who gave me the confidence in my work and carried my emotional weight during the hard times.

7 TABLE OF CONTENTS Page 1 INTRODUCTION CMOS Scaling Thesis Organization STABILITY ANALYSIS OF DELTA-SIGMA MODULATORS Delta-Sigma Modulators Single-Loop Modulators Stability Zero-Optimization Signal Transfer Function Opamp Gain Requirements Multi-Stage Noise Shaping Modulators STURDY-MASH DELTA-SIGMA MODULATORS SMASH Delta-Sigma Modulators SMASH Stability System level design Circuit Level Design Operational Amplifiers Quantizers Quantization Error Extraction Front-end DACs Switched-Capacitor Implementation of the Modulator Measurement Results Summary EXTENDED DYNAMIC RANGE SINGLE-LOOP DELTA-SIGMA MOD- ULATORS

8 TABLE OF CONTENTS (Continued) Page 4.1 Quantizer Saturation in Σ Modulators Extended Dynamic Range Single-Loop Modulator Circuit Design Operational Amplifiers Active-Adder Quantizers In-loop Digital Summation and DACs Measurement Results Summary NOISE-SHAPED INTEGRATING QUANTIZERS Integrating Quantizers Traditional Dual-Slope ADCs Noise-Shaped Dual-Slope ADCs Bi-Directional Dual-Slope Noise-Shaped ADC Counting-Clock Jitter Comparator Non-Idealities Noise-Shaped Quantizer in a Delta-Sigma Loop Circuit Implementation Timing of the Quantizer Comparator Measurement Results CONCLUSION BIBLIOGRAPHY

9 LIST OF FIGURES Figure Page 1.1 An example of an 8-QAM pulse in ideal case An example of an 8-QAM pulse at the receiver. The outputs levels are distorted by non-ideal channel effects PSD of the quantization noise High-pass filtering of the quantization noise in delta-sigma modulators. The signal bandwidth is only a fraction of the overall bandwidth A general N th order single-loop modulator The 3 rd order noise transfer function with all the poles at infinity Linearized single-loop delta-sigma structure The magnitude of the quantization noise amplitude at the input of the quantizer V q (z) The linear range of an M-level quantizer (M is odd) The probability density function of the quantization noise. The shaded area denotes q e > 0.9 LSB The histogram of the quantization noise (top) and the input of the quantizer (bottom) for 2 18 sample simulation The SQNR versus varying input amplitude sinewave for a thirdorder system with 7-level quantizer, all poles at infinity and OSR= The histogram for a third-order modulator employing a 7-level quantizer with -8dBFS input sinewave. Most of the occurrences are within the linear range of the quantizer making the system stable The pole-zero map of the third-order system with OFBG= The magnitude transfer functions of the third order system with OFBG=5 and OFBG= The SQNR versus varying input amplitude sinewave for a thirdorder system with 7-level quantizer, OFBG=5 and OSR=

10 LIST OF FIGURES (Continued) Figure Page 2.15 The pole-zero map of the third-order system with OFBG=5 and optimized zeros The implementation of a resonator in a third order modulator The magnitude transfer functions of the third order system with OFBG=5 with both optimized and non-optimized zeros The magnitude of the non-unity signal transfer function of the third-order system with OFBG= A parasitic insensitive integrator The magnitude transfer functions of the third-order system with OFBG=5 and with ideal and non-ideal opamps A two-stage MASH delta-sigma modulator A 1+1 MASH structure SNR of a 2+2 MASH at OSR=16 with varying opamp gain and 1% mismatch in capacitor gain Deriving SMASH modulator from the traditional MASH structure. By removing the digital filters and feeding the second stage output inside the first loop (dashed line) SMASH structure is obtained Gain requirements of MASH and SMASH for the first integrator (rest of the integrators are assumed ideal) Gain requirements of MASH and SMASH for all integrators (varied simultaneously) Quantization noise in the single loop modulator Quantization noise in the SMASH modulator The simplified model for the SMASH modulator The simulated histogram of the input of the quantizer (V q ) for both the SMASH and the single-loop modulators

11 LIST OF FIGURES (Continued) Figure Page 3.8 The simulated one-sided PDF of the V q for the SMASH and the single-loop modulators Implemented 2+2 SMASH modulator General form of the second loop of 2+2 SMASH structure Simulated SNDR vs. input signal amplitude for the proposed 2+2 SMASH modulator using 9-level quantizers for both loops Opamp used for the integrators Passive adder in front of the pre-amplifier Outputs of the first and second quantizers. On the left, the actual wave forms are shown. The histograms of the waveforms are shown on the right The error in the extraction of E 1 can be modeled as an added random error Extraction of the first loop quantization error at the input of the second loop Two DACs at the input of the modulator. One DAC is associated with the first stage quantizer (Q 1 ) and another is associated with the second stage quantizer (Q 2 ) Effect of nonlinearity in front-end DACs. (a) σ=0.1% nonlinearity in DAC A (b) σ=0.1% nonlinearity in DAC B Simulated SNDR degradation due to the mismatch between DAC A and DAC B at the input of the modulator The simplified schematic of the DWA used in this design Single-ended switched-capacitor implementation of the modulator (actual design uses fully differential implementation) Die photograph of the implemented IC Measured output spectrum SNR and SNDR versus input amplitude

12 LIST OF FIGURES (Continued) Figure Page 4.1 A single-loop delta-sigma modulator The proposed extended dynamic range structure. The added auxiliary quantizer injects E 2 and cancels E 1 via the in-loop digital summation When the sum of the input signal and filtered quantization noise are within the linear range of the first quantizer When the sum of the input signal and filtered quantization noise exceeds the linear range of the main quantizer The block diagram of the implemented third-order modulator The active-adder and the quantizer timings (several switches are removed for simplicity) SC-DAC at the input of the second quantizer to extract E Fast digital in-loop addition in thermometer code by multiplexing Die photograph Measured spectrum with 0dBFS input signal Measured spectrum with +3.7dBFS input signal SNDR and SNR versus varying input signal amplitudes for the proposed and traditional structures The traditional dual-slope ADC The timing of the traditional dual-slope ADC for two different DC input signals. In this example, D 1 =3 and D 2 =7 assuming counting is done at both rising and falling edges of the counting clock Similarity between the time-domain and voltage-domain quantization. Each counting edge is similar to a comparator reference Signal transfer function of the dual-slope ADC. The input amplitude is normalized to 0dBFS

13 LIST OF FIGURES (Continued) Figure Page 5.5 The modified discharging phase. The value stored on the integrator at the end of this phase is LSB minus the quantization error 2 of the current sample The bi-directional noise-shaped integrating quantizer The compensation of the signal dependent offset in bi-directional NSIQ structure The jitter in high-speed counting clock. Any error in the counting clock will be translated to voltage and added to the next input signal sample The comparator noise when affecting the output code. The effect is stored in both analog and digital and will be compensated in the next samples A typical low-distortion structure. At the end of the ϕ 2 the output of active-adder has added the signals from different loop filter nodes and the input signal and its ready to feed it to the quantizer Using noise-shaped integrating quantizer, merging it with the active-adder and removing the flash ADC. The output of the active-adder will be discharged and number of pulses during the discharge interval determines the final digital output code The block diagram of the implemented modulator. The proposed bi-directional noise-shaped quantizer is merged with the active adder and it shown with its equivalent linearized model The simplified schematic of the active-adder merged with the bidirectional single-slope quantizer The timing diagram of the operation of the proposed quantizer The continues-time comparator used for both direction and commonmode crossing detection Die photograph of the fabricated prototype Measured 32k-samples FFT output spectrums Measured SNDR and SNR versus varying input signal amplitudes. 104

14 LIST OF TABLES Table Page 3.1 Performance Summary-Sturdy MASH Performance Summary-Extended Dynamic Range Performance Summary-NSIQ structure

15 In memory of my mother who brought all the joy to my life

16 ARCHITECTURAL COMPENSATION TECHNIQUES FOR ANALOG INACCURACIES IN Σ ANALOG-TO-DIGITAL CONVERTERS CHAPTER 1. INTRODUCTION Recent advances in digital wired and wireless communications have put an increasing demand for high-performance analog-to-digital converters (ADCs). According to international technology roadmap for semiconductors [1] the recent challenges are presented as the challenges that RF and AMS technologies have in meeting the demands of wireless applications for cellular phones, wireless local area networks (WLANs), wireless personal area networks (WPAN), phased array RF systems, and other emerging wireless communication, radar, and imaging applications operating between typically 0.4 GHz and 100 GHz. Although some earlier digital codings such as frequency-shift keying (FSK) and amplitude-shift keying (ASK) used binary levels of transmission, the recent and more sophisticated digital modulation schemes such as quadrature amplitude modulation (QAM) hires more symbol information and are extensively used in modern telecommunication schemes. The main effort of these modern modulation schemes is to increase the maximum bit-rate with available bandwidth. For this reason, the traditional binary levels are being replaced with multi-level transmissions such as 16-QAM, 64-QAM and 128-QAM. These data are transmitted through noisy channels and become more susceptible to noise as we move towards

17 2 Volts D(t) Figure 1.1: An example of an 8-QAM pulse in ideal case. Volts D(t) Figure 1.2: An example of an 8-QAM pulse at the receiver. The outputs levels are distorted by non-ideal channel effects. higher-order constellation. To reconstruct these pulses at the receiver, high performance ADCs are required. The bandwidth and the resolution of the ADC are defined by the input signal bandwidth, the channel noise, modulation process, etc. The more number of symbols requirers higher resolution ADC to be able to detect it in noisy channels. An example is shown in Fig. 1.1 where an ideal 8-QAM pulse is illustrated. In this case, an 8-level quantizer should be able to detect all the information of this pulse. However, if this pulse is fed to a noisy channel, the output will get severely distorted as shown in Fig To recover this pulse, a higher resolution ADC is needed.

18 3 Over the past few years, wireless communications became an important topic because of the mobile applications. Standards such as EDGE, UMTS and WiMAX [2] have been employed to increase the communication speed of cell phones, PDAs, Ebook readers, laptops and other portable products. The battery operated nature of these devices demands low power consumption to increase its operating time. This includes both analog and digital circuitry to work with minimum possible power. One of the most difficult challenges of such designs is the ADC used for receiver in these portable devices. On one hand, the bandwidth and resolution requirements are getting higher and higher, and on the other hand, increased battery life is much desired, demanding low-power operation. 1.1 CMOS Scaling Over the past decades, the CMOS process scaling has enabled ultra large scale digital systems on a single chip. It is often desired to also embed the analog circuits such as ADCs and analog filters on the same silicon wafer to reduce the fabrication cost. This implies the analog building blocks to be implemented in the same process as the digital ones. Even though the scaling of transistor dimensions comes with increased switching speed and lowered parasitic capacitance for the minimum size transistors, but for analog processes, this doesn t necessarily implies and advantage; in many analog blocks, large transistors are required to reduce the thermal and flicker noises or increase the output impedance. Furthermore, the power supply and the threshold voltage (V T ) of the transistors are not scaled with the same ratio. The promise of lowered power consumption with lowered power supplies and scaled processes is not always true. For example, in many ADC structures, often

19 4 high gain opamps are needed to provide a clean virtual ground. The power supply and threshold voltage directly affect the dynamic range of the system by lowering the available signal range. To increase the gain of the opamps, one way is to stack more transistors between power supply rails. But this will further reduce the available swing which is already squeezed by minimal power supply voltage. The other way is to use multiple stages to meet the gain requirements, but in this fashion, the power is increased and complicated analog stability techniques such as cascode [3] or nested-miller [4] compensations are required. 1.2 Thesis Organization This thesis deals with improving three main aspects in delta-sigma modulators which are: stability, allowable input signal range and reducing the hardware. These are explored and discussed in details in this thesis, and for each, a new delta-sigma architecture is proposed. First, to provide a background, a review on existing delta-sigma structures is provided in Chapter 2 which discusses the basic stability analysis of these structures. In Chapter 3 a new multi-loop delta-sigma modulator is presented. This structure eliminates the digital filters required in the traditional multi-loop structures, and hence, it enables low-gain opamps to be used. Despite its simplicity, it can have wide verity of stability choices and noise-shaping properties making it suitable for many different applications. Chapter 4 tackles the problem with lowered dynamic range in modern CMOS processes. A simple yet effective delta-sigma structure is proposed which uses a delay-free two-step quantizer. This structure enables even the signal above the full-scale to be processed by the loop, drastically increasing the overall dynamic

20 5 range. Chapter 5 discusses a new quantizer based on the traditional dual-slope ADCs. With a small modification in the traditional dual-slope ADCs, quantization noise shaping is achieved. This structure has wide verity of applications and it can be used both as a stand-alone ADC or as the quantizer in a delta-sigma loop.

21 6 CHAPTER 2. STABILITY ANALYSIS OF DELTA-SIGMA MODULATORS Data converters are divided into two main categories: Nyquist converters and oversampled ones. The Nyquist data converters offer high to ultra-high bandwidth and low to medium resolutions. These types of data converters are prone to circuit non-idealities such as opamp finite gain, MOS transistor noise, mismatches between capacitors and resistors and etc. For this reason, often an analog and/or digital error cancelation schemes follows these converters to compensate for analog inaccuracies. Nevertheless, these ADCs can sample signals up to half of the sampling clock speed making them suitable for many modern communication systems. On the other hand, oversampled converters obtain very high resolution by sacrificing the signal bandwidth. The most well-known and commonly used structure of all oversampled systems is delta-sigma modulator in which both oversampling and quantization noise shaping are employed to further enhance the performance. The main advantage of these structures over the Nyquist ones is the ability to obtain high resolution without demanding highly accurate analog blocks. Hence, often no digital or analog compensation technique is required for these structures. However, since these structures employ a feedback, the stability and limited dynamic range are most critical and are often the major limiting factors of their performance. In this chapter, we provide a fundamental and yet simple analysis on the stability of the delta-sigma modulators. The intend of following analysis is not finding a stable noise transfer function (NTF) for a general delta-sigma loop, but to ana-

22 7 lyze the effects of the power of the quantization noise on the stability given a stable loop filter is provided. Also, the analysis is focused on the low-pass modulators, however, the same concept can be applied to bandpass and high-pass modulators as well. 2.1 Delta-Sigma Modulators Delta-sigma modulators (DSMs) were often used in low frequency applications such as audio and DC converters. The advances in CMOS processes and the demand for higher bandwidth in many applications have motivated these structures to perform in megahertz bandwidth range. The oversampling nature of these structures allows simpler anti-aliasing filtering due to the fact that signal bandwidth is only a fraction of the overall sampling frequency. In delta-sigma modulators, unlike the Nyquist converters, doubling the oversampling ratio will result in drastic performance improvement, theoretically. To analyze this, lets assume that the quantization noise has a uniform power spectral density (PSD) between f s /2 and +f s /2 [5] as shown in Fig. 2.1 with root-mean-square (rms) value of σ 2 e = LSB2 12 (2.1) Based on this definition, calculating the signal-to-quantization noise ratio (SQNR) for a sinusoidal waveform with ac power of Vref 2 /8 will be ref /8 SQNR = 10log( P in ) = 10log( V 2 P noise LSB 2 /12 ) (2.2)

23 8 PSD f s 2 f s f s f Figure 2.1: PSD of the quantization noise. knowing that for an N-bit quantizer, the LSB = V ref 2 N, the above equation simplifies to SQNR = 10log( N ) = (6.02N )dB (2.3) for a Nyquist converter. In these structures, doubling the OSR will only result in 3dB SQNR improvement since it will only reduce the power of the quantization error by a factor of two. In delta-sigma modulators, the idea is to high-pass the quantization error (shape) and chose only a small bandwidth so the quantization noise in the bandwidth of the interest is minimum. The concept of noise shaping is shown in Fig. 2.2 However, the order of quantization noise shaping cannot be increased without bound; the higher the order of the noise shaping results in decreased dynamic range. This will be discussed in details in this chapter. In general, delta-sigma modulators are divided into two main categories, the single-loop modulators and multi-stage noise-shaping (MASH) ones. The single loop modulator inherits the advantage of low DC gain opamps while MASH architectures are more stable. In this section, a brief description on stability of these

24 9 PSD BW f s = 2 OSR f s 2 f s 2 f Figure 2.2: High-pass filtering of the quantization noise in delta-sigma modulators. The signal bandwidth is only a fraction of the overall bandwidth. structures will be provided Single-Loop Modulators In a single-loop modulator, both the signal and the filtered quantization noise is processed in a single loop. An important advantage of this structure is the ability to employ low gain opamps to be used for the integrators, relaxed modulator coefficients and simple pole-zero optimization. However, the price to pay is stability and limited dynamic range especially when high-order modulators are employed. Stability A general N th order single-loop modulator is shown in Fig The H i (z) are often integrators with a transfer function of H i (z) = b i z 1 1 z 1 (2.4)

25 10 a X 0 1 a1 a2 an 1 H (z) H 2(z) H n(z) a n V (z) q E 1 Q 1 Y SL Figure 2.3: A general N th order single-loop modulator. where the opamps are assumed to be ideal. Because for an N th order modulator, the number of employed integrators is N, the output of the modulator is an N th order polynomial containing both the signal and the quantization noise. For the sake simplicity, lets assume the signal is zero and focus on the NTF. Since the quantizer is placed at the back-end of the modulator, it will see the general transfer function of NT F = (1 z 1 ) N Den N (z) (2.5) where Den N (z) =(1 z 1 ) N + z 1 (1 z 1 ) N 1 b N + z 2 (1 z 1 ) N 2 b N b N z N+1 (1 z 1 ) 1 b N b N 1...b 2 + z N b N b N 1...b 2 b 1. (2.6) Theoretically, it is possible to put all the poles of the system at infinity and simplify the system to an N th order ideal differentiator. However there will be a tradeoff between the stability and pole placement of the system. This can be understood in an example provided below where a third-order modulator loop is analyzed. In a third order system based on equation (2.6), the general form of the dennumerator will be

26 11 Den 3 (z) = (1 z 1 ) 3 + z 1 (1 z 1 ) 2 b 3 + z 2 (1 z 1 ) 1 b 3 b 2 + z 3 b 3 b 2 b 1. (2.7) To place all the poles at infinity, one should cancel any z 1 in the denominator. Rearranging above equation yields Den 3 (z) = z 3 (b 3 b 3 b 2 +b 3 b 2 b 1 1)+z 2 ( 2b 3 +b 3 b 2 +3)+z 1 (b 3 3)+1 (2.8) which implies that to cancel all poles, the following coefficients should selected b 3 = 3 b 2 = 1 b 1 = 1 3 (2.9) This selection of the loop coefficients will result in the overall NTF to be NT F 3 = (1 z 1 ) 3. (2.10) Placing all the poles of the system at infinity gives maximum suppression of the quantization error in lower frequencies. This is because, in general, the closer the poles are to the zeros, the less effective suppression will be obtained. Hence, the advantage of pushing the poles to infinity is the maximum efficiency of the zeroes. The magnitude of this NTF is plotted in Fig. 2.4 showing 60dB/decade slope which is consistent with third-order noise-shaping. The out of band gain (OFBG) of the noise transfer function can be evaluated by putting z 1 = 1 and calculate the NT F (z), which in this example will be Max [ NT F 3 (e jω ) ] = [ 1 ( 1) ] 3 = 8. (2.11) The Max [ NT F 3 (e jω ) ] which is the maximum out-of-band gain of the NTF over all the frequency range is also known as the infinity norm or the Chebyshev norm

27 12 50 Magnitude (db) dB/decade Normalized Frequency Figure 2.4: The 3 rd order noise transfer function with all the poles at infinity. and is shown with NT F. For the maximally flat transfer functions, this norm can be simply calculated by putting z 1 = 1. As it will be discussed later, the maximum OFBG of a stable system plays an important role in the stability and the maximum achievable SQNR. Before exploring into the details of the stability, it would be beneficial to analyze the improvement achieved in the in-band quantization noise supersession. In the frequency domain, the magnitude squared of the noise transfer function can be approximated by NT F 3 (z) 2 z=e j2πf = (2sin(πf)) 6 (2πf) 6 (2.12) assuming OSR >> 1, or in other words, f << 1 [6]. The total power of the in-band quantization noise at the output of the modulator can be calculated as σ 2 q σ 2 e 1 2 OSR 1 2 OSR (2πf) 6 df = σ2 e 7 π 6 OSR 7. (2.13) The above equation holds an important value since it shows the dependency of the power of the in-band quantization noise at the output of the modulator to the oversampling ratio. Each doubling of the OSR results in reduction of this

28 13 quantization error by a factor of 128 or 21dB. This will result in 3.5-bits increased resolution. Compared to Nyquist converters, which the benefit of doubling the OSR is only 3dB improvement in the SQNR, delta-sigma modulators gain significant improvement. However, there would be a price to pay, and that is, increasing the modulator order to maximize the efficiency comes with the price of reduced dynamic range and stability concerns. A general rule of thumb for stability of the delta-sigma modulators (modified Lee criterion) [7][8] states that a binary DSM with an NT F (z) is likely to be stable if OFBG or the maximum of the NT F (z) is smaller than 1.5. Accordingly, for a maximally flat noise transfer function, the maximum of the NTF will be equal to the OFBG at f s /2. However, this criteria is neither necessary nor sufficient [9] because single-bit modulators can be extremely non-linear. Delta-sigma modulators are non-linear in nature. That is, the modeling of the quantization noise with a probability density function (PDF) may not be valid, especially in single-bit modulators. However, in high-order modulators, the dependency of the quantization noise to the input signal becomes less and hence the linearized model may be applied. Using multi-bit quantizer also significantly reduces the nonlinear behavior of the modulator. Here, the analysis of stability is based on the linearized model of the system as shown in Fig Here, H(z) denotes the loop filter transfer function. The NTF of this structure can be easily calculated as NT F (z) = H(z) 1 + H(z) (2.14) Although the architecture shown in Fig. 2.5 is a general version of the lowdistortion structure [10], but any other loop filter from other common structures can be simplified to fit in this model (except signal path which is not of a concern

29 14 V Q q E X H(z) Y V Q + q E Figure 2.5: Linearized single-loop delta-sigma structure. at this point). The noise transfer function at the input of the quantizer shown with V q is always V q (z) = NT F (z) 1 = 3z 1 + 3z 2 z 3 (2.15) and since NT F (z) is a high-pass transfer function, the V q (z) is always an allpass transfer function with a magnitude of 1 at zero frequency and a peak at f s /2 for maximally flat NTFs. For the above third-order example, the maximum out-of-band will be V q ( 1) = 7, as shown in Fig It can be seen that the maximum peak occurs at f s /2 equal to 20 log(7) = 16.9dB. An important note should be made here, that is, since the quantization error of each sample is (ideally) uncorrelated from the previous sample, the maximum amplitude of the quantization noise seen at the input of the quantizer is the peak value of V q (z) multiplied by +LSB/2 for the positive side or multiplied by LSB/2 for the negative side. In this case, this translates to ±7LSB/2. To see how this value could affect the stability, lets assume the quantizer references are ±1V. In this case, if a 3-level quantizer is used, then the LSB = 1V and the linear range of the quantizer will be 3/2V, the maximum input quantization noise at the quantizer would be 7 LSB 2 = 3.5V which is much larger that the linear range of the quantizer. Note that for an M-

30 15 20 Magnitude (db) Normalized Frequency Figure 2.6: The magnitude of the quantization noise amplitude at the input of the quantizer V q (z). Y out M M 1 linear range 4 M 1 2 M 1 1 M 3 M 5 M M M M+ 1 M V in Figure 2.7: The linear range of an M-level quantizer (M is odd). level mid-tread quantizer, the LSB would be M 2V M 1 ref as shown in Fig V ref M 1 and the linear range would be

31 16 Base on the above discussion, for a stable transfer function, the maximum of V q (z) times ±LSB/2 should be within the linear range of the quantizer and since the equation (2.16) simplifies to Max[V q (z)] LSB 2 LSB = 2V ref M 1 < M M 1 V ref (2.16) (2.17) Max[V q (z)] < M. (2.18) The above equation is a sufficient (but not necessary) condition for quantizer not to overload. In the provided example, at least a 7-level quantizer (again note that M should be odd) is needed ( LSB 2 = 1 6 = ) to stabilize the loop with minimal available input signal range. It should be also noted that the equation (2.18) is an upper bound for the maximum quantization noise fed to the quantizer: the case that the all uncorrelated samples of the quantization noise become either +LSB/2 or LSB/2 will rarely or never occur. For example, the probability of each sample to occur between ±0.9LSB/2 and ±LSB/2 based on the required polarity will follow P ( 0.9LSB 2 P ( 0.9LSB 2 P ( 0.9LSB 2 > q e (z 3 ) > LSB 2 ) = < q e (z 2 ) < LSB 2 ) = > q e (z 1 ) > LSB 2 ) = (2.19) This is shown with the shaded area in PDF of the quantization noise depicted in Fig Since this should happen for three consequent samples, the probability of P ( V q ) > 7 0.9LSB/2 = ( )3. (2.20)

32 17 pdf LSB LSB LSB LSB 2 LSB 2 q e Figure 2.8: The probability density function of the quantization noise. The shaded area denotes q e > 0.9 LSB 2. On the negative side (minimum value), the same probability exists, i.e., the probability of V q being below 7 0.9LSB/2 is the same as above. A simulated histogram of V q (z) for the provided third-order modulator employing a 7-level quantizer with ±1V references is shown in Fig The quantization noise shown in the top section is uniformly distributed between ±LSB/2. The bottom figure shows the histogram of the input of the quantizer. The maximum value occurred is 1.16, which is in good agreement with the provided calculations (7 LSB/2 = 1.166), but the probability of its occurrence is very small (2 out of 2 16 samples). So far, one important factor has been eliminated from the picture, and that is, the allowable signal range. To illustrate this, we can extend the equation (2.18) to account for input signal Max [ V q (z) ] LSB 2 + Max [ X(z) ] < M M 1 V ref (2.21)

33 # of occurrences Quantization error (q e ) # of occurrences Input of the quantizer (V ) q Figure 2.9: The histogram of the quantization noise (top) and the input of the quantizer (bottom) for 2 18 sample simulation. meaning the upper limit of the sum of the input signal and the filtered quantization noise should not exceed the linear range of the quantizer. But again, above condition is only sufficient and is not necessary. To illustrate this, for the 7-level example provided, the above equation states that the maximum input is zero. This means the loop is stable only for infinitesimally small input signals. However, this is not the case in practice. To prove this, the amplitude versus SQNR is plotted in Fig where the peak SQNR is 73.5dB. Surprisingly, the maximum tolerated input signal can be about -5dBFS in this system which is in contradiction with above equations. The answer to this ambiguity is, as provided, the probability of V q (z) being in the upper or the lower limits is very small, and hence, only few

34 SQNR (db) Input Amplitude (dbfs) Figure 2.10: The SQNR versus varying input amplitude sinewave for a third-order system with 7-level quantizer, all poles at infinity and OSR=16. samples will exceed the linear range of the quantizer. The histogram of this example is provided in Fig where -8dBFS sinewave has been applied. The linear range of the quantizer which is ±1.16 is shown. Although this histogram has a larger spread compared to the one shown in Fig. 2.9 where the input signal was close to zero, the major portion of the samples are still within the linear range of the quantizer. Hence, the system is stable. So far, the analysis has proved that large number of quantization levels is needed for high-order loops, and even with that, the available signal range might not be sufficient. However, in many designs, the number of the quantization levels is fixed or it is desired not to exceed a certain value because of the added complexity in the front-end DAC. The solution to stabilize high-order loop filters without increasing the number of the quantization levels lies in pole placement of the system. In the provided example, the coefficients of the loop filter where chosen to put all the poles at infinity. However, this might not lead to best achievable performance. Although it has been mentioned that putting all poles at infinity will result

35 # of occurrences Input of the quantizer (V q ) Figure 2.11: The histogram for a third-order modulator employing a 7-level quantizer with -8dBFS input sinewave. Most of the occurrences are within the linear range of the quantizer making the system stable. in maximum efficiency of the zeros of the system, i.e. maximum suppression of the in-band quantization noise, but it also results in larger amount of out-of-band quantization noise which limits the allowable input signal range. To decrease the OFBG, the poles of the modulator can be placed inside the unity circle. In this fashion, the NTF is often selected as Butterworth or inverse Chebyshev for the desired transfer function and out-of-band gain. Fortunately, a very useful tool has been developed [11] to find the optimized pole placement for a given out-of-band gain (and oversampling ratio in case if zero optimization is used). For the discussed third-order example, the OFBG was 8 with all poles at infinity. To see the effect of lowered OFBG, lets analyze the same transfer function but with OFBG=5 using synthesizentf function from Schreier s toolbox. In this case, the NTF will be NT F 5 3 = (1 z 1 ) 3 ( z 1 )( z z 2 ) (2.22)

36 21 Pole Zero Map Imaginary Axis Real Axis Figure 2.12: The pole-zero map of the third-order system with OFBG=5. where the superscript denotes the OFBG. The three poles added to the system inside the unity circle are shown in the pole-zero map of this system illustrated in Fig To realize this NTF, equation (2.8) can be used which results in b 3 = 2.6 b 2 = 0.91 b 1 = (2.23) Since the poles are close to zeros, it is expected that the suppression in lower frequencies not to be as effective. Indeed this is true, since the decreased OFBG will come with the price of increased in-band power. The Fig shows the magnitude transfer functions of the third order system with OFBG=5 and OFBG=8. The in-band power has increased by approximately 2.5dB and the OFBG has decreased by 4dB. The question that arises here is how much this modification enhances the stability of the modulator. To answer this question, the same analysis of the case

37 22 Magnitude (db) OFBG=5 OFBG= Normalized Frequency Figure 2.13: The magnitude transfer functions of the third order system with OFBG=5 and OFBG=8. where all the zeros were placed at infinity should be applied. The input of the quantizer for the modified NTF will be V 5 q (z) = NT F 5 (z) 1 = 2.6z 1 (1 1.08z z 2 ) (1 0.23z 1 )( z z 2 ) (2.24) Since the out-of-band gain of the original NTF was chosen to be 5, the out-ofband gain of the V 5 q (z) will be 4. Hence, in the modified modulator, based on equation (2.18), only 5-level quantizer is sufficient for the stability. If similar to the previous case, a 7-level quantizer is chosen, then based on equation (2.25), the guaranteed maximum input tolerated by the modulator will be Max[ X(z) ] < 7 6 (2.25) resulting in Max [ X(z) ] < 1 2 to be tolerated by the loop. Comparing to the previous case where the maximum input was about -5dBFS with the peak SQNR

38 SQNR (db) Input Amplitude (dbfs) Figure 2.14: The SQNR versus varying input amplitude sinewave for a third-order system with 7-level quantizer, OFBG=5 and OSR=16. of 73.5dB, we expect the modified one with reduced OFBG to be improved in the allowable input signal range. The simulation result is shown in Fig in which the modulator can tolerate the signals up to -3dB with the peak SQNR of 74dB. Although the SQNR hasn t improved significantly (about 0.5dB) in this example, but the fact that the modulator is able to process larger signals is of an important value. This is because, in the previous case (OFBG=8), the SQNR is maximized with lowering in-band quantization noise, but in this case, it is done by increasing the allowable signal range. Having larger signal is more desired since in practical designs, the lower bound of the noise is set by the thermal noise rather than the quantization noise. For this matter, the capacitors of the latter case can be significantly smaller than the former case resulting in lowered power consumption and area. Further reduction in the OFBG can be employed setting a tradeoff between the in-band quantization error and the maximum input signal tolerated by the loop.

39 24 Pole Zero Map Imaginary Axis Real Axis Figure 2.15: The pole-zero map of the third-order system with OFBG=5 and optimized zeros. Zero-Optimization The analysis provided so far was based on placing all the zeros at DC. For a very large OSR, the edge of the signal bandwidth of the modulator will approach zero, and it is most desired to have all zeros at DC. However, if the OSR is not sufficiently large, the signal bandwidth becomes larger and hence, putting all zeros away from the edge of the signal bandwidth may not be as effective. For the same example provided above, with OFBG=5 and OSR=16, the optimized zeros can be calculated using synthesizentf command and results in NT F 5 3 = (1 z 1 )( z 1 + z 2 ) ( z 1 )( z z 2 ) (2.26)

40 25 g 1 X b z z b2 1 z 1 X r b z z 1 V q (z) E 1 Q 1 YSL Figure 2.16: The implementation of a resonator in a third order modulator. which is very close to equation (2.22) except for the difference in 1.977z 1 term in above and 2z 1 term in the non-optimized one. The pole-zero map of the zerooptimized NTF is shown in Fig showing a pair of complex conjugated zeros have moved away from DC on the unity circle. To implement a complex pair of zeros of the NTF, a resonator is needed in the loop. This can be achieved by a simple addition to the loop as depicted in Fig A feedback from the output of the second integrator is added to the input of the modulator. Also, the second integrator is a delay-free integrator to form the resonator. The resonator formed in this fashion results in a complex pair of zeros NT F 3 opt (z) = ( 1 2(1 + gb1 b 2 )z 1 + z 2). (2.27) Den opt (z) The denominator of the NTF can be calculated using the equations(2.6) and equation (2.7) by replacing b 2 with b 2 z 1 resulting in (assuming g 0 for the denominator) Den 3 opt (z) = z 3 (b 3 1)+z 2 ( 2b 3 b 3 b 2 +b 3 b 2 b 1 +3)+z 1 (b 3 b 2 +b 3 3)+1 (2.28) which for OFBG=5, the b i coefficients will be as follows b 3 = 0.97 b 2 = 1.7 b 1 = (2.29)

41 26 and g = The small value calculated for the resonator coefficient makes it negligible in the pole placement. However, for a very small OSR when the zeroes has to be pushed furthered away from DC, the resonator value will become larger and it might be needed to be considered for the pole calculations. The magnitude of the optimized and non-optimized NTFs are shown in Fig The thick vertical line shows the signal bandwidth. It can be seen that although the non-optimized NTF is smaller in low frequency, as we approach to the edge of the signal band it will increase significantly, whereas the zero-optimized one has a pair of zeros near the edge of the signal band resulting in reduced overall quantization noise. The maximum achieved SQNR in this structure is 77dB which shows 3dB improvement compared to the case where all the zeros are placed at DC. With this method, better performances can be obtained as the modulator order is increased. For example, the SQNR improvement for 4 th and 5 th order modulators at OSR=32 can be up to 8dB and 13dB, respectively. Signal Transfer Function The analysis provided so far gave details of the noise-transfer function in the single-loop delta-sigma modulators. The signal-transfer function, however, has its own unique property as well and can affect the circuit requirement such as opamp linearity and slewing requirements. In a traditional single-loop modulator, the signal is only fed to the input of the modulator. However, in many modern structures, either a distributed signal feed-forward [6] or low-distortion structure [10] is used. A general N th order DSM with distributed signal feed-forward was shown in Fig. 2.3 where a 1, a 2,..., a N denoted the feed-forward coefficients. For this structure, the overall signal transfer function (STF) can be calculated as

42 27 Magnitude (db) Zero Optimized All DC Zeros Normalized Frequency Figure 2.17: The magnitude transfer functions of the third order system with OFBG=5 with both optimized and non-optimized zeros. ST F N (z) = Num ST F N(z) Den N (z) (2.30) where Den N (z) follows the equation (2.6) and the Num ST F N (z) is ST F N (z) =a N (1 z 1 ) N + a N 1 z 1 (1 z 1 ) N 1 b N + a N 2 z 2 (1 z 1 ) N 2 b N b N a 1 z N+1 (1 z 1 ) 1 b N b N 1...b 2 + a 0 z N b N b N 1...b 2 b 1. (2.31) The equation (2.30) shows that the poles of the NTF are also the poles of the signal transfer function. However, the numerator is slightly different: it is the weighted sum of the denominator coefficients. In a special case (also commonly used), if a 0, a 1,..., a N = 1, the the STF will be unity, i.e. ST F = 1. Such signal transfer function is very beneficial from the circuit implementation aspect. The reason for this is that the output of the modulator is in the form of Y SL (z) = NT F N (z) + X(z) (2.32)

43 28 thus, the input signal to the first integrator will be V in int1 (z) = NT F N (z). (2.33) Hence, this integrator is only processing the shaped quantization error. Depending on the number of quantization levels, this value might be very small and can lead to only few millivolts of the output swing, greatly relaxing the opamp requirements. Also, the added settling error and non-linearity of the opamps will only affect the shaped quantization error, and hence it will only add to the output noise-floor. The disadvantage of this structure is apparent by looking at STF which equals unity, meaning that this type of STF has no supression for higher frequency inputs and might add to the complexity of the front-end anti-aliasing requirements. To create a low-pass transfer function, the coefficients a 0, a 1..., a N can be used. For example, the signal transfer function of the third-order example with the OFBG=5 can be modified to provide high out-of-band rejection ST F N (z) = 0.343z z z z 1 (2.34) (1 0.23z 1 )( z z 2 ) The STF magnitude is shown in Fig where it shows about 27dB rejection at f s /2. Such high rejection can greatly simplify the front-end anti-aliasing filter with the price of increased linearity and swing requirements of the integrators of the modulator. In the above case, as opposed to the unity STF case, the integrators will process both the signal and the filtered quantization noise. Because the signal is processed in the loop, the integrators will need larger swing and higher linearity. Opamp Gain Requirements This section describes the opamp gain requirement in the single-loop modulators. The focus is based on switched-capacitor (SC) implementation of a parasitic insensitive integrators [13]. A simple switched-capacitor integrator is shown in

44 29 Magnitude (db) Normalized Frequency Figure 2.18: The magnitude of the non-unity signal transfer function of the thirdorder system with OFBG=5. Fig where the open loop gain of the opamp is shown with A. In the ideal case, when A, then the transfer function of the integrator will be V out (z) V in (z) = bz 1 1 z 1 (2.35) where b = C S C I. The analysis provided for stability was based on this ideal transfer function for the integrators. However, in practice, the opamp will have a limited gain and the C S to C I ratio (b) will deviate by c due to capacitor mismatch. In this case, the above transfer function deviates from the ideal case and becomes [6] Assuming D << 1 and b/a << 1 V out (z) V in (z) = b z 1. (2.36) 1 pz 1 b b[1 ( c b A )] and p 1 b A (2.37) The above analysis shows two important aspects of the non-ideal transfer function of the integrator. First is the deviation of the integrator coefficient b from

45 30 C I ϕ 1d V in ϕ 2d C S ϕ 1 ϕ 2 A ϕ 1 V out Figure 2.19: A parasitic insensitive integrator. its ideal value which stems from two different sources: the limited opamp gain and the capacitor mismatch. The limited opamp gain is somewhat predictable and can be accounted for in advance, however, the capacitor mismatch is random and in most of the cases it is not predictable. In overall, when low-gain opamp is used, the effect of the limited opamp gain is much more dominant. For example, +0.1% mismatch in capacitor ratio will only result in b = 1.001b which is negligible. The other aspect of limited opamp gain is the shift of the integrator pole. The new pole has moved from DC to 1 b/a. Since the poles of the integrators are the zeroes of the NTF, the limited opamp gain will result the zeros of the NTF to move towards the origin, reducing the effective DC suppression. The noise transfer function of the previous example (OFBG=5 and all zeros at DC) is shown in Fig Although the noise floor at low frequencies has increased significantly, the SQNR will not be affected as much. The reason can be understood by looking at the edge of the signal band (OSR=16). At this point, the magnitude of the noise transfer function for both cases is 20dB larger than the ideal case, leading that the major part of the noise power at the output is associated with this region rather than low-frequency regions. This is similar to zero optimization (of course this case is not always beneficial) where some zeroes

46 31 50 Ideal Opamp Opamp Gain = 36dB Magnitude (db) Normalized Frequency Figure 2.20: The magnitude transfer functions of the third-order system with OFBG=5 and with ideal and non-ideal opamps. are shifted from DC to the edge of the signal band. Two main reasons that shifting zeros by reducing the opamp gain is not beneficial are: 1-Using limited opamps for integrators results all the zeros to be shifted from DC whereas in zero optimization, often a single zero or a complex pair is kept close to DC. 2-In the zero optimization, zeros are often placed on the unity circle and hence they come in complex-conjugated pairs whereas in low-gain opamp case, they are real and will move on the Real axis from DC towards the center of the unity circle Multi-Stage Noise Shaping Modulators Contrary to the single-loop modulators where all the signal and the quantization noise were processed inside a single loop, MASH structures (also known as cascaded modulators) use cascaded loops to improve the noise shaping. A simple

47 32 X L S1(z) L N1(z) E 1 Q 1 H 1 Y MASH k E 1 L S2(z) L N2(z) E 2 Q 2 H 2 Figure 2.21: A two-stage MASH delta-sigma modulator. two-stage MASH is shown in Fig where L si and L ni denote the signal and noise loop filters of the i th stage, respectively. Digital filters H i are used to cancel the first stage quantization error and k denotes the interstage residue amplification gain. The MASH structure performs high-order noise shaping by feeding the quantization error of the preceding stage to the next stage, which is usually realized by another delta-sigma loop. Since the quantization error is dithered by the loop filter and can be viewed as an added random noise, it may often be regarded independent from the input signal of the modulator. Hence, the operation of the second stage is independent of the first stage and the stability of the modulator is determined by the stability of each individual stages, which are usually chosen to be first or second order modulators. The overall output of the MASH structure shown in Fig can be written as follows Y = ST F 1 H 1 X + (H 1 NT F 1 k H 2 ST F 2 )E 1 H 2 NT F 2 E 2 (2.38)

48 33 where the NTF and STF can be evaluated by knowing L si and L ni transfer functions. Although it may seem that the output contains both quantization errors, with a simple selection of digital noise canceling filters (H i ) the first stage quantization noise can be eliminated from the output. For canceling E 1, it would be sufficient to satisfy following H 1 NT F 1 = k H 2 ST F 2 (2.39) which results in H 1 = ST F 2 and H 2 = NTF 1 (2.40) k The above criteria is straightforward to implement since ST F 2 often only contains several delays, and the NT F 1 can be implemented with a simple digital FIR filter. With this selection, in an ideal case, the first stage quantization error will be canceled and only the second stage quantization error will remain Y = ST F 1 ST F 2 X NT F 1 NT F 2 E 2 (2.41) k For example, if the first loop and the second loops are second order, the final noise transfer function will be a fourth-order transfer function. However, the main advantage of this structure over the single-loop one is that the operation of each stage is independent of the other stage, and hence, the stability analysis simplifies to several independent loops. For this example, The first loop has to satisfy the criteria of equation (2.18), knowing that the maximum V q for a second order system even if all poles are placed at infinity is 3, this system is guaranteed to be stable with only a 3-level quantizer for Q 1. For the second loop to be stable, the same analysis of a regular single-loop can be applied with one exception, the input of the second-loop is the random quantization error of Q 1 and it should be in the linear range of the second loop. In other words, one can design a regular single loop

49 34 modulator that only tolerate -20dB of the full-scale input signal, but the second stage of a MASH structure should be able to process the full-scale quantization error of the first stage without saturation. Since the non-linearity of the DACs in the second loop are shaped by the first loop noise transfer function, large number of quantization levels can be used on the second loop without having to deal with very linear DACs. For the stability of the second loop we have Max [ V q2 (z) ] LSB LSB 1 2 < M 2 M 2 1 V ref (2.42) which yields M 2 > 5, hence a 5-level quantizer is sufficient to guarantee the stability. Larger number of quantization levels can be used in order to achieve smaller E 2 and also to enable interstage gain scaling to further suppress this quantization error. Such good stability and improvement of the noise-shaping property is very promising, but the performance of the MASH structures are not often limited to the noise-shaping or the stability, but to the quantization noise leakage. In practice, the mismatch between the analog transfer functions and the digital noise canceling filters will cause to E 1 to leak to the output and limits the performance of the modulator. To understand this, let us start with a 1+1 MASH modulator with no interstage residue scaling, as shown in Fig In this case, H 2 = 1 z 1 1 z 1 + bz 1 (2.43) based on equation (2.40). However, the noise transfer function of the first loop filter is different from equation (2.43) due to limited opamp gain and possible capacitor mismatch NT F 1a = 1 pz 1 1 pz 1 + b z 1 (2.44) The difference between the NT F 1d (or H 2 ) and NT F 1a is called the leakage transfer

50 35 E 1 X bz 1-z -1-1 Q 1-1 z YMASH E z Q z E H 2 Figure 2.22: A 1+1 MASH structure. function and is equal to 1 z 1 T F leakage = 1 z 1 + bz 1 pz 1 (2.45) 1 1 pz 1 + b z 1 where sub indexes d and a denote the digital and analog transfer functions, respectively. To simplify above transfer function, although it is non-linear with respect to p, b and b coefficients, we can approximate it for two difference cases. First, if b = b and p is very close to 1, then T F leakage1 = (1 z 1 ) [1 (1 1/a)z 1 ] E 1 = E 1 A (2.46) which shows E 1 has appeared at the output only suppressed by the DC gain of the first integrator. The second case is that if we assume p = 1 and the difference between b and b is small, then we will have T F leakage2 (1 z 1 ) (b b )z 1 E 1 = [ c b /a A ](1 z 1 )E 1 (2.47) which shows a noise-shaped leakage not only dependent to the opamp gain, but

51 Opamp gain only Opap Gain + 1% cap mismatch SNR (db) Opamp gain (db) Figure 2.23: SNR of a 2+2 MASH at OSR=16 with varying opamp gain and 1% mismatch in capacitor gain. also to the capacitor matching. In high OSR applications, the non-noise shaped leakage will be dominant since it is only suppressed by the opamp gain. In low OSR applications, both shaped and non-shaped leakages should be taken into account and hence both high gain opamps and excellent capacitor matching is required. The same analysis can be applied to higher order loop filters, although being more complicated, the end result would be similar. For example, in a 2+1 MASH, the leakage of E 1 will appear in three different terms: unshaped, first order shaped and second order shaped. The unshaped term is suppressed by the product of the gain of the opamps of the first loop, the first-order shaped one is suppressed by the first opamp gain, and the second-order shaped one is not suppressed by the gain of the opamps. This does not include the second loop non-ideal behaviors since they will be suppressed by the digital NTF placed at its output. A 2+2 MASH with 5-level quantizer for both Q 1 and Q 2 at OSR of 16 is simulated and the SNR versus the

52 37 opamp gain is plotted in Fig Although this structure can achieve very high SNR, the required opamp gain is at least 60dB. In practice, to account for process and temperature variations, higher gain opamps are required which will make this structure power hungry. In general, higher order loop filters in the first stage will result in lower quantization noise leakage, but same as the single-loop modulators, increasing the order will come with stability concerns. Zero optimization can be also applied to the MASH structure [14] to enhance its performance, but it will not reduce the effect of the quantization noise leakage. Since the digital filter at the output of the second loop should match the noise transfer function of the first stage, optimizing zero in the first loop will come with complicated digital filter to match its counterpart. Thus, second loop is more convenient for optimizing its zeros without changing the digital filters. The MASH structure can employ more number of loops for further performance and stability improvement and the same analysis can be applied: The digital filter of each stage should be the product of the noise transfer functions of the preceding stages. The required opamp gain of the later stages is reduced due to the high loop gain of the preceding stages. In the next chapter, a new multi-loop delta-sigma modulator will be presented which takes benefit from the relaxed circuit requirements of the single-loop modulators but also provides high order of noise shaping without severe stability concerns.

53 38 CHAPTER 3. STURDY-MASH DELTA-SIGMA MODULATORS As discussed in the previous section, the two most commonly used deltasigma modulators are the single-loop modulators and the MASH modulators. The single-loop modulators takes advantage from relaxed circuit requirements such as low gain opamps and inaccurate modulator coefficients but they suffer from severe stability issues as the loop order increases. On the other hand, MASH modulators employ several independent loops to enhance their noise shaping property and achieve good stability, but they are prone to quantization noise leakage due to mismatch between the analog and the digital noise transfer functions. In this chapter a new modulator is presented which combines the improved stability of the multi-loop structures with the relaxed circuit requirements of the single-loop modulators. 3.1 SMASH Delta-Sigma Modulators The key concept of the proposed structure is to eliminate the need for high gain requirements of the opamps in the traditional MASH structure and use only analog blocks to perform the noise shaping. Because the need for high opamp DC gain stems from the use of the digital filters outside the modulator loops, the first step is to remove these filters [15] [16]. Next, to maintain the desired noise transfer function, the second loop output is fed back into the first loop after the first stage quantizer output, in the digital domain. This in-loop digital addition is shown

54 39 X L S1(z) E 1 Y SMASH Y MASH L N1(z) Q 1 STF 2D E 1 L S2(z) E 2 L N2(z) Q 2 NTF 1D Figure 3.1: Deriving SMASH modulator from the traditional MASH structure. By removing the digital filters and feeding the second stage output inside the first loop (dashed line) SMASH structure is obtained. with a dashed line in Fig As it will be discussed later, it is very important to add the output of the second loop after the first stage quantizer in digital domain. If this addition is moved to the input of the quantizer in the first loop (in analog form), it will increase the quantization noise power at this node and thus directly limit the dynamic range of the modulator. For this structure, the signal and noise transfer function would be as follows Y SMASH = ST F 1 X NT F 1 NT F 2 E 2 + NT F 1 (1 ST F 2 )E 1. (3.1) Equation (3.1) shows that the output of the SMASH structure contains three terms. The first term contains the desired signal which only relies on the first loop signal transfer function. The second term contains E 2 which is shaped by the product of the first and second stage noise transfer functions. This is the same as in the traditional MASH structure. The third term which contains E 1, however, is not only shaped by the first stage noise transfer function, but also multiplied by an extra term (1 ST F 2 ). The key idea in this structure is to use this extra term to match the order of noise shaping for both quantization errors. This can be done

55 40 by simply choosing ST F 2 = 1 NT F 2 (3.2) resulting in NT F overall = NT F 1 NT F 2. (3.3) For example, in a 2+2 low-pass SMASH modulator with all zeros placed at DC and all the poles at infinity, the second stage noise transfer function should follow NT F 2 = (1 z 1 ) 2 (3.4) which results in ST F 2 = 2z 1 z 2. (3.5) This will result in fourth order noise shaping for both quantization errors. Later, it will be shown that equations (3.2) and (3.3) can be realized independent of the second loop integrators transfer functions. Unlike the traditional MASH structure where (under ideal conditions) E 1 is canceled and only E 2 appears at the output, in this structure both E 1 and E 2 will appear at the output. This will add 3dB to the noise floor assuming E 1 and E 2 are uncorrelated and σe1 2 = σ2 E2, i.e. same number of quantization levels is used for both Q 1 and Q 2. This could be further reduced by employing interstage gain or extra order of noise shaping [22]. Because the noise transfer function of the proposed SMASH structure is obtained using only the analog loop components (i.e. no digital filter), it is expected to have less dependency on the opamp gain compared to that of the MASH structure. This is demonstrated in Figs. 3.2 and 3.3. These figures illustrate the gain requirements for a 2+2 SMASH and a 2+2 traditional MASH structures. For both structures, 9-level quantizers are used in both loops and the assumed oversampling ratio is 16. As observed in Fig. 3.2, only 25dB opamp DC gain in the first integrator will result in over 80dB SQNR in the proposed SMASH structure. Fig. 3.3

56 41 SQNR (db) Opamp gain (db) 2+2 SMASH 2+2 MASH Figure 3.2: Gain requirements of MASH and SMASH for the first integrator (rest of the integrators are assumed ideal) SQNR (db) Opamp gain (db) 2+2 SMASH 2+2 MASH Figure 3.3: Gain requirements of MASH and SMASH for all integrators (varied simultaneously). shows the opamp DC gain dependency for these structures when all the opamp gains are varied simultaneously. It can be shown that with 25dB opamp DC gain, the proposed structure can achieve extra 30dB SQNR compared to the traditional MASH structure. Another way to observe this is to say that for both structures to obtain the same SQNR, the MASH structure requires extra 25dB DC gain in

57 42 the opamps SMASH Stability In the proposed SMASH structure, although the output of the second loop is fed to the first loop, this addition is done after the first stage quantizer. In other words, an additional amount of quantization noise is injected after the quantizer. This quantization noise is then fed back to the input of the loop and suppressed by the loop filter before it reaches the first stage quantizer. Hence, it will not saturate the quantizer as fast as it would for a regular single loop modulator. This observation is illustrated in Figs. 3.4 and 3.5. Although both modulators can accommodate the same noise transfer function, the quantizer in the single-loop modulator processes all of the shaped quantization noise, whereas in the proposed SMASH structure, this quantizer only processes a fraction of this quantization noise seen in the single-loop modulator, and the rest of it is added after this quantizer. To understand this more clearly, same as any regular delta-sigma modulator, the quantization noise transfer function at the input of the first-stage quantizer (Q 1 ) should be analyzed. For a fourth-order single-loop modulator, we could write the final fourth-order NTF as a product of two second-order NTFs for simplicity NT F 4 SL = NT F 1 NT F 2 (3.6) which leads to V q4 SL = NT F 1 NT F 2 1. (3.7) The details of this analysis was discussed in Chapter 2. However, in the case of the SMASH structure, unlike any other regular delta-sigma modulator, this transfer

58 43 a1 an 1 an E 1 X H 1(z) H n(z) Q 1 Y SL b1 b2 bn Figure 3.4: Quantization noise in the single loop modulator. X L S1(z) E 1 L N1(z) Q 1 Y SMASH E 1 L S2(z) E 2 L N2 (z) Q 2 Figure 3.5: Quantization noise in the SMASH modulator. function is different. Since another path is fed into the first loop as shown in Fig. 3.6, although the final output is still the product of two NTFs, the output of the first quantizer before the digital summation would be different. The output of the second loop of the SMASH follows Y 2 = (1 NT F 1 )E 1 + NT F 2 E 2 (3.8) and hence, the noise transfer function before the digital summation and after the first stage quantizer is V q out = Y SMASH + Y 2 = NT F 2 (NT F 1 1)(E 1 E 2 ) E 1 (3.9) and referring this to the input of the quantizer will result in V q SMASH = NT F 2 (NT F 1 1)(E 1 E 2 ). (3.10)

59 44 X L S1(z) L N1(z) Vq SMASH E 1 Q 1 Vq out Y SMASH (1 NTF 2)E1 + NTF2 E2 Figure 3.6: The simplified model for the SMASH modulator. The above equation holds a significant advantage over regular delta-sigma modulators, that is, to suppress the Max [ V q SMASH (e jω ) ], or in other words, V q SMASH, we can minimize the NT F 1 and maximize NT F 2, as its demonstrated in the following example. In a fourth-order single-loop modulator where all the poles are at infinity, the maximum of V q would be 15. For the SMASH structure, this will result in V q SMASH = = 24 (3.11) which is larger than a regular single-loop. However, this is not the optimized situation since the NT F 1 is not minimized, in fact, it has been maximized. The extra multiplication by 2 is because there are two quantization errors in this structure. In another and more practical example, if we chose the maximum out-of-band gain of 1.6 for NT F 1 (the transfer function will be provided later in this chapter) and keep all poles of the NT F 2 at infinity, the single loop modulator will see maximum V q equal to 5.4. For the SMASH structure, however, this value would be V q SMASH = (1 1.6) 4 2 = 4.8 (3.12) which is smaller than the single-loop one, thus, the system is more stable. Note that in the above example, for both the signal-loop and the SMASH modulators,

60 45 the final NTF would have the OFBG of 6.4. More suppression in the first-loop OFBG can be made which results in better stability in the SMASH modulators. Another important aspect regarding the stability is the spread of the filtered quantization error at the input of the quantizer. As discussed in details in Chapter 2, the quantization error at the input of the quantizer, i.e. V q, is not uniformly distributed. In fact, it is the weighted sum of uniformly distributed PDFs. In the above calculations, it was assumed that for the SMASH modulator, the maximum of E 1 E 2 is 2 (each quantization error is normalized to 1). This is indeed true, but more important than its maximum value, is the probability of both of these quantization errors to be on their maximum or minimum. Similar to the single-loop modulators, we can calculated the probability of four consequent samples of the quantization error to be within a specified range. But for the SMASH modulators, not only four consequent samples of E 1 should be within the maximum range, but also, four consequent samples of E 2 should be within the same range. Hence, the probability of the both quantization errors being in that range is much smaller than the single-loop since these quantization errors are uncorrelated. This is an advantageous property over the single-loop modulators where only one quantization error determines the probability of being in the maximum or the minimum range. To verify this, a single-loop modulator with OFBG=5.4 and a SMASH modulator with OFBG=6.4 are simulated using Matlab. Both structures employ 9-level quantizers with V ref = ±0.5V. The maximum V q for the single-loop modulator is 4.4 and for the SMASH is 4.8 based on the above calculations. Theoretically, the spread of the quantization error of the SMASH modulator for infinite number of samples should become larger than the single-loop one. However, as discussed above, the probability of both quantization errors in SMASH to be within their

61 46 # of occurances V q of Single Loop # of occurances V of SMASH q Figure 3.7: The simulated histogram of the input of the quantizer (V q ) for both the SMASH and the single-loop modulators. maximum or minimum range for 4 consequent samples approaches zero rapidly. The simulated histogram of the V q is shown in Fig. 3.7 for both structures. This clearly illustrates that the SMASH structure has much smaller spread even though it has larger (theoretically) maximum V q. Also, for more clear illustration, the PDF of V q of the simulated modulators are shown in Fig The x-axis is the V q in millivolts and the y-axis is the probability of V q being greater than x-values. For example, the probability of V q > 0.2 for the single-loop modulator is 0.2 whereas for the proposed SMASH modulator is about 0.05 which is four times smaller.this comparison proves that although both modulators exhibit the same performance and noise shaping property, the SMASH modulator is more stable and able to process larger input signals [17]. Having two separate loops also provides additional flexibility to define the

62 SMASH Single Loop P( V q > X) V q (mv) Figure 3.8: The simulated one-sided PDF of the V q for the SMASH and the singleloop modulators. desired NTF with minimal coefficient spread, and makes the modulator less sensitive to coefficient variations. This is because any coefficient in this modulator only controls the location of one pair of poles and zeros, in contrast to the single loop modulator where a single coefficient variation affects all poles and zeros locations. This is found to be important especially when using a high order modulator with lowered out-of-band gain of the NTF to stabilize the modulator [23]. In such case with a single-loop modulator, a small variation in the modulator coefficients may shift the poles of the modulator too close to the signal band, seriously deteriorating the performance of the modulator [24]. It is also possible to cancel the first stage quantization error by choosing ST F 2 = 1 [25]. However, this mandates to extract the first stage quantization error, feed it to the second loop, and subtract the output of the second loop without any delay. This may not be feasible especially in multi-bit modulators where quantization error extraction requiters a DAC.

63 48-1 z E 1 X 0.5z 1-z z 1-z -1 Q 1 Y E 2 E 1 0.5z 1-z z 1-z -1-1 Q 2 Figure 3.9: Implemented 2+2 SMASH modulator. E 2 E 1 I Q2 3 I 4 Y 2 Figure 3.10: General form of the second loop of 2+2 SMASH structure System level design For the prototype IC implementation, the modulator shown in Fig. 3.9 was chosen. The first loop uses distributed signal feedforward topology to minimize the swing requirements of the integrators [26]. As discussed in the previous chapter, the feedforward reduces opamp/integrator linearity requirements by passing the main portion of the signal through the feedforward path and leaving only the quantization error to be process by the integrators. This specific design was chosen for simplicity, but any other delta-sigma loop may be used for the first loop, since there are no specific constraints on the signal and noise transfer functions of this loop. The delay in the signal feedforward path is due to non-zero delay from the quantizer and the feedback path, and it will result in less than 0.1dB in-band peaking in the signal transfer function. The modulator coefficients are chosen to

64 49 minimize output swing/slewing of integrators and to provide maximum out-of-band gain of 6.4. The noise transfer function of the first loop is NT F 1 = (1 z 1 ) 2 1 z z 2 (3.13) which results in OFBG=1.6 for the first loop. The second loop satisfies the criteria of (3.5) with all poles placed at infinity. An interesting property of this loop is that it satisfies (3.2) and (3.3) independent of its integrators transfer functions. This is mores clear by analyzing the general form of this loop shown in Fig It can be calculated that the signal transfer function of this loop follows ST F 2 = I 4(I 3 + 1) I 4 (I 3 + 1) + 1 (3.14) where I 3 and I 4 denote the third and fourth integrators transfer functions, respectively. In the same manner, the noise transfer function of this loop can be found as NT F 2 = 1 I 4 (I 3 + 1) + 1 (3.15) The calculated signal and noise transfer functions always satisfies (3.2) and hence the overall noise shaping would be in the form of (3.3), independent of I 3 and I 4. This property allows the use of very low opamp DC gain and coarse modulator coefficients in the second loop without severely affecting the noise shaping property of the whole modulator. In general, in a single-loop modulator, if all the signal feedforward coefficients (a 1,..., a N ) are equal to one, then the final signal transfer function would be unity. On the other hand, we know the transfer function from the a N alone to the output would be equal to NTF, since it is fed where the quantization noise is injected and they will see the same transfer function. With superposition, if all unity coefficients results in unity STF, and if a N results in NTF, if we chose a 0, a 1,...a N 1 = 1 and

65 SQNR (db) Input Amplitude (dbfs) 1.1 Figure 3.11: Simulated SNDR vs. input signal amplitude for the proposed 2+2 SMASH modulator using 9-level quantizers for both loops. a N = 0, then the signal transfer function of the second loop will always follow equation (3.2) regardless of loop characteristics. In this design, the noise transfer function of the second loop follows (3.4) resulting in the overall noise transfer function NT F Overall = (1 z 1 ) 4 (3.16) 1 z z 2 This transfer function shapes both E 1 and E 2, and has four zeros at DC and two poles at 1 2 ± 1 2 j. These poles will stabilize the modulator and reduce the output swing of integrators by reducing the out-of-band gain at the cost of increased in-band quantization error. However, the limiting factor in performance is more commonly set by KT C noise of the front-end sampling capacitors and DAC nonlinearity. The maximum achievable SQNR of this structure is shown in Fig This figure shows that the proposed structure can process input signal close to full-scale and that SQNR can reach over 85dB. Since the OFBG of the first loop is 1.6 and the second loop is 4, the maximum

66 51 input to the first stage quantizer is 4.8LSB/2. Hence, a 5-level quantizer is required for the loop stability. However, more quantization levels are preferred to suppress the power of quantization error and to enhance the maximum input signal range. Thus, 9-level quantizers are used for the first and the second loops. The use of multi-bit quantizers comes with one disadvantage, that is, the front-end DAC linearity becomes critical. To linearize the front-end DAC of the modulator, dataweighted averaging technique (DWA) is used [27]. Depending on the number of quantization levels and the DEM technique employed, this operation may take up to a half-clock period [28]. During this time, the in-loop digital addition should also take place. To reduce the DEM complexity and timing, and also to eliminate the need for fast digital adder in the modulator loop, the digital adder inside the modulator is replaced by additional DACs in the first loop [29] which it will be discussed later in this chapter. In the proposed structure, similar to any regular delta-sigma modulator, the linearity of the front-end DAC associated with the quantizer of the first loop is very important. By contrast, the front-end DAC associated with the second loop quantizer is not as critical. This is because the second loop processes only the first stage quantization noise. It will be shown later that this DAC which is associated with the second loop quantizer will only have a negligible effect on total noise and power. Also note that the output of the second loop is fed to the output of the first loop (as shown by a dashed line in Fig. 3.1). Therefore, any error generated in the second loop will be shaped by the first stage NTF. This advantageous property relaxes matching requirements of DACs in the second loop.

67 52 V DD Cc Cc Vo R R V o+ V b2 V cmo V in + V in V b1 opamp CMFB Figure 3.12: Opamp used for the integrators. 3.2 Circuit Level Design Operational Amplifiers As discussed in the previous section, eliminating all digital noise cancelation filters and employing fully analog transfer functions makes this structure less sensitive to opamp DC gain compared to the traditional MASH structure. MATLAB simulation results provided in Fig. 3.2 and Fig. 3.3 confirmed that 25dB opamp gain is sufficient to yield over 80dB SQNR. To add a safety margin for gain degradation due to feedback factor, and also for process and temperature variations, an opamp with 35dB open loop gain (based on transistor level simulation) is designed. Such low gain opamp would result in large phase and gain errors in the loop integrator [30]. Due to the robust modulator topology, the gain/phase error as well as coefficient variations can be tolerated to a significant level.

68 53 As shown in Fig. 3.12, a simple opamp with NMOS cascode transistors is chosen to satisfy the minimally required gain and large output swing. A single stage opamp with no additional gain boosting technique allows low-power/voltage operation and leads to a simple design. A continuous-time common-mode feedback is used to set the output common-mode of the opamps to a desired value. This single-stage opamp acts as a single pole system in the bandwidth of interest, hence no explicit frequency compensation is necessary. Any need for complex and costly two-stage opamps is entirely eliminated [31] Quantizers 9-level quantizers are used in this implementation. This will ensure modulator stability even for input signal close to full-scale. A switched-capacitor (SC) adder is used in front of each pre-amplifier to add the input signal, output of the second integrator and the reference voltages, as shown in Fig It is critically important to reset the pre-amplifier in order to minimize any memory effects from the gate-drain capacitance of the input transistors [32]. This is because this parasitic capacitor can store the decision dependent kick-back from the latched data and add it to the next input sample. To make sure to eliminate this effect, the input transistor pair is reset each period (ϕ 1 ). The operation of this circuit is as follows: In ϕ 1, the input signal is sampled on C Q1 while the comparator offset is sampled on C Q2. The gate-drain capacitance of the input transistor is also discharged. In the next phase, the output of the second integrator is connected to C Q2 while C Q1 provides the reference voltage generated from the resistor ladder. At the falling edge of ϕ 2, the comparator latches the pre-amplifier output (latches are not shown for simplicity).

69 54 V DD X V int2+ ϕ 1 C Q1 ϕ 2 ref(i) ϕ 2 C Q2 ϕ 1 ϕ 1 ϕ 1 Complementary SC Network V cm V bias ϕ 1 ϕ 2 Figure 3.13: Passive adder in front of the pre-amplifier. The same switched-capacitor adder is used for the second loop quantizer. However, the output of the second loop will not utilize the full dynamic range of its quantizer since the input of this loop is only the quantization error of the first stage, which is bounded by ± LSB 1 2 E 1. This is shown in Fig where the maximum allowable signal (-1.2dBFS) was applied to the modulator. This figure illustrates that the first quantizer employs all its levels to process the input signal and the filtered quantization error. However, the second quantizer only uses 5 levels to process its input which is only quantization error. Because this output is bounded within this region, the extra comparators (the top and the bottom two) can be safely removed to save power and design complexity. Consequently, capacitors associated with these comparators are also removed from the DAC at the input of the modulator, minimizing the impact of the additional DAC to the overall noise and power.

70 55 Quantizer 1 output # of occurance 10k 8k 6k 4k 2k Quantizer 2 output Time (µs) # of occurance 30k 20k 10k Quantizer output Figure 3.14: Outputs of the first and second quantizers. On the left, the actual wave forms are shown. The histograms of the waveforms are shown on the right Quantization Error Extraction As shown in Fig. 3.9, the input of the second loop is the quantization error of the first loop (E 1 ). This quantization error must be extracted accurately enough to maintain the error sources within the overall noise budget. The is, any error in the extracted quantization error would be shaped by the first loop transfer function. This is illustrated in Fig The error in the extraction of E 1 is modeled with an added random error E ext. This error is fed to the second loop, and after that it will be fed back to the first loop, after the quantizer. The output transfer function for this error is T F E ext = ST F 2 NT F 1 (3.17)

71 56 X L S1(z) L N1(z) E 1 Q 1 Y SMASH E + E 1 ext L S2(z) L N2(z) E ext E 2 Q 2 Figure 3.15: The error in the extraction of E 1 can be modeled as an added random error. which is suppressed by the first loop filter NTF. Since a passive adder is used in front of the quantizer, the input of the quantizer is not directly accessible. Hence, the first stage quantization error cannot be extracted in a conventional way (i.e. by subtracting the input of the quantizer from its output). In our implementation, the error extraction is done at the input of the second loop by drawing the signals from output of the first quantizer (Q 1 out ), input signal (X) and the second integrator output (V int2 ). In other words, the first stage quantization error is extracted by E 1 = Q 1 out V int2 z 1 X. (3.18) A conceptual block diagram is depicted in Fig where only the second and third integrators are shown for simplicity. It can be seen that the input signal (X) fed to the second loop is an advanced version of the signal fed to the first quantizer. Due to the oversampling nature (X(n) X(n + 1)) this timing difference will only result in a small amount of signal component in the second

72 57 X -1 z E 1-1 z 1-z -1 Q 1 Q 1_ out Y V int 2 0.5z 1-z -1-1 Figure 3.16: Extraction of the first loop quantization error at the input of the second loop. E 1 X 0.5z 1-z -1-1 Q 1 Y SMASH DAC A E 1 DAC B L s2 (z) L n2 (z) E 2 Q 2 Figure 3.17: Two DACs at the input of the modulator. One DAC is associated with the first stage quantizer (Q 1 ) and another is associated with the second stage quantizer (Q 2 ). loop, and it will negligibly affect the noise shaping property. In this prototype, all the summations are done at the input of the third and fourth integrators to avoid the need for extra active elements Front-end DACs As a result of replacing the in-loop digital adder of Fig. 3.1 with an adder outside the loop and extra feedback DACs shown in Fig. 3.9, two DACs oper-

73 SNDR= 66.93dB SFDR=70.1 db 0.1% nonliearity in DAC A PSD(dB) (a) 0 20 SNDR= 73.8dB SFDR=96 db 0.1% nonliearity in DAC B PSD (db) (b) Normalized frequency Figure 3.18: Effect of nonlinearity in front-end DACs. (a) σ=0.1% nonlinearity in DAC A (b) σ=0.1% nonlinearity in DAC B. ate in parallel at the input of the modulator. This is shown in Fig where DAC A and DAC B denote the DACs associated with the first and second loop output, respectively. Since DAC B only processes the quantization noise, it is less sensitive to nonlinearity compared to DAC A. In other words, DAC A carries the

74 SQNR (db) Mismatch between DACs (%) Figure 3.19: Simulated SNDR degradation due to the mismatch between DAC A and DAC B at the input of the modulator. signal, so any nonlinearity of this DAC will increase the noise floor and also produce tones. On the other hand, DAC B only carries the quantization noise, so its nonlinear spectrum is spread over the bandwidth and its effect is reduced by the oversampling ratio. This is evident in Fig where the assumed OSR is 16 and 9-level quantizers are used in the simulation. As illustrated in the figure, nonlinearity (σ=0.1%) in the DAC A produces large tones and results in significant loss of SNDR, dropping from 88dB (shown in Fig with ideal DACs) to 67dB. The spurious free dynamic range (SFDR) is also limited to 70dB. For DAC B, same level of nonlinearity results in 74dB SNDR without any significant spurious tones in the spectrum. Nevertheless, the increased noise floor might limit the performance in high accuracy applications. To suppress the nonlinearity of the front-end DACs, data-weighed averaging (DWA) was used for both DACs [27]. In this implementation, 3-bit and 2-bit DWAs are used for the first and second loops, respectively. Although the use of second set of DACs from the second stage removes the need for fast digital in-loop adder,

75 60 ϕ 2 Thermometer Input Log Shifter To DAC Thermometer to Binary Shift Latch En Binary Adder DFF DFF ϕ 1 ϕ 2 ϕ 1 Figure 3.20: The simplified schematic of the DWA used in this design. the gain matching between these DACs remain an important requirement. This is because any mismatch between the DACs will cause the first stage quantization noise to appear at the output unshaped. Fortunately, this matching accuracy is defined by the total capacitance (instead of each unit capacitance). The simulated matching requirements between DAC A and DAC B with 9-level quantizers are plotted in Fig This figure shows that a 0.5% matching between these DACs is sufficient to achieve over 12-bit performance. Such matching requirements is easily accommodated in modern CMOS processes. The proper timing of the DWA is critical to avoid any glitches in the data codes (DAC values). The simplified schematic of the DWA is shown in Fig The output of the quantizer is ready at the falling edge of ϕ 2. This output goes directly to the log-shifter and is rotated during ϕ 1. By the end of this phase, the outputs are shifted/rotated and are ready to drive the DACs in the next ϕ 2. Also, during the ϕ 1, the output of the quantizer is converted to binary and is fed to binary adders, which add the previous output to the current output. This binary

76 61 value is then delayed by means of two D-flip-flops (DFFs). The output of the second DFF which holds the data in ϕ 1 is used to drive the log-shifter for the next sample to avoid any sudden changes in the codes. This operation gives half-delay for the rotation, thermometer-to-binary conversion and for the summation which updates the pointer Switched-Capacitor Implementation of the Modulator The single-ended (to simplify illustration) implementation of the modulator is shown in Fig The IC implementation is fully differential. To avoid signal dependent loading on the references of the DACs, the sampling capacitors at the input of the modulator and the input DACs are separated. A 1pF sampling capacitor for the input signal, a total of 1pF capacitor for DAC A and a total of 0.5pF capacitor for DAC B are used at the input of the modulator. Both DACs activate in ϕ 2, leaving sufficient time for DEM operation to take place [33]. With thermal noise and matching requirements of the rest of the loop filter significantly suppressed by high-pass transfer function of the loop filter, the chosen capacitor values are more than sufficient for this design. The rest of the DACs in the modulator share the capacitors with other signals to minimize power dissipation and area. Because these capacitors are sufficiently small, they will not seriously impact the reference loading of these DACs. A specific type of bootstrapped switches [34] are used for sampling the input signal to guarantee linearity over a wide amplitude range. The bootstrapped switch is circled with a dashed line in Fig Except for the input of the modulator where DAC B is implemented with four capacitors (because the extra comparators were removed from Q 2 ), in the rest of the loop this DAC is implemented with eight capacitors to equalize the gain from

77 62 ref - ref + 8x X D A1 D A1 ϕ 2d ϕ 2d ϕ 1d ϕ 1d C DA1 C S1 ϕ 1 ϕ 2 C I1 X ϕ 1d ϕ 2d D B1 ref + ref - ϕ 1d C S2 ϕ 1 D B1 C S2 ϕ 2 8x ϕ 2 C I2 X ϕ 1 C Q1_1 ϕ 2 V ref ϕ 2 8x ϕ 1 2 Latch + Y SMASH ϕ 2d ϕ 1 ref - ref + 4x D B1 D B1 ϕ 2d ϕ 1d C DB1 D A1 ref - ref + D A1 8x -1 ϕ 1 C Q1_2 V CM To DACs A To DACs B 3-bit DWA 2-bit DWA ϕ 1d C S3 ϕ 2 ϕ 1d C S4 ϕ 2 ϕ V 2 ref ϕ 1 C Q2_1 ϕ 1 ϕ 2 ϕ 2d D A1 ϕ 1 D A1 C I3 ϕ 2d D A1 ϕ 1 D A1 C I4 V CM Latch ref + ref - 8x ref+ ref- 8x ϕ 2 ϕ 1 C Q2_2 X ϕ 1d ϕ 2d C S3 ϕ 1 ϕ 2 ϕ 2d ϕ 1d C S4 ϕ 1 ϕ 2 V CM 4x D B1 D B1 D B1 D B1 ref - ref + 8x ref - ref + 8x X ϕ 1d C S4 ϕ2d ϕ1 ϕ 2 Figure 3.21: Single-ended switched-capacitor implementation of the modulator (actual design uses fully differential implementation). the signals shared with this DAC with the gain of the signals shared with DAC A which employs eight unit elements. As discussed earlier, the quantization error of the first loop is extracted at the input of the third and fourth integrators. This requires that the output of the second integrator feed the input of third and fourth integrators. Since the second integrator also charges the capacitors of the first stage quantizer, the additional load would result in increased power dissipation in this integrator. To minimize this, different clock phases are used for the first stage quantizer and the second loop. As shown in Fig. 3.21, second integrator charges the capacitors of the first

78 63 Figure 3.22: Die photograph of the implemented IC. quantizer in ϕ 2, while it charges the capacitors of the second loop in ϕ 1. Although the output of this integrator does change between the two phases, due to switch charge injection and feedback factor, such small amount of error is comfortably tolerated by the second loop. In the end, it will appear as an added error to the first stage quantization error E Measurement Results The prototype ADC was fabricated in a 0.18µm CMOS process. Fig shows the die photograph of the prototype IC. The active area is mm 2. Fig shows a 32 kilo-samples of measured output spectra with 92kHz -6dB (of full-scale) sine-wave input signal. The 3rd and 5th harmonics are at -98dB and -94dB, respectively. Shown in Fig is the summary of measured SNR

79 64 20 F in =92 khz A in = 6 dbfs SNDR=70.6 db 40 PSD (db) Frequency (Hz) Figure 3.23: Measured output spectrum. and SNDR of the prototype chip as a function of input signal amplitude. The measured dynamic range, peak SNR and SNDR are 76.9dB, 75.6dB and 74.6dB, respectively. This prototype was tested at 1.2V analog and digital power supplies. Because a passive adder is used at the quantizer, large input signal near full-scale voltage (FS=1.2V) is effectively processed by the modulator. Analog supply down to 1V operate with minimal degradation. Table 3.1 summarizes the measured performance of the prototype ADC. The total power dissipated in the analog portion is 2.1mW, of which 1.2mW is dissipated in the opamps (480µW in the first integrator), and the rest is dissipated in quantizers and resistor ladders. The digital power includes clock generators and clock buffers, DWAs and both quantizer latches.

80 65 70 SNDR SNR SNR, SNDR (db) Input Amplitude (dbfs) 1.5 Figure 3.24: SNR and SNDR versus input amplitude. 3.4 Summary A new multi-loop delta-sigma modulator is presented which benefits from multi-loop stability and combines it with relaxed circuit requirements of the singleloop modulators. The unique transfer function at the input of the quantizer results in lowered quantization noise at this node and hence improves the stability. Moreover, having two-separate loops makes the design much simpler. To demonstrate the efficiency and the key concept of this structure, a 2+2 SMASH modulator is implemented and measurement results are provided. It is shown that the achieved performance with very low gain opamps is comparable to the traditional MASH structure utilizing costly high gain opamps. This important advantage over the traditional multi-loop architectures allows low-voltage operation and low-power

81 66 Table 3.1: Performance Summary-Sturdy MASH Supply Voltage 1.2V Sampling Frequency 20MHz Oversampling Ratio 16 Dynamic Range SNR SNDR SFDR Power Dissipation Technology 76.9dB 75.6dB 74.6dB 89.7dB 2.1mW Analog 1.1mW Digital 0.18µm 2P5M CMOS Active Area 1.92 mm 2 dissipation. The passive switched-capacitor adder and modified error extraction, together with a unique modulator topology, enables large input signal to be processed with robust stability.

82 67 CHAPTER 4. EXTENDED DYNAMIC RANGE SINGLE-LOOP DELTA-SIGMA MODULATORS In the previous chapter, a new multi-loop delta-sigma modulator was presented which provided high stability with relaxed circuit requirements. This chapter presents a new single-loop delta-sigma modulator with extended dynamic range. It employs an auxiliary multi-bit quantizer which processes the quantization error of the main quantizer. Unlike the SMASH structure, this structure aims to cancel the quantization noise of the auxiliary quantizer in order to provide better stability. 4.1 Quantizer Saturation in Σ Modulators In any regular single-loop delta-sigma modulator, in steady-state, when the sum of the input signal and the filtered quantization error exceeds the linear range of the quantizer, the modulator enters saturation. This sum is shown with V q in Fig. 4.1 where L S and L N denote the signal and noise loop filters, and E i denotes the quantization noise of Q i. As the input signal increases, V q will increase and ultimately saturates the modulator. The lost information due to the quantizer saturation will not be fed back to the input of the modulator, hence, the DAC is unable to subtract this data from the input signal. Thus, an extra amount of the input signal will enter the loop in the next sample. This extra amount will lead to another quantizer overload, and this cycle repeats and eventually the modulator saturates. As discussed in Chapter 2, increasing the number of quantization levels will only minimize the

83 68 X L S(z) E 1 L N(z) V Q Q 1 Y SL V DAC DAC Figure 4.1: A single-loop delta-sigma modulator. quantization error, allowing somewhat larger input signal to be processed in the loop. However, the fact that quantizer saturates when its input exceeds its linear range holds true, regardless of the loop filter characteristics and the number of quantization levels employed. 4.2 Extended Dynamic Range Single-Loop Modulator The key idea of the proposed structure is to recover the lost information due to the quantizer saturation and feed it back to the loop [35]. This is done with an auxiliary quantizer as illustrated in Fig This quantizer will process the quantization error of the main quantizer and feed it back to the loop in the digital domain. The fundamental operation of this quantizer can be well understood by analyzing it in two different cases. First, if the sum of the input signal and the filtered quantization error is within the linear range of the first quantizer, both quantizer work in the linear region, as illustrated in Fig In this case, removing the main quantizer and replacing it with the auxiliary quantizer will have no effect on the loop. However, if the sum of the input signal and the filtered quantization noise

84 69 X L S(z) L N (z) E 1 Q 1 E 2 Y Q 2 DAC Figure 4.2: The proposed extended dynamic range structure. The added auxiliary quantizer injects E 2 and cancels E 1 via the in-loop digital summation. +Vref Q1 -Vref +Vref Q2 -Vref Figure 4.3: When the sum of the input signal and filtered quantization noise are within the linear range of the first quantizer. exceeds the linear range of the main quantizer, the extra amount which it will show itself as added quantization noise to E 1 will be fed to the second quantizer. As long as this extra amount is within the linear range of the second quantizer, the loop will be stable. This is because the second quantizer will process the lost information due to the main quantizer saturation and feed it back to the loop in digital domain. This case is shown in Fig. 4.4.

85 70 +Vref Q1 -Vref +Vref Q2 -Vref Figure 4.4: When the sum of the input signal and filtered quantization noise exceeds the linear range of the main quantizer. This configuration will result in cancelation of E 1 by the second path created by the auxiliary quantizer and the introduction of smaller quantization error E 2, if Q 2 uses more quantization levels. In other words, the first quantizer injects E 1 into the loop, however, this quantization error is also fed to the auxiliary quantizer which introduces E 2. Hence, the output of the auxiliary quantizer includes both E 1 and E 2. This output is then subtracted from the output of the main quantizer, which in ideal case, results in complete cancelation of E 1. In the case of non-ideal cancelation of the first stage quantization error (E 1 ), the output of the modulator can be written as Y = ST F X + NT F E 1 NT F (E 1 + E 2 + σ E1 ) (4.1) where σ E1 denotes the leakage resulted from non-ideal cancelation of E 1. The simplified final output can be written as Y = ST F X NT F (E 2 + σ E1 ). (4.2)

86 71 An interesting property of the proposed modulator is that any error in the cancelation of E 1 will be suppressed by the modulator loop, similar to the SMASH structure where the imperfection in extraction was shaped by the first loop filter. Hence, it does not impose any burden on the analog loop filter. As a simple example, if the rms power of σ E1 is equal to the rms power of E 2, only 3dB SQNR degradation will occur. This is an extreme case and in practical situations, this leakage will be negligible. This is in contrast with traditional MASH structure where a near perfect cancelation is required which results in power hungry analog loop filter. Because E 1 is being canceled, there is no need to use a multi-bit quantizer for it, i.e. a binary or 3-level quantizer will suffice. Instead, because the modulator loop will only see E 2, the auxiliary quantizer can be chosen to be a multi-bit quantizer [36]. The appearance of E 1 due to a non-perfect cancelation will act like an added random noise and it will not seriously affect the performance. As long as the sum of the input signal and the filtered quantization error is in the linear range of the main quantizer, the input of the auxiliary quantizer is bounded to ± LSB 1 2. When this voltages exceeds the linear range of the main quantizer, the overloaded voltage will be fed to the auxiliary quantizer. Thus, in this case, the input of Q 2 contains two parts. First, is the bounded ± LSB 1 2 of the main quantizer, and second, is the overloading signal. With further increase in the input signal, the overloading signal portion will increase until it saturates Q 2. The saturation of Q 2 will happen roughly at the 2V ref LSB 1 above the linear range of the first quantizer, greatly increasing the dynamic range of the modulator. A similar concept has been recently applied to 0-N MASH structures [37]. However, in this structure, the quantization extraction is done at the front-end and its cancelation is done outside the loop via digital filters. Such cancelation requires very high DC gain opamps and accurate modulator coefficients to match their digital

87 72 X 0.5z 1 z z 1 z 1 1 z 1 z 1 Active adder E 1 Q 1 Y EX E 2 Q 2 Figure 4.5: The block diagram of the implemented third-order modulator. counterparts, resulting in power hungry analog loop filter. Also, the switches required for canceling the quantization error demand high linearity since they are located at the front-end of the modulator. But in the proposed structure, this extraction is done at the back-end where high gain of the loop filter will greatly suppress the requirement of these switches. This is an important design criteria since the input of this structures can be beyond the full-scale of the references. It is of critical importance to distinct between the proposed structure and the traditional two-step architectures described in [38] and [39]. In contrast to these structures where an improved SQNR was achieved by conventional two-step quantization using residue amplification (minimizing the quantization error), in the proposed structure the enhanced SQNR is achieved by allowing larger input signals to be processed by the loop, without any residue amplification. For this, note that in delta-sigma modulators, reducing the in-band quantization noise comes with a cheap price of increasing the OSR. For example, in 2nd order and 3rd order modulators, doubling the OSR will increase the SQNR by roughly 15dB and 21dB respectively, whereas in Nyquist converters, it results in only 3dB enhancement. Nevertheless, the performance of DSMs are often not limited to quantization noise,

88 73 but to the thermal noise of input sampling network. Using residue amplification in the two-step quantizer will only further decrease the quantization noise, but the thermal noise limitation of the input sampling path remains the same and limits the overall performance of the system. In contrast, increasing the allowable signal range can significantly enhance the signal power to the thermal noise of the frontend sampling, resulting in either smaller capacitors (for achieving same SNDR but reduced power) or the same size capacitor (and increased SNDR). Another difficulty of the residue amplification technique lies in the complicated front-end LSB and MSB DACs and the need of an extra opamp to amplify the residue. In the proposed structure, the front-end DAC is similar to that of the regular single quantizer modulators, and also simple passive summation can be used to extract the quantization of the main quantizer. 4.3 Circuit Design The implemented modulator is a third-order low-distortion structure with a complex pair of zeros in the signal band. The modulator structure is shown in Fig The modulator coefficients are chosen to maximize the feedback factor of the active-adder which is used to sum the loop signals and also to improve the overall stability Operational Amplifiers Due to the fact that the cancelation of E 1 in the modulator loop is processed after the main quantizer, the opamp DC gain requirements of this modulator is

89 74 Sig ϕ 2 +int 3 ϕ 1 ϕ 2 C S-AA C q1 ϕ 2 +int 1 ϕ 2 C S-AA ϕ 1 ϕ 1 int 2 ϕ 2 ϕ 2 C q2 V CM - 1c C q3 ϕ1c + - To Integrator1 DAC C q4 ϕ 1 ϕ 2 ϕ 1c Figure 4.6: The active-adder and the quantizer timings (several switches are removed for simplicity). similar to that of the traditional single-loop modulators. For this design, simple opamps with NMOS cascode transistors are chosen to satisfy the minimum gain requirement of 30dB and large available output swing as shown in Fig Having reduced number of transistors between the power supply rails enables low-voltage operation of the opamps. Continuous-time common-mode feedback is used to set the output common-mode of the opamps to the desired value. In the designed 3rd order low-distortion structure [10], 3 integrators and one active-adder has been implemented.

90 Active-Adder An active-adder is used to add the signals of the loop and feed it to the quantizer. These signals are the output of the first, second and the third integrators. A capacitor is shared to sample the outputs of the first and second integrators in attempt to maximize the feedback factor. The third integrator drives a capacitor in ϕ 1 which will be flipped around in ϕ 2 to form the feedback capacitor. The simplified active-adder and its quantizer timing is shown in Fig. 4.6 where a single-ended implementation is shown for simplicity (the actual implementation is fully-differential). The output of the active-adder feeds both quantizers via switched-capacitor networks. The shared switched-capacitor network shown in this figure is for simplicity and the actual design uses separate capacitive networks for each quantizer. Since this structure can process very large input signals, the input signal is not fed to the active-adder to avoid large swing requirements in the opamp. Instead, it is directly added to the switched-capacitor input of the comparators. This will removes the signal component from the active adder and hence it will only process the filleted quantization noise. The switches used for the input feedforward path are complementary MOS switches with boosted clock Quantizers A 3-level main quantizer and a 9-level auxiliary quantizer both operating with 1.2V reference have been used for this design. The first quantizer (Q 1 ) will quantize the output of the loop filter at the end of ϕ 2. The quantization error of this quantizer is then fed to the auxiliary quantizer by the rising edge of the ϕ 1.

91 76 V DD +V DA C V cm Q 1 ϕ 1c C Q1 ϕ 2 V AA ϕ 1c C Q2 ϕ2 ϕ2 R R Complementary SC Network CM -V DAC ϕ 2 V bias ϕ 1 ϕ 2 V ref ϕ 1c Figure 4.7: SC-DAC at the input of the second quantizer to extract E 1. A simple switched-capacitor network has been used at the input of the preamps of the second quantizer to perform this quantization extraction, as shown in Fig This data is then latched at the falling edge of ϕ 1c (latches and the input signal sampling path are not shown for simplicity). In this figure, V AA represents the active adder output In-loop Digital Summation and DACs The high speed requirement of the in-loop digital adder and the data-weighted averaging circuit (DWA) can be problematic and power consuming because both should operate between the falling edge of ϕ 1c and the rising edge of ϕ 2 to operate the frond-end DAC at ϕ 2. To avoid this addition, one can replace it with two separated DACs at the input of the modulator [40]. As discussed in the previous chapter, this technique demands good matching between the gain of the two separated DACs to minimize the quantization noise leakage. In this design, since

92 77 Q 2 8 zeros 4X0 4X0 D8 D7 D6 D5 D4 D3 D2 D1 Q 1 = 0 Q 2 4 zeros 4X0 D8 D7 D6 D5 D4 D3 D2 D1 4X1 4 ones Q 1 = 1 Q 2 D8 D7 D6 D5 D4 D3 D2 D1 4X1 4X1 8 ones Q 1 = 2 (a) (b) (c) Figure 4.8: Fast digital in-loop addition in thermometer code by multiplexing. the first quantizer is only 3-level, a simple array of digital multiplexors are used to directly add these two outputs in thermometer code. Thus, enabling the use of a single DAC at the input to avoid any leakage/mismatch problem. Note that summing these two thermometer outputs results in 17-level thermometer output. The output of the first quantizer selects 3 possible states. If Q 1 = 0, then the 8 thermometer outputs of Q 2 will start from lowest code to code 8, and above that there will be 8 zeroes. If Q 1 = 1, the first four codes will be 1, and then the output Q 2 will start from code 5 to 12 and the rest will be zeros. If Q 1 = 2, then the first 8 codes will be one and the rest would be from Q 2. This is illustrated in Fig. 4.8 where 8 zeros and ones are factored in groups of 4 for simplicity of drawing. This technique will significantly reduce the digital hardware complexity by avoiding output conversion to binary, subtracting them and reconverting it to thermometer code to be used for the DWA placed afterwards. The multiplexing in this structure can be done very fast since the control pins of the multiplexes are ready as soon as the main quantizer has resolved. Hence, as soon as Q 2 resolve, it

93 78 will be directly passed through the MUX tree. Switched-capacitor DAC is used at the front-end of this modulator. To avoid possible signal dependent loading on the DAC references, separate sampling capacitors are used. The input is sampled via a CMOS switch with boosted clock to enable over full-scale sampling. These switches are placed in a shielded deep NWELL to minimize substrate noise leakage. 4.4 Measurement Results The prototype ADC is fabricated in a 0.18-µm 2-Poly 5-Metal CMOS process. Fig. 4.9 shows the die photo of this IC. The active area is 0.85mm 2. Fig and Fig show a 32k-sample measured output spectra with 115kHz 0dBFS and +3.7dBFS sine-wave input signals, respectively. The 3rd harmonic is at -85.4dB for the +3.7dBFS case. The second harmonic in both figures are from the asymmetric traces on the test board. Further increasing the input signal will cause larger tones due to non-linearity of the sampling switches which will limit the achievable SNDR. For a comparison between the proposed structure and the traditional modulator, an extra option is implemented in the prototype IC to disable Q 1 and use Q 2 as the main quantizer of the modulator. In other words, this option allows configuration of the traditional 3rd order modulator with 9-level quantizer. The measured SNR and SNDR of both structures as a function of the input signal amplitude are shown in Fig It is clear from this figure that the proposed structure achieves over an extra bit (about 6.5dB) of SNDR by processing larger input signal, made possible by adding only a simple 3-level quantizer. Table 4.1 summarizes the measured performance of the prototype ADC. The

94 79 Figure 4.9: Die photograph. 0 Fin=115kHz Vin=0dBFS 20 SNDR=72.3dB PSD(dB) Frequency(Hz) Figure 4.10: Measured spectrum with 0dBFS input signal. total power dissipated in analog part is 3.3mW where 2.28mW of this power is dissipated in the opamps and the rest is dissipated in the quantizers, preamps and the resistor ladders. Further power optimization is possible in both digital and

95 Fin=115kHz Vin=3.7dBFS SNDR=75dB 40 PSD(dB) Frequency(Hz) Figure 4.11: Measured spectrum with +3.7dBFS input signal SNDR Extended SNR Extended SNDR Normal SNR Normal SNDR.SNR(dB) Input Amplitue (dbfs) Figure 4.12: SNDR and SNR versus varying input signal amplitudes for the proposed and traditional structures. analog parts; however, this prototype ADC was primarily intended to demonstrate the feasibility of the proposed structure.

96 81 Table 4.1: Performance Summary-Extended Dynamic Range Supply Voltage Sampling Frequency 1.2 V 40MHz Oversampling Ratio 16 Dynamic Range Peak SNDR Peak SNR Power Dissipation Technology 77.2dB Proposed 69.2dB Traditional 75dB Proposed 68.5dB Traditional 76.1dB Proposed 69dB Traditional 3.3mW Analog 1.6mW Digital 0.18-µm 2P5M CMOS Active Area 0.85mm Summary A new dual-quantizer single-loop modulator is proposed and the details of the design are discussed. This structure can tolerate input signals beyond the full-scale of the references of the modulator. The quantization error subtraction is done at the back-end of the modulator and hence the analog loop requirements

97 82 are relaxed. Moreover, employing a 3-level main quantizer allows simple passive quantization error extraction and enables fast in-loop addition. The combination of these features leads to significantly improved stability with minimal additional hardware.

98 CHAPTER 5. NOISE-SHAPED INTEGRATING QUANTIZERS A new integrating analog-to-digital converter is presented and its properties are discussed. With a small modification to the discharging phase of the traditional single/dual slope converter, first-order quantization noise is achieved. This structure can be used as a stand alone ADC or as the quantizer in a delta-sigma loop. It will be shown that integration of this structure with delta-sigma modulator can be very simple and effective with no need for an extra active element. 5.1 Integrating Quantizers Traditional Dual-Slope ADCs The concept of the time-based quantizer is similar to that of the dual-slope ADCs. In a traditional Dual-Slope ADC, in the sampling phase, the input signal is sampled on the integrating capacitor of the opamp as shown in Fig The sampling is often done via a resistor in continuous-time fashion, but it can be also done in switched-capacitor way. For a continuous-time sampling, the output of the integrator at the end of the sampling phase will be V DS = 1 Ts V in(t) dt (5.1) RC 0 where V DS is the output voltage of the integrator and T S is the sampling period. Note that for positive inputs, the output will be negative. For a fixed input signal

99 84 ϕ r X ϕ D ϕ s R C V DS V ref Figure 5.1: The traditional dual-slope ADC. (i.e., DC), the output value is directly proportional to input amplitude, resulting in V DS = V in T s RC (5.2) knowing that R, C and T s are fixed values. In the discharging phase, the sampling resistor will be connected to a fixed bias voltage and discharges the integrator to the zero crossing. This zero crossing is detected by a comparator. As soon as the output of the comparator detects the zero crossing, the discharging phase is over. During this phase, a fast clock is fed to a digital counter which increments during the discharge. The vale stored on this digital counter at the end of the discharging phase is the quantized representation of the analog input. The integrator is reset in ϕ r to remove any offset or memory from the previous sample. Fig. 5.2 illustrates the operation principle. Fig. 5.3 is provided to illustrate the similarity between the time-based quantization and its voltage domain counterpart. In this figure, LSB T and LSB V denote the time domain and voltage domain LSBs, respectively. Each edge of the counting clock acts as the reference of the comparators in a regular flash ADC. If the zero

100 85 ϕ V 2 -V s DS D ϕ r s ϕ ϕ V 1 t D2 D1 t Figure 5.2: The timing of the traditional dual-slope ADC for two different DC input signals. In this example, D 1 =3 and D 2 =7 assuming counting is done at both rising and falling edges of the counting clock. crossing occurs slightly before this edge, then the quantization error will be close to zero on the negative side. If it happens right after this edge, the quantization error would be zero and positive, and it increases as the zero-crossing moves towards the middle of the time interval between the edges. It is also possible to view to quantization error as a uniformly distributed random error between 0 and LSB, but this definition will not be useful for the next section describing bi-directional discharging. Although the discharging is always done with a fixed-slope, the sampling would be different for different input frequencies. For higher frequency input signals, the value stored on the integrator will be different. This can be simply evaluated using (5.1) yielding V DS = 1 Ts A cos(wt) dt = 1 Asin(wT s ) RC 0 RC w (5.3)

101 86 + LSBV LSB V 2 2 X Counting Clock q E + LSB V 2 LSB T 2 + LSBT 2 LSB V 2 Figure 5.3: Similarity between the time-domain and voltage-domain quantization. Each counting edge is similar to a comparator reference. which will result in a Sinc transfer function shown in Fig This is a useful property for a stand-alone ADC, since these types of ADCs are often used for DC or very low frequency applications and it provides an inherent anti-aliasing filter. However, to achieve N bits of quantization resolution, 2 N clock cycles is required (assuming 50% duty-cycle for sampling and discharging and the counting is done at both rising and falling edges). In other words, the counting clock speed should be 2 N f s. Because of such high speed requirements of the digital circuitry, the application of these types of converters were limited to DC and very low frequency measurements. In next section a simple technique will be presented which will significantly reduce the speed requirements of the counting clock.

102 Amplitude (db) Normalized input frequency (f /f ) in s Figure 5.4: Signal transfer function of the dual-slope ADC. The input amplitude is normalized to 0dBFS Noise-Shaped Dual-Slope ADCs With a small modification in the discharging phase of the traditional dualslope ADCs, a first order quantization noise shaping can be achieved [41]. The input signal is sampled similar to the traditional case. However, in the discharging phase, the discharging will continue through the zero-crossing of the comparator and it will be terminated at the next edge of the counting clock. The value stored on the integrating capacitor at the end of the discharging phase will be LSB 2 minus the quantization error of the current sample. The next input signal will be added to this value and the reset phase is eliminated. The modified discharging phase is illustrated in Fig Bottom axis shows the quantization error of all possible zero crossings. Since in this discharging method, the termination of the discharge always occur after the zero crossing, the stored value error is always negative. As opposed to the ideal case where the quantization references are at the middle of each pulse (illustrated in Fig. 5.3), in this case, the references are the edges of the

103 88 ϕ V 1 -V s DS D s ϕ ϕ t Counting Clock q E t t Figure 5.5: The modified discharging phase. The value stored on the integrator at the end of this phase is LSB 2 minus the quantization error of the current sample. counting clock, resulting in LSB 2 offset in the stored quantization error. Hence, the final stored value of the integrating capacitor would be the negative quantization error of the current sample plus LSB. Interestingly, the negative polarity of the 2 stored quantization error is desired to form high-pass quantization noise shaping, and the LSB 2 will result is a fixed offset. This offset will slightly reduce the dynamic range of the ADC and in most of the cases no compensation is necessary. However, if dynamic range is of an important concern, it can be easily canceled by injecting half LSB during the input sampling phase. As mentioned above, the negative polarity of the quantization error can be used for shaping the quantization error. The digital output of this ADC contains the signal plus the quantization error of current sample minus the shifted previous one D(n) = X(n) + q e (n) q e (n 1) + LSB 2 (5.4)

104 89 where D(n) is the digital output of the n th sample. Taking the Z-Transform and eliminating the DC offset, the final digital output will be D(z) = X(z) + (1 z 1 )q e (z). (5.5) Above equation shows a first-order high-pass quantization noise shaping is achieved. The effectiveness of this quantization noise shaping can be analyzed by looking at the power of the in-band quantization error. For high OSR values, the noise transfer function (NTF) would be approximately NT F (f) 2 = 2πf (5.6) and hence, integrating above value over the band of interest will result in σ 2 q ns = 1 2 OSR 0 2πf S e (f) df (5.7) where S e (f) is the single-sided power spectral density (PSD) of the quantization noise, and is equal to σ 2 q = LSB2 6. Evaluating (5.7) will result in σ 2 q ns = The improvement due to the noise-shaping will be π 2 6 (OSR) LSB2 (5.8) 3 6 σ 2 q ns σ 2 q = π 2 6 (OSR) 2 (5.9) which shows 6dB relative improvement for each doubling of the OSR (starting from -2.1dB for OSR=1). For example, for OSR=8, the improvement will be 3*6-2.1=15.9dB. To achieve 12-bit performance at this OSR, the counting clock for the traditional dual-slope should be 1450f s and for the proposed structure will be 360f s which is 4 times slower (assuming counting is done at both rising and

105 90 falling edges). Next section describes a technique that can reduce the counting clock requirement by two. 5.2 Bi-Directional Dual-Slope Noise-Shaped ADC So far, the idea of the dual-slope was based on charging in one direction (up) and discharging it in the opposite direction (down). The problem with this scheme is that, if the input signal falls below the input common-mode of the opamp, the signal will be charged in the opposite direction and the output of the integrator will be below the comparator reference. Hence, there would be a possibility of saturation without careful common-mode biasing. Also, in some structures, such as delta-sigma modulators, during the start-up time, the input to the quantizer is not well defined. Hence, using the uni-directional discharging can be problematic. A simple modification can be made to fix these issues: employing bi-directional discharging by comparing the differential output of the integrator with the commonmode voltage. If this voltage is above the common-mode voltage, it implies the differential output should be discharged, and if it is below the common-mode voltage, it should be charged. From here on, we use the definition of discharge up and discharge down to address the discharging and charging of the integrator, respectively. The single-ended implementation and its timing diagram are shown in Fig The output of the integrator is compared with the V CM and depending on the decision, it will be discharged up or down. In this fashion, one extra bit is achieved (polarity) which will result in halved counting clock speed. Also, the swing requirements of the opamp is halved. The sensitivity to the input signal common-mode and input common-mode of the opamp is also removed. However, there is an important design consideration for the bi-directional

106 91 C X Dir. ϕ1 R V DS V ref + V CM Vref Dir. Timing Control -V DS Discharge Discharge Sample Sample Sample V CM Figure 5.6: The bi-directional noise-shaped integrating quantizer. t case that needs to be addressed. As discussed earlier, the modified discharging will result in half LSB shifted quantization error. In the case of uni-directional, this would not be important since it will be always fixed offset. But for the bidirectional discharging, depending on the signal polarity, this shift can be positive or negative. This will result in a signal dependent offset and it will cause tones to appear at the output. Since the quantization error stored for the n th sample will be subtracted from the (n+1) th sampled, the signal dependent offset can be corrected in the next sampling phase. In other words, after the signal is quantized, the next input signal will be sampled. During this sampling, the signal dependent offset can be corrected/canceled, as shown in Fig In this figure, the input signal is sam-

107 92 Vref V ref + Dir. ϕ 2 N R C Dir. X Dir. ϕ 2 R V DS V ref + V CM Vref Dir. Timing Control ϕ 1 Figure 5.7: The compensation of the signal dependent offset in bi-directional NSIQ structure. pled during ϕ 2 and discharged during ϕ 1. The offset correction is also performed during ϕ 1 to cancel the offset of the previous sample. If the total number of the physical bits (not including oversampling effect) resolved is N +1, meaning the discharging has 2 N edges in the discharging period, the charging/discharging resistor will discharge 2 N LSB in this period. To add or subtract LSB/2 in the same time (assuming the same duty-cycle for sampling and discharging), the compensation resistor value should be 2 N+1 R. The direction of the references for compensation network, as illustrated in this figure, is opposite of the discharging one Counting-Clock Jitter Generally, continues-time sampling of the input signal or discharging of the DAC is more prone to clock jitter than the switched-capacitor counterparts. The effect of the clock jitter for the sampling of the signal and the DAC has been analyzed in many literatures [42] [44] and can be easily applied to this structure. The

108 93 focus of this of this discussion is the jitter in the high-speed counting clock, which as later discussions will show, it can have a critical effect on the final performance. For the following analysis, we assume that the signal is sampled without any clock jitter, and each edge of the high speed clock has an independent non-accumulative phase noise with a zero mean Gaussian distribution [45][46]. In the uni-directional noise-shaped integrating quantizer, the maximum output of the opamp will be roughly equal to the maximum input signal magnitude (V F S ), without using scaling. The timing of such structure was shown in Fig In the discharging phase, any error on the first edge after the zero-crossing will directly affect the discharging time. Although this error seems to be only as the quantizer error, i.e. error in the comparator decision level in the traditional flash ADC, but in this case, this error will be also affect the inherent DAC which is the discharging time. As an example, in Fig. 5.8, assume the first sample of signal X(n) is sampled without any error. In the discharging phase, however, the first edge after the zero-crossing has jitter and it comes t j later than its ideal case. Hence, the discharging pulse D out (t) will be exactly t j longer than its ideal case. This will cause an error in the quantization noise equal to E j = t j I dis C (5.10) This error (E j ) along with the quantization error q e (n) will be subtracted from the next sample of the input signal. Hence, the value stored on the integrating capacitor of the quantizer before the next discharging will be V DS = [X(n + 1) E j (n)] q e (n) (5.11)

109 94 -V DS ϕs ϕd X(n) q (n 1) e ϕ S [X(n + 1) E (n)] q (n) j e E j q ( n) + E (n) e j t t D out t j D out (t) Figure 5.8: The jitter in high-speed counting clock. Any error in the counting clock will be translated to voltage and added to the next input signal sample. and the final digital output will be D out (z) = X(z) + (1 z 1 )q e (z) z 1 E j (z). (5.12) From equation (5.12) we can observe that the error in the discharging time originated from the counting clock uncertainty is multiplied by the discharging slope and added to the signal. For the modulator, this error is undistinguishable from the input signal, and hence it will be equivalent of adding an error directly to the input signal. For this reason, the error will directly appear at the output, and due to its random nature, it will increase the in-band noise floor. The most effective way to reduce this error is to reduce the discharging slope. One may suggest to increase the integrating capacitor of the quantizer to reduce the discharging slope. But in this method, not only the load of the opamp has been increased, but also the noise induced jitter will remain the same. For example assume that we double the integrating capacitance, hence the maximum input

110 95 signal will be halved at the output of the integrator. However, the discharging current remains the same since it needs to discharge Q = 2 C V F S 2 in the same time. The final error due to the clock jitter will be halved due to the reduced discharging slope. But this error is subtracted/added to the next sample of the input signal which is also halved because of doubling the integrating capacitance. Hence, no improvement in sensitivity to clock jitter will be achieved in this fashion. In other words, both signal and jitter induced error are scaled with the same factor. However, in the proposed bi-directional discharging technique, the effect of the counting clock jitter is halved. This is because the maximum discharging will be half of that of the traditional case. The reduced output swing, resolving an extra bit and reduced sensitivity to the clock jitter makes this structure superior to the traditional uni-directional one. If this ADC is used as the quantizer in a delta-sigma loop, then the effect of the counting clock jitter will be suppressed by the high gain of the loop filter and will not be a critical design consideration. In this case, the jitter of the counting clock will be shaped by the loop filter (not including the added shaping by the quantizer). For example, in a second-order loop filter which also uses the proposed quantizer, the overall quantization noise shaping order will be three and counting clock jitter shaping order will be two Comparator Non-Idealities The comparator which detects the zero crossing circuit can also add noise to the system. The analysis of the comparator noise is similar to the comparatorbased circuits [47] [48] with one main difference; the reference and the discharging slope are fixed. The fixed portion of the comparator delay (t cf ) acts like an added

111 96 -V DS ϕs ϕd X(n) q (n 1) e ϕ S X(n + 1) [q ( n ) + q ( n) ] e tc ϕ D t cn t q (n) + q (n) e tc Dout-ideal = 3 Dout-ideal = 4 t Dout-tn = 4 Dout-tn = 3 Figure 5.9: The comparator noise when affecting the output code. The effect is stored in both analog and digital and will be compensated in the next samples. offset and can be fixed in both digital and analog domains. The delay due to the noise (t cn ) will act similar to the comparator noise in a regular flash ADC. If the zero crossing happens around the middle of the clock pulse, the comparator noise will have no effect. This is because the discharging will stop at the next edge of the counting clock, not with respect to the output of the comparator. As long as comparator triggers sometime between the clock edges, the discharge time is fixed. In the other case, if the crossing happens very close to the counting clock edge, because of the comparator noise the zero crossing might be moved to the next edge. In this case, there will be an extra error stored on the integrator. However, the digital code has also been changed and includes this error. Since the final digital output is tracking this error and the value is also stored and will be subtracted from the next sample, it will be averaged and first order shaped. A simple example is shown in Fig. 5.9 where a decision uncertainty of the comparator

112 97 ϕ 2 C SQ2 Active Adder C IQ X H(z) ϕ 1 ϕ 2 C SQ1 ϕ1 ϕ1 ϕ 2 ϕ 2 Y ϕ 2 Q 1 DAC Figure 5.10: A typical low-distortion structure. At the end of the ϕ 2 the output of active-adder has added the signals from different loop filter nodes and the input signal and its ready to feed it to the quantizer. pushes the zero-crossing to the next edge. Hence, the digital output will be equal to 4 whereas in ideal case it should have been 3. However, the added comparator noise is subtracted from the next signal sample, and hence, as shown in the figure, the next digital code will compensate for the excess in the previous one. 5.3 Noise-Shaped Quantizer in a Delta-Sigma Loop In delta-sigma modulators, the quantizer is placed after the loop filter to digitize the output(s) of the loop filter. In the case of low-distortion structures, often an active-adder is used to sum the signals of the loop filter and feed it to the quantizer [10]. For example, in a second order low-distortion structure, the active-adder is used to sum the input signal, the output of the first integrator and the output of the second integrator. For now, assume this summation is done at ϕ 2 and the front-end DAC works in the next ϕ 2, giving the quantizer a half-delay (ϕ 1 ) to operate. A general loop filter is shown in Fig where H(z) is the loop filter transfer function. By the end of the ϕ 2, the output voltage of active

113 98 ϕ 2 C SQ2 C IQ X H(z) ϕ 1 ϕ 2 C SQ1 ϕ1 ϕ1 ϕ 2 V ref ϕ 1 R Q D Counting ϕ 2 V out Latch Digital Counter EN Clock Figure 5.11: Using noise-shaped integrating quantizer, merging it with the activeadder and removing the flash ADC. The output of the active-adder will be discharged and number of pulses during the discharge interval determines the final digital output code. adder is exactly the voltage that is needed to be quantized. This brings a perfect opportunity to use a single(dual)-slope ADC instead of the regular flash ADC. To do so, in the next phase where the active-adder was to be reset, instead, its output is discharged with a fixed current and the digital counter starts to increment until the first edge after the zero crossing to keep the residue, similar to what described in the previous section. The modified circuit of Fig employing the described technique is shown in Fig The only added hardware is few digital gates but the modulator achieves an extra order of noise shaping. Moreover, the power hungry flash ADC is replaced with a single comparator to detect the zero crossing. Furthermore, the active-adder will only drive a single comparator, whereas in the traditional modulators, it should to drive a multi-bit flash ADC which requires long routing. This added load due to the routing and several input capacitance of the comparator can be substantial and demands more current in the active-adder. As demonstrated in Fig. 5.11, the inputs of the active-adder (quantizer) are sampled

114 99 Active adder 1 (1 z )E 1 X 0.5z 1 z z 1 z 1 Y Figure 5.12: The block diagram of the implemented modulator. The proposed bi-directional noise-shaped quantizer is merged with the active adder and it shown with its equivalent linearized model. in switched-capacitor fashion. This removes the unnecessary windowing of the input signals which can affect the loop characteristics. 5.4 Circuit Implementation The proposed bi-directional noise-shaped quantizer is used in a second-order loop filter resulting in an overall third-order noise shaping, as shown in Fig This quantizer is merged with the active adder to reduce the hardware and the power consumption. The opamps used for the integrators are similar to the opamps used in extended dynamic range structure discussed in the previous chapter. The input signal sampling capacitors are shared with the front-end DAC capacitors to maximize the feedback factor of the first integrator and reduce the thermal noise from the input sampling.

115 Timing of the Quantizer As discussed earlier, the outputs of the loop filter are fed to an active-adder. In traditional modulators, this adder was used to feed the quantizer. In the proposed structure, this active adder will be discharged instead, and a single comparator will detect the common-mode crossing. The simplified schematic of the merged quantizer is shown in Fig and its timing is shown in Fig The basic principle of the operation is as follows. In ϕ 2 the outputs of the loop filter (first and second integrators) and the input signal are stored on the integrating capacitor of the active-adder (C IQ ). The continues-time comparator is always connected to the output of the active-adder, and by the end of ϕ 2 when the output of the opamp has settled, it will read the direction to discharge. This means, if the differential output is above the common-mode voltage, the direction of discharge should be negative, and if the differential output of the opamp is below the common-mode voltage, the direction of the discharge should be positive. The discharging circuitry has the non-overlapping of the clocks available to switch to the proper direction. By the starting of ϕ 1, the discharging circuitry will start to discharge (either positive or negative) until the next edge of the common-mode crossing. The digital circuitry will detect this crossing and stops the discharging. The final digital output (D out ) will be ready to be fed to the DWA which operates the front-end DAC of the modulator. In the next ϕ 2 where the next samples of the loop filter are being sampled, the LSB/2 compensation circuitry will start to discharge (opposite direction of the previous discharging) to remove the half LSB from the integrator. Thus, by the end of the ϕ 2, the polarity dependent offset has been removed and the comparator will decide on the next direction of the discharging.

116 101 R comp V ref + ϕ 2 ϕ 2 Dir Vref Half-LSB Compensation int 2-1 int1-1 R comp ϕ 2 Dir X ϕ ϕ 1 2 C Q2 ϕ 2 C Q1 ϕ 2 C IQ Discharging ϕ 1 ϕ 1 V ref + Vref ϕ dis R dis R dis ϕdis Dir ϕ dis Dir ϕ dis Dir D out V CM Digital Circuitry DLL ϕ1 Figure 5.13: The simplified schematic of the active-adder merged with the bidirectional single-slope quantizer. ϕ 1 ϕ 2 Sampling inputs+lsb/2 compensation Sampling inputs+lsb/2 compensation Reading direction Discharge starts Discharge ends Reading direction Figure 5.14: The timing diagram of the operation of the proposed quantizer Comparator The continuous-time comparator is implemented using cascade of three gain stages. This schematic is shown in Fig The final output is then buffered and

117 102 V dd R R R R Vo R R V o+ V in + V in V bias Figure 5.15: The continues-time comparator used for both direction and commonmode crossing detection. fed to digital detection circuitry. A simple DLL is used to provide five edges within the discharging phase, noting that for 9-level quantization, MSB is resolved first, and for each direction, 5-levels are requirers. The first edge is the common-mode level which is shared between both positive and negative and it has half the delay compared to the delay between the other edges to form a mid-tread quantizer. The output of the comparator is fed to five DFFs, which each are clocked by the edges generated from the DLL. When the comparator detects a common-mode crossing, its output becomes high (or low) and the first DFF which detects this transition will stop the discharging. In this fashion, the 9-level flash ADC is replaced with a coarse DLL and five D-flip-flops. 5.5 Measurement Results The prototype ADC is fabricated in a 0.18-µm 2-Poly 5-Metal CMOS process. Fig shows the die photograph of the fabricated prototype. The active

118 103 Figure 5.16: Die photograph of the fabricated prototype. area is 0.44mm 2. Fig shows two measured output spectrums. The sampling frequency is 50MHz and oversampling ratio is 24. The out-of-band peaking is deliberately set to help the stability and to allow larger input signals to be processed by the loop. Fig shows the measured SNR and SNDR versus 196kHz varying input signal amplitudes. This modulator achieves 78.2dB peak SNDR and 79.3dB peak SNR while consuming 1.35mW analog and 1.55mW digital power from 1.5V supplies. The major portion of the digital power (1.3mW) is consumed by an over-designed generic clock generator to provide flexibility in testing with various sampling frequencies. The rest of the digital power (0.25mW) includes the DLL, digital counter, DWA and the comparator. The achieved minimal analog power is a direct result of the extra order of noise shaping, and the elimination of the flash ADC and the typical large capacitive loading that comes with it. The FoM is 210fJ/conversion-step which shows significant power reduction due to elimination of the power consuming flash ADC and its substantial added routings. Table 5.1 summarizes the measured performance of the prototype ADC.