A Low-Power Single-Bit Continuous-time DS Converter with 92.5dB Dynamic Range and design of Low-Voltage Σ ADCs

Transcription

1 A Low-Power Single-Bit Continuous-time DS Converter with 92.5dB Dynamic Range and design of Low-Voltage Σ ADCs Sakkarapani Balagopal and Vishal Saxena* Department of Electrical and Computer Engineering Boise State University, ID IEEE Subthreshold Microelectronics Conference 2011 Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 1/34

2 Outline 1 Introduction 2 Architecture 3 System Design 4 Circuit Design 5 Simulation 6 Low-Voltage Design 7 Conclusion Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 2/34

3 Motivation Demonstrate a low-power CT- Σ ADC in the subthreshold optimized XLP2 process run ADC for Biomedical Signal Processing (BSP) chain requires Signal bandwidth of 1-6 KHz 14 bits resolution, low-power consumption Applications: Electro-cardiogram (ECG), Electroencephalogram (EEG), Evoked potential (EP), etc. ADC Architecture Delta-sigma ADC higher resolution, robust to device mismatch in nano-cmos Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 3/34

4 Motivation Demonstrate a low-power CT- Σ ADC in the subthreshold optimized XLP2 process run ADC for Biomedical Signal Processing (BSP) chain requires Signal bandwidth of 1-6 KHz 14 bits resolution, low-power consumption Applications: Electro-cardiogram (ECG), Electroencephalogram (EEG), Evoked potential (EP), etc. ADC Architecture Delta-sigma ADC higher resolution, robust to device mismatch in nano-cmos Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 3/34

5 Motivation Demonstrate a low-power CT- Σ ADC in the subthreshold optimized XLP2 process run ADC for Biomedical Signal Processing (BSP) chain requires Signal bandwidth of 1-6 KHz 14 bits resolution, low-power consumption Applications: Electro-cardiogram (ECG), Electroencephalogram (EEG), Evoked potential (EP), etc. ADC Architecture Delta-sigma ADC higher resolution, robust to device mismatch in nano-cmos Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 3/34

6 Continuous-time CT- Σ ADC Comprises of continuous-time loop filter,l(s), and a low resolution quantizer Output noise in signal band is suppressed by the noise-shaping loop Decimation filter is a synthesized digital block Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 4/34

7 Continuous-time CT- Σ ADC Comprises of continuous-time loop filter,l(s), and a low resolution quantizer Output noise in signal band is suppressed by the noise-shaping loop Decimation filter is a synthesized digital block Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 4/34

8 Continuous-time CT- Σ ADC Comprises of continuous-time loop filter,l(s), and a low resolution quantizer Output noise in signal band is suppressed by the noise-shaping loop Decimation filter is a synthesized digital block Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 4/34

9 Why Continuous-time Σ ADC? Low-power consumption compared to DT- Σ ADC Relaxed performance requirement for the integrators (opamps) Inherent anti-alias filtering (AAF) of CT ΔΣ Modulator Fixed resistive input impedance Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 5/34

10 Why Continuous-time Σ ADC? Low-power consumption compared to DT- Σ ADC Relaxed performance requirement for the integrators (opamps) Inherent anti-alias filtering (AAF) of CT ΔΣ Modulator Fixed resistive input impedance Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 5/34

11 Why Continuous-time Σ ADC? Low-power consumption compared to DT- Σ ADC Relaxed performance requirement for the integrators (opamps) Inherent anti-alias filtering (AAF) of CT ΔΣ Modulator Fixed resistive input impedance Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 5/34

12 Why Continuous-time Σ ADC? Low-power consumption compared to DT- Σ ADC Relaxed performance requirement for the integrators (opamps) Inherent anti-alias filtering (AAF) of CT ΔΣ Modulator Fixed resistive input impedance Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 5/34

13 Continuous-time DS ADC for BSP Target 6 KHz Bandwidth 15 bit resolution OSR = 512 (fs = 6.144MHz) Order of L(s) = μm FD-SOI process < 100µA current from a 1.5V supply Architecture choice Single-bit quantizer Distributed feed-forward summation (CIFF) architecture OBG =1.5 (for loop stability) Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 6/34

14 Continuous-time DS ADC for BSP Target 6 KHz Bandwidth 15 bit resolution OSR = 512 (fs = 6.144MHz) Order of L(s) = μm FD-SOI process < 100µA current from a 1.5V supply Architecture choice Single-bit quantizer Distributed feed-forward summation (CIFF) architecture OBG =1.5 (for loop stability) Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 6/34

15 Single-bit vs Multi-bit Quantizer Single-bit Quantizer Multi-bit Quantizer Simple hardware High jitter sensitivity 1-bit DAC is inherently linear Large opamp slew rate requirements Out-of-band gain (OBG) 1.5 Low power dissipation Complex hardware Low jitter sensitivity DAC non-linearity (DEM/DWA) Reduced slew rate requirements OBG 4 (aggressive NTF) Higher power dissipation Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 7/34

16 Modulator Architecture u t k3 c t fs n v n k2 k1 Loop-filter largely processes the quantization noise First opamp consumes more power better linearity and smaller input referred noise First integrator needs to be fastest in CIFF Last opamp is slowest and lowest power Out-of-band peaking in signal transfer function (STF ) Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 8/34

17 Modulator Architecture u t k3 c t fs n v n k2 k1 Loop-filter largely processes the quantization noise First opamp consumes more power better linearity and smaller input referred noise First integrator needs to be fastest in CIFF Last opamp is slowest and lowest power Out-of-band peaking in signal transfer function (STF ) Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 8/34

18 Modulator Architecture u t k3 c t fs n v n k2 k1 Loop-filter largely processes the quantization noise First opamp consumes more power better linearity and smaller input referred noise First integrator needs to be fastest in CIFF Last opamp is slowest and lowest power Out-of-band peaking in signal transfer function (STF ) Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 8/34

19 Modulator Architecture u t k3 c t fs n v n k2 k1 Loop-filter largely processes the quantization noise First opamp consumes more power better linearity and smaller input referred noise First integrator needs to be fastest in CIFF Last opamp is slowest and lowest power Out-of-band peaking in signal transfer function (STF ) Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 8/34

20 Modulator Architecture u t k3 c t fs n v n k2 k1 Loop-filter largely processes the quantization noise First opamp consumes more power better linearity and smaller input referred noise First integrator needs to be fastest in CIFF Last opamp is slowest and lowest power Out-of-band peaking in signal transfer function (STF ) Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 8/34

21 Continuous-time DS ADC CT-ΔΣ ADC is sensitive to Excess loop delay Comparator delay is τ d = 100ps T s Finite operational amplifier gain and gain-bandwidth product Clock Jitter Effect of jitter on SNR for NRZ is J = σ2 Ts T 2 s σ 2 LSB πosr π 0 ( 1 e jw) NTF ( e jw) 2 dω SJNR = 111.7dB σ j = 100 ps for f s = MHz is not an issue for 15-bit resolution RC time-constant variation Digital tuning method using a programmable capacitor bank (using σ 2 δv statistics) Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 9/34

22 Continuous-time DS ADC CT-ΔΣ ADC is sensitive to Excess loop delay Comparator delay is τ d = 100ps T s Finite operational amplifier gain and gain-bandwidth product Clock Jitter Effect of jitter on SNR for NRZ is J = σ2 Ts T 2 s σ 2 LSB πosr π 0 ( 1 e jw) NTF ( e jw) 2 dω SJNR = 111.7dB σ j = 100 ps for f s = MHz is not an issue for 15-bit resolution RC time-constant variation Digital tuning method using a programmable capacitor bank (using σ 2 δv statistics) Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 9/34

23 Continuous-time DS ADC CT-ΔΣ ADC is sensitive to Excess loop delay Comparator delay is τ d = 100ps T s Finite operational amplifier gain and gain-bandwidth product Clock Jitter Effect of jitter on SNR for NRZ is J = σ2 Ts T 2 s σ 2 LSB πosr π 0 ( 1 e jw) NTF ( e jw) 2 dω SJNR = 111.7dB σ j = 100 ps for f s = MHz is not an issue for 15-bit resolution RC time-constant variation Digital tuning method using a programmable capacitor bank (using σ 2 δv statistics) Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 9/34

24 Continuous-time DS ADC CT-ΔΣ ADC is sensitive to Excess loop delay Comparator delay is τ d = 100ps T s Finite operational amplifier gain and gain-bandwidth product Clock Jitter Effect of jitter on SNR for NRZ is J = σ2 Ts T 2 s σ 2 LSB πosr π 0 ( 1 e jw) NTF ( e jw) 2 dω SJNR = 111.7dB σ j = 100 ps for f s = MHz is not an issue for 15-bit resolution RC time-constant variation Digital tuning method using a programmable capacitor bank (using σ 2 δv statistics) Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 9/34

25 Continuous-time DS ADC CT-ΔΣ ADC is sensitive to Excess loop delay Comparator delay is τ d = 100ps T s Finite operational amplifier gain and gain-bandwidth product Clock Jitter Effect of jitter on SNR for NRZ is J = σ2 Ts T 2 s σ 2 LSB πosr π 0 ( 1 e jw) NTF ( e jw) 2 dω SJNR = 111.7dB σ j = 100 ps for f s = MHz is not an issue for 15-bit resolution RC time-constant variation Digital tuning method using a programmable capacitor bank (using σ 2 δv statistics) Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 9/34

26 Loop-filter Coefficient Tuning 0 Discrete Time Loop Filter L(Z) ς 20 Sampled integrator and loop-filter outputs l 0 u t ς 1+ς 0 Continuous Time Loop Filter L(s) lc(t) lc[n] 15 l 1 l 2 l 3 y c ρ(t-ς) t 5 0 u t ς 1+ς 1 t 2 t 3 t 3 c t s n ρ(t-ς) 2 1 Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 10/34

27 Loop-filter Coefficient Tuning Loop-filter coefficients are typically determined using the Schreier s ΔΣ Toolbox [2] Algorithm If the sampled outputs of the direct path and the integrators are given by l 0 [n], l 1 [n], l 2 [n] and l 3 [n], and the open-loop impulse response is l[n]. Here, Z(l[n]) = L(z) = 1 NTF (z) 1. The coefficients K = [ k 0 k 1 k 2 k 3 ] T are determined by solving [ l 0 [n] l 1 [n] l 2 [n] l 3 [n] ] K = l[n] Solved using LMS data fitting for N samples (pseudo-inverse of the matrix). Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 11/34

28 Loop-filter Coefficient Tuning Loop-filter coefficients are typically determined using the Schreier s ΔΣ Toolbox [2] Algorithm If the sampled outputs of the direct path and the integrators are given by l 0 [n], l 1 [n], l 2 [n] and l 3 [n], and the open-loop impulse response is l[n]. Here, Z(l[n]) = L(z) = 1 NTF (z) 1. The coefficients K = [ k 0 k 1 k 2 k 3 ] T are determined by solving [ l 0 [n] l 1 [n] l 2 [n] l 3 [n] ] K = l[n] Solved using LMS data fitting for N samples (pseudo-inverse of the matrix). Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 11/34

29 Problems with Coefficient Tuning Practical integrators are implemented using opamps finite opamp gain (A OL ) and unity-gain bandwidth (f un), and with additional poles and zeros NTFs The ELD due to finite f un causes significant amount of gain peaking in the resulting NTF. Tuning is numerically unstable [5] Higher OBG leads to instability in the modulator dbfs ω / π Ideal Real Integrator N=5 N=20 N=50 Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 12/34

30 Problems with Coefficient Tuning Practical integrators are implemented using opamps finite opamp gain (A OL ) and unity-gain bandwidth (f un), and with additional poles and zeros NTFs The ELD due to finite f un causes significant amount of gain peaking in the resulting NTF. Tuning is numerically unstable [5] Higher OBG leads to instability in the modulator dbfs ω / π Ideal Real Integrator N=5 N=20 N=50 Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 12/34

31 Problems with Coefficient Tuning Practical integrators are implemented using opamps finite opamp gain (A OL ) and unity-gain bandwidth (f un), and with additional poles and zeros NTFs The ELD due to finite f un causes significant amount of gain peaking in the resulting NTF. Tuning is numerically unstable [5] Higher OBG leads to instability in the modulator dbfs ω / π Ideal Real Integrator N=5 N=20 N=50 Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 12/34

32 Problems with Coefficient Tuning Practical integrators are implemented using opamps finite opamp gain (A OL ) and unity-gain bandwidth (f un), and with additional poles and zeros NTFs The ELD due to finite f un causes significant amount of gain peaking in the resulting NTF. Tuning is numerically unstable [5] Higher OBG leads to instability in the modulator dbfs ω / π Ideal Real Integrator N=5 N=20 N=50 Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 12/34

33 Systematic Design Centering Method Instead of fitting the open-loop response, fit NTF (z)(1 + L(z)) to 1 [5] Algorithm h[n] + h[n] l[n] = δ[n], where h[n] = Z 1 (NTF (z)) is the impulse response corresponding to NTF (z) Let h i [n] = l i [n] h[n], for i = 0, 1,.., 3 The coefficients K = [ k 0 k 1 k 2 k 3 ] T are determined by solving [ h 0 h 1 h 2 h 3 ] K = δ[n] h[n] Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 13/34

34 Systematic Design Centering Method Instead of fitting the open-loop response, fit NTF (z)(1 + L(z)) to 1 [5] Algorithm h[n] + h[n] l[n] = δ[n], where h[n] = Z 1 (NTF (z)) is the impulse response corresponding to NTF (z) Let h i [n] = l i [n] h[n], for i = 0, 1,.., 3 The coefficients K = [ k 0 k 1 k 2 k 3 ] T are determined by solving [ h 0 h 1 h 2 h 3 ] K = δ[n] h[n] Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 13/34

35 Systematic Design Centering contd. The loop-filter coefficients are tuned to compensate for the excess loop delay due to the op-amps and the quantizer delay NTF response with non-ideal integrators is close to the ideal NTF NTFs Coefficient tuning is numerically stable Custom toolbox for systematic design and rapid simulation of CT- Σ employs state-space representation and matrix integrals based solution dbfs ω / π Ideal N=5 N=20 N=50 Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 14/34

36 Systematic Design Centering contd. The loop-filter coefficients are tuned to compensate for the excess loop delay due to the op-amps and the quantizer delay NTF response with non-ideal integrators is close to the ideal NTF NTFs Coefficient tuning is numerically stable Custom toolbox for systematic design and rapid simulation of CT- Σ employs state-space representation and matrix integrals based solution dbfs ω / π Ideal N=5 N=20 N=50 Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 14/34

37 Systematic Design Centering contd. The loop-filter coefficients are tuned to compensate for the excess loop delay due to the op-amps and the quantizer delay NTF response with non-ideal integrators is close to the ideal NTF NTFs Coefficient tuning is numerically stable Custom toolbox for systematic design and rapid simulation of CT- Σ employs state-space representation and matrix integrals based solution dbfs ω / π Ideal N=5 N=20 N=50 Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 14/34

38 System Level Simulation Results CT DSM simulated using the custom tool SQNR = 149dB (sim time = 3 secs) non-linearities and thermal+flicker noise not included CT Modulator Output Spectrum dbfs SNDR = db ENOB = = ω / π Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 15/34

39 Noise Budget Noise is dominated by the resistance thermal noise in the loop-filter modulator is dithered by the dominant thermal noise (less tones) Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 16/34

40 Power Optimization System level power reduction by employing systematic design centering lower-power opamps for the same ADC performance The design leverages the higher gm I D ratios for XLP FDSOI when compared to the bulk CMOS Opamps operate in weak inversion region Circuits were implemented in the process V DD = 1.5V Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 17/34

41 Power Optimization System level power reduction by employing systematic design centering lower-power opamps for the same ADC performance The design leverages the higher gm I D ratios for XLP FDSOI when compared to the bulk CMOS Opamps operate in weak inversion region Circuits were implemented in the process V DD = 1.5V Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 17/34

42 Power Optimization System level power reduction by employing systematic design centering lower-power opamps for the same ADC performance The design leverages the higher gm I D ratios for XLP FDSOI when compared to the bulk CMOS Opamps operate in weak inversion region Circuits were implemented in the process V DD = 1.5V Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 17/34

43 Power Optimization System level power reduction by employing systematic design centering lower-power opamps for the same ADC performance The design leverages the higher gm I D ratios for XLP FDSOI when compared to the bulk CMOS Opamps operate in weak inversion region Circuits were implemented in the process V DD = 1.5V Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 17/34

44 Power Optimization System level power reduction by employing systematic design centering lower-power opamps for the same ADC performance The design leverages the higher gm I D ratios for XLP FDSOI when compared to the bulk CMOS Opamps operate in weak inversion region Circuits were implemented in the process V DD = 1.5V Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 17/34

45 Loop Filter Design Rr C1 C2 C3 Vim R1 Vom1 R2 Vop2 R3 Vom3 Vip R1 Vop1 R2 Vom2 R3 Vop3 C3 C1 C2 Rr R00 Vip Vop3 R33 R22 Vop2 Vop1 R11 Vop Vom1 Vom2 R11 R22 Vom Vom3 Vim Rf R f k0 = R00 Rf k1 = R11 Rf k2 = R22 R33 R00 Rf Rf k3 = R33 Opamp power consumption: A 1 > A 2 > A 3 Summing opamp consumes power comparable to A 1 Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 18/34

46 Loop Filter Design Rr C1 C2 C3 Vim R1 Vom1 R2 Vop2 R3 Vom3 Vip R1 Vop1 R2 Vom2 R3 Vop3 C3 C1 C2 Rr R00 Vip Vop3 R33 R22 Vop2 Vop1 R11 Vop Vom1 Vom2 R11 R22 Vom Vom3 Vim Rf R f k0 = R00 Rf k1 = R11 Rf k2 = R22 R33 R00 Rf Rf k3 = R33 Opamp power consumption: A 1 > A 2 > A 3 Summing opamp consumes power comparable to A 1 Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 18/34

47 Operational Amplifier First stage opamp is biased to draw 20µA from the supply (including CMFB loop). VDDA Vtail Vip 1 2 Vim Voutm V1 Voutp IC V01p V01m CIC V01m VBN1 V01p 12 V1 V2 VCMFB1 5 6 VGNDA Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 19/34

48 Comparator The comparator is biased with 1µA current. Dissipates 5µW at MHz clock rate. Delay = 100ps, Resolution = 1µV Resistive DAC was employed in the design Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 20/34

49 Comparator The comparator is biased with 1µA current. Dissipates 5µW at MHz clock rate. Delay = 100ps, Resolution = 1µV Resistive DAC was employed in the design Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 20/34

50 Chip Implementation On-chip capacitors n+ poly and n+ body plates C ox = 6 ff µm 2 On-chip resistors unsilicided nactive layer R = 3 kω 20% variation expected, but typical values are not controlled CT DSM can tolerate RC time-constant variation of 30%, but typical value needs to be fixed Linearity Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 21/34

51 Chip Implementation On-chip capacitors n+ poly and n+ body plates C ox = 6 ff µm 2 On-chip resistors unsilicided nactive layer R = 3 kω 20% variation expected, but typical values are not controlled CT DSM can tolerate RC time-constant variation of 30%, but typical value needs to be fixed Linearity Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 21/34

52 Chip Implementation On-chip capacitors n+ poly and n+ body plates C ox = 6 ff µm 2 On-chip resistors unsilicided nactive layer R = 3 kω 20% variation expected, but typical values are not controlled CT DSM can tolerate RC time-constant variation of 30%, but typical value needs to be fixed Linearity Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 21/34

53 Chip Implementation On-chip capacitors n+ poly and n+ body plates C ox = 6 ff µm 2 On-chip resistors unsilicided nactive layer R = 3 kω 20% variation expected, but typical values are not controlled CT DSM can tolerate RC time-constant variation of 30%, but typical value needs to be fixed Linearity Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 21/34

54 Chip Implementation On-chip capacitors n+ poly and n+ body plates C ox = 6 ff µm 2 On-chip resistors unsilicided nactive layer R = 3 kω 20% variation expected, but typical values are not controlled CT DSM can tolerate RC time-constant variation of 30%, but typical value needs to be fixed Linearity Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 21/34

55 Chip Micrograph Three CT- Σ modulators for wider RC spreads (2mm 1mm) Test structures for estimating R and C typical values Experimental results awaited Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 22/34

56 Chip Micrograph Three CT- Σ modulators for wider RC spreads (2mm 1mm) Test structures for estimating R and C typical values Experimental results awaited Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 22/34

57 Transistor-level Simulation Results PSD (db) Frequency (khz) Spectre simulated 16-bit resolution, 94.4 db dynamic range noise floor set by the transient simulation accuracy Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 23/34

58 Simulation Results Contd SNDR, db Amplitude, dbfs Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 24/34

59 Performance Summary Summary of simulated ADC performance. Signal Bandwidth/Clock Rate 6KHz/6.144MHz Quantizer Range 3V pp,diff Input Swing for peak SNR 1.92dBFS Dynamic Range/ SNDR 94.4dB/92.4dB Active Area 0.016mm 2 Process/Power Supply Voltage 0.15μmFD-SOI/1.5V Power Dissipation (Modulator) / +Ref 110μW /20μW Figure of Merit 0.271pJ/level Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 25/34

60 Low-Voltage CT- Σ Design A 0.5V CT- Σ ADC has been demonstrated in bulk CMOS[10] Employs low-voltage OTAs with body input and local CMFB[11] Return-to-open (RTO) DAC Multi-bit, 0.5V Σ ADC designs are difficult with traditional architectures insufficient headroom for quantizer (think LSB size) K.-P. Pun, S. Chatterjee, P. Kinget, "A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC." IEEE JSSC, vol. 42, no. 3, Mar 2007 Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 26/34

61 Low-Voltage CT- Σ Design A 0.5V CT- Σ ADC has been demonstrated in bulk CMOS[10] Employs low-voltage OTAs with body input and local CMFB[11] Return-to-open (RTO) DAC Multi-bit, 0.5V Σ ADC designs are difficult with traditional architectures insufficient headroom for quantizer (think LSB size) K.-P. Pun, S. Chatterjee, P. Kinget, "A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC." IEEE JSSC, vol. 42, no. 3, Mar 2007 Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 26/34

62 Multi-Step Quantizers Multi-Step quantizers can be leveraged to realize multi-bit CT- Σ Quantizer comprises of single-bit stages (Low-voltage) Need to compensate for the additional latency Low-voltage Subtractor/MDAC is required φ1 Vref1 b0 DAC Cdac Csub Vsub φ2_delayed Vref Vref Vin φ1 Csub Vin b1 φ1 Subtractor Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 27/34

63 Multi-Step Quantizers Multi-Step quantizers can be leveraged to realize multi-bit CT- Σ Quantizer comprises of single-bit stages (Low-voltage) Need to compensate for the additional latency Low-voltage Subtractor/MDAC is required φ1 Vref1 b0 DAC Cdac Csub Vsub φ2_delayed Vref Vref Vin φ1 Csub Vin b1 φ1 Subtractor Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 27/34

64 Multi-Step Quantizers Multi-Step quantizers can be leveraged to realize multi-bit CT- Σ Quantizer comprises of single-bit stages (Low-voltage) Need to compensate for the additional latency Low-voltage Subtractor/MDAC is required φ1 Vref1 b0 DAC Cdac Csub Vsub φ2_delayed Vref Vref Vin φ1 Csub Vin b1 φ1 Subtractor Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 27/34

65 CT- Σ ELD Compensation (1 < τ < 2) A S/H is used to compensate for the ELD by creating a fast loop NTF new (z)= (1 + az 1 )NTF original (z) Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 28/34

66 Comparison of NTF original (z) with NTF new (z) Magnitude response (db) Order = 4 OSR = 10 OBG orig = 3 OBG new = 7-40 ELD < 1 ELD = ω / π NTF(e jω ) showing the effect of (1 + az 1 ) in the NTF new (e iω ) An additional zero in the NTF new (e iω ) reduces the in-band SQNR Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 29/34

67 Comparison of NTF original (z) with NTF new (z) Magnitude response (db) Order = 4 OSR = 10 OBG orig = 3 OBG new = 7-40 ELD < 1 ELD = ω / π NTF(e jω ) showing the effect of (1 + az 1 ) in the NTF new (e iω ) An additional zero in the NTF new (e iω ) reduces the in-band SQNR Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 29/34

68 Comparison of NTF original (z) with NTF new (z) Magnitude response (db) Order = 4 OSR = 10 OBG orig = 3 OBG new = 7-40 ELD < 1 ELD = ω / π NTF(e jω ) showing the effect of (1 + az 1 ) in the NTF new (e iω ) An additional zero in the NTF new (e iω ) reduces the in-band SQNR Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 29/34

69 Two-Step Quantizer Simulation Results System-level Simulink simulation results for a CT- Σ 2-bit, two-step quantizer Stable loop with ELD=1.5 Ideal SNDR = 157 db, MSA is reduced to 0.6 Can be extended to a pipelined Quantizer with ELD>2 compensation Modulator Output Spectrum Modulator Output Spectrum dbfs -100 dbfs SNDR = db ENOB = = SNDR = db ENOB = = ω / π ω / π Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 30/34

70 Two-Step Quantizer Simulation Results System-level Simulink simulation results for a CT- Σ 2-bit, two-step quantizer Stable loop with ELD=1.5 Ideal SNDR = 157 db, MSA is reduced to 0.6 Can be extended to a pipelined Quantizer with ELD>2 compensation Modulator Output Spectrum Modulator Output Spectrum dbfs -100 dbfs SNDR = db ENOB = = SNDR = db ENOB = = ω / π ω / π Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 30/34

71 Two-Step Quantizer Simulation Results System-level Simulink simulation results for a CT- Σ 2-bit, two-step quantizer Stable loop with ELD=1.5 Ideal SNDR = 157 db, MSA is reduced to 0.6 Can be extended to a pipelined Quantizer with ELD>2 compensation Modulator Output Spectrum Modulator Output Spectrum dbfs -100 dbfs SNDR = db ENOB = = SNDR = db ENOB = = ω / π ω / π Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 30/34

72 Conclusion A low-power Continuous-time Σ ADC has been designed in the XLP2 FDSOI process CT loop-filter coefficients were systematically obtained by incorporating the op-amp non-idealities The method, coupled with higher gm I D performance of XLP2 transistors, resulted in lower power consumption in the opamps System-level techniques were discussed to enable design for higher-performance multi-bit CT- Σ ADCs in <0.5V regime Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 31/34

73 Conclusion A low-power Continuous-time Σ ADC has been designed in the XLP2 FDSOI process CT loop-filter coefficients were systematically obtained by incorporating the op-amp non-idealities The method, coupled with higher gm I D performance of XLP2 transistors, resulted in lower power consumption in the opamps System-level techniques were discussed to enable design for higher-performance multi-bit CT- Σ ADCs in <0.5V regime Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 31/34

74 Conclusion A low-power Continuous-time Σ ADC has been designed in the XLP2 FDSOI process CT loop-filter coefficients were systematically obtained by incorporating the op-amp non-idealities The method, coupled with higher gm I D performance of XLP2 transistors, resulted in lower power consumption in the opamps System-level techniques were discussed to enable design for higher-performance multi-bit CT- Σ ADCs in <0.5V regime Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 31/34

75 Conclusion A low-power Continuous-time Σ ADC has been designed in the XLP2 FDSOI process CT loop-filter coefficients were systematically obtained by incorporating the op-amp non-idealities The method, coupled with higher gm I D performance of XLP2 transistors, resulted in lower power consumption in the opamps System-level techniques were discussed to enable design for higher-performance multi-bit CT- Σ ADCs in <0.5V regime Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 31/34

76 Questions? Questions? Vishal Saxena Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 32/34

77 References I N. Van Helleputte et al., "A flexible system-on-chip (SoC) for biomedical signal acquisition," Sensors and Actuators: A. Physical, vol. 142 no. 1, pp , R. Schreier and G. Temes, Understanding Delta-Sigma Data Converters. Piscataway, NJ: IEEE Press, S. Pavan, N. Krishnapura, R. Pandarinathan, and P. Sankar, "A power optimized continuous-time Delta-Sigma ADC for audio applications," IEEE J. Solid-State Circuits, vol. 43, no. 2, pp , Feb P. Sankar and S. Pavan, "Analysis of integrator nonlinearity in a class of continuous-time delta-sigma modulators," IEEE Trans. Circuits Syst.II, Exp. Briefs, vol. 54, no. 12, pp , Dec S. Pavan, "Systematic Design Centering of Continuous Time Oversampling Converters," IEEE tran.on circuits and systems-ii, vol. 57, no. 3, pp , March S. Pavan, and N. Krishnapura,"Automatic Tuning of Time Constants in Continuous-Time Delta-Sigma Modulators,"IEEE Trans. Circuits Syst.II, Exp. Briefs, vol. 54, no. 4, pp , April J. Cherry and W. Snelgrove, "Excess loop delay in continuous-time delta-sigma modulators," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 4, pp , Apr K. Reddy and S. Pavan, "Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 10, pp , Oct Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 33/34

78 References II Saxena, V., and Baker, R.J., "Compensation of CMOS Op-Amps using Split-Length Transistors,", proceedings of the 51st Midwest Symposium on Circuits and Systems, pp , August 10-13, K.-P. Pun, S. Chatterjee, P. Kinget, "A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC." IEEE JSSC, vol. 42, no. 3, Mar 2007 S. Chatterjee, Y. Tsividis, and P. Kinget, "0.5-V analog circuit techniques and their application in OTA and filter design," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp , Dec Sakkarapani Balagopal and Vishal Saxena* Continuous-time DS ADC 34/34