High-Speed Serial IO Testing: Jitter Extraction & Bit-Error Rate Estimation. Serial Signaling Speed Trend

Transcription

1 High-Speed Serial IO Testing: Jitter Extraction & Bit-Error Rate Estimation K.-T. Tim Cheng Dept. of ECE University of California, Santa Barbara Serial Signaling Speed Trend 8/6/04

2 Bus Topologies 8/6/04 3 Parallel Bus vs Serial Link Setup Tx Hold Parallel Bus Setup Rx Hold Tx Serial Link Rx 8/6/04 4

3 Serial Link Overview Data TX SER. Data with Embedded Clock RX DES. Data CDRC Clock is embedded in data Clock and Data Recovery (CDR) circuit is required The BER or quality of transmission depends on the receiver s ability to recover the clock signal from the transmitted data 8/6/04 5 Bit-Error Error-Rate Testing of HSL Most serial links require 10-1 or lower BER To measure such level of BER, test time would be excessively long Timing jitter is the major contributor to BER Infer BER based on extracted jitter Would reduce test time significantly 8/6/04 6

4 Serial Link Operation t i (T) t i (T) Data with Embeded Clock D SET Q Output Jitter (µseconds) Data Clk t o (T) t o (T) Total Jitter Recovered Clock Jitter Number of Samples CDR Circuit Recovered Clock CDR circuit has a low- pass filter characteristic for the input jitter If the change rate of jitter is gradual, the CDR circuit can track CLR Q 8/6/04 7 Serial Link Operation Jitter (seconds) Total Jitter Number of Samples Recovered Clock Jitter If jitter varies significantly from cycle to cycle, the CDR circuit cannot track Extracting jitter s spectral information is critical for measuring transmission quality 8/6/04 8

5 Outline Jitter Extraction Techniques Bit-Error Rate Testing & Estimation 8/6/04 9 Jitter Extraction for Multi- GHz Signal N sample periods every every N cycles The filtered periods spectrum reshaped with inverse filter fertrans function The noise population used for random jitter estimation LPF LPF Sampling Time Time Estimation Period Period adjustment FFT FFT or or computing derivatives A B The filtered periods spectrum B P = NSE_tot PNSE_A A Sinusoidal Jitter Jitter Extraction Random Jitter Jitter Extraction Extraction Using single-shot shot measurement unit to sample signal periods for spectral analysis No reference clock required for sampling Ref: Ong, Hong, Cheng and Wang, ASP-DAC 004 and DATE004 8/6/04 10

6 Derivative-based Random Jitter Extraction The The variance of a signal s derivative is dominated by the higher-frequency components within the signal x x Periods Width (secs) Periods Width (secs) Sample Numbers Sampled Periods Sample Numbers Sampled Periods Derivative The random jitter variance can be estimated from the variance of the total jitter s s derivative 8/6/04 11 Measuring Multiple Periods Per Sample N sample periods every every N cycles T he filtere d pe rio ds spe ctrum re s ha ped w ith inve rse filte fer r tra function ns T he no ise pop ula tio n used for ra ndo m jitte r e stimatio n LPF Sampling Time Time e Estimation a tion Period adjustment FFT or or computing computing derivatives derivatives A B T he filtere d pe rio ds spe ctrum B P = NSE_tot PNSE_A A Sinusoidal Jitter Jitter Extraction Extraction Random Jitter Jitter Extraction 8/6/04 1

7 Measuring Multiple Periods Per Sample N sample periods every every N cycles T he filtere d pe rio ds spe ctrum re s ha ped w ith inve rse filte fer r tra function ns T he no ise pop ula tio n used for ra ndo m jitte r e stimatio n LPF Sampling Time Time e Estimation a tion Period adjustment FFT or or computing computing derivatives derivatives A B T he filtere d pe rio ds spe ctrum B P = NSE_tot PNSE_A A Sinusoidal Jitter Jitter Extraction Extraction Random Jitter Jitter Extraction 8/6/04 13 Measuring Multiple Periods Per Sample N sample periods every every N cycles T he filtere d pe rio ds spe ctrum re s ha ped w ith inve rse filte fer r tra function ns T he no ise pop ula tio n used for ra ndo m jitte r e stimatio n LPF Sampling Time Time e Estimation a tion Period adjustment FFT or or computing computing derivatives derivatives A B T he filtere d pe rio ds spe ctrum B P = NSE_tot PNSE_A A Sinusoidal Jitter Jitter Extraction Extraction Random Jitter Jitter Extraction Sampling the length of multiple-periods, periods, instead of single-period, to reduce performance requirement of the sampling circuitry - Accuracy increases for periodic jitter - Accuracy decreases for random jitter Can be compensated by more samples Ref: Ong, Hong, Cheng and Wang, VLSI Test Symp /6/04 14

8 Experiment Setup 3GHz Signal Generator Jitter char: 3 sinusoidal jitters and a random jitter Jitter Spectral Extraction N Sinusoidal jitter extraction - LPF - Sample time estimation - Period estimation - FFT Random jitter extraction - Differentiation Demonstrated, through simulation, accurate extraction of multiple sinusoids & random jitter components for a 3GHz signal 8/6/04 15 Outline Jitter Extraction Techniques Bit-Error Rate Testing & Estimation 8/6/04 16

9 BER Testing of HSL Most serial links require 10-1 or lower BER To measure such level of BER, test time would be excessively long Timing jitter is the major contributor to BER Infer BER based on extracted jitter Would reduce test time significantly 8/6/04 17 Key Parameters for BER Est. Spectral information of jitter Frequencies and amplitudes of Sinusoidal Jitter (SJ) Variance of Random Jitter (RJ) Jitter transfer characteristics of CDR circuit Magnitude response - Low pass filter characteristic Phase response - Determining timing response in clock recovery Ref: Hong, Ong, and Cheng, to appear in Int l Test Conf /6/04 18

10 BER Estimation with RJ T Data Clk 0.5T Ideal Sampling Point RJ Error Error RJ RJ is characterized by a zero-mean Gaussian BER BER can be estimated using Q function BER = T Q ( σ ) 1 Q( x) = P[ X > x] = Π e x t / 8/6/ T dt * Source: John P. et al, DesignCon 00 Impact on BER for SJ and RJ SJs within certain amplitudes and frequencies do not contribute to BER RJ contributes BER depending on the variance Amp. SJ Freq. BER RJ Var. BER 50KHz 0 0.1T 1MHz 10MHz 0 0 T / e-5 100MHz 0 8/6/04 0

11 BER - Different Combinations of SJ and RJ SJ RJ BER Amp. Freq. Var. SJ+RJ 50KHz 9.6e T 1MHz 10MHz T / e-4 1.8e-4 100MHz 1.69e-4 SJsSJs of different frequencies (but same amplitude), combined with fixed RJ, resulted in different BER Due to the receiver s s jitter transfer characteristic 8/6/04 1 Clock and Data Recovery Circuit CDRC CDRC commonly implemented using PLL-based architecture CDR CDR ckt has low-pass filter characteristic for input jitter If change rate is gradual, CDRC can track no bit error If jitter is of very high frequency, CDRC cannot track errors 8/6/04

12 Characteristics of CDR Ckt Divide it into 4 regions: Region1 (0~70KHz) Magnitude gain is 1 Phase curve is flat Region(70KHz~MHz) Magnitude gain is 1 Phase curve is non-flat Region3(MHz~40MHz) Magnitude gain is < 1 Phase curve is non-flat region1 region region3 region4 Region4(40MHz~ ) Magnitude gain is negligible 8/6/04 3 BER Estimation Each region uses a different equation for BER est. Region 1 Magnitude gain is 1, and phase curve is flat SJ is perfectly tracked No contribution to BER Only RJ contributes to BER T BER = Q ( ) σ n : Variance of RJ σ n 8/6/04 4

13 Characteristics of CDR Ckt Divide it into 4 regions: Region1 (0~70KHz) Magnitude gain is 1 Phase curve is flat Region(70KHz~MHz) Magnitude gain is 1 Phase curve is non-flat Region3(MHz~40MHz) Magnitude gain is < 1 Phase curve is non-flat region1 region region3 region4 Region4(40MHz~ ) Magnitude gain is negligible 8/6/04 5 BER Estimation (Region ) Jitter (seconds) Error Boundaries Magnitude gain is 1 SJ is tracked by the CDRC Total Jitter Phase curve has a non-zero slope Sinusoidal Jitter Recovered clock has certain delay t 0 Recovered Time delay t 0 is calculated by Clock Jitter d t0 = { H ( jω)} dω Number of Samples 8/6/04 6

14 BER Estimation (Region ) Assume input SJ is Error occurs when: a sin( ω ) 1 t a 1 sin( ωt) + n( t) a1 sin( ω( t t0)) + T, and RJ is n(t) / a1 sin( ωt) + n( t) a1 sin( ω( t t0)) T /, or Data with Embeded Clock Output SET D Q By simplification: a1 cos( ωt0 )sin( ωt +Θ1 ) + n( t) T / Therefore effective variance is σ = a + eff BER = 1 ( 1 cos( ωt0 )) σ n T Q( σ eff ) CDR Circuit Recovered Clock CLR Q 8/6/04 7 Characteristics of CDR Ckt Divide it into 4 regions: Region1 (0~70KHz) Magnitude gain is 1 Phase curve is flat Region(70KHz~MHz) Magnitude gain is 1 Phase curve is non-flat Region3(MHz~40MHz) Magnitude gain is < 1 Phase curve is non-flat region1 region region3 region4 Region4(40MHz~ ) Magnitude gain is negligible 8/6/04 8

15 BER Estimation (Region 3) Jitter (seconds) Error Boundaries Number of Samples Total Jitter Sinusoidal Jitter Recovered Clock Jitter Magnitude gain is less than 1 SJ is not perfectly tracked Phase Phase curve has a non-zero slope Recovered clock has certain delay t 0 Time Time delay is almost half of the period of SJ 8/6/04 9 BER for Different Combinations of SJ and RJ SJ RJ BER Amp. Freq. Var. SJ+RJ 50KHz 9.6e UI 1MHz 10MHz T / e-4 1.8e-4 100MHz 1.69e-4 8/6/04 30

16 BER Estimation (Region 3) Assume input SJ is Recovered clock jitter Error occurs when By simplifying a sin( ω ) 1 t, and RJ is n(t) a sin( ω( t t0)) a 1 sin( ωt) + n( t) a sin( ω( t t0)) + T / a1 sin( ωt) + n( t) a sin( ω( t t0)) T /, or ( a < a1) Data with Embeded Clock CDR Circuit a1 + a a1a cos( ωt0 )sin( ωt + Θ) + n( t) T / D Recovered Clock SET CLR Q Q Output Therefore effective variance is a1 a a σ eff = (1 + cos( ωt0 )) + σ n a a 1 1 8/6/04 31 Characteristics of CDR Ckt Divide it into 4 regions: Region1 (0~70KHz) Magnitude gain is 1 Phase curve is flat Region(70KHz~MHz) Magnitude gain is 1 Phase curve is non-flat Region3(MHz~40MHz) Magnitude gain is < 1 Phase curve is non-flat region1 region region3 region4 Region4(40MHz~ ) Magnitude gain is negligible 8/6/04 3

17 BER Estimation (Region 4) Jitter (seconds) Error Boundaries Number of Samples Total Jitter Sinusoidal Jitter Recovered Clock Jitter Magnitude gain is negligibly small SJ is not tracked at all SJ can be interpreted as RJ Error Error occurs when a1 sin( ωt) + n( t) T / Thus effective variance is: a1 σ eff = + σ n 8/6/04 33 Experiment Results 1.00E E E E E E-04 BER 1.00E-05 BER 1.00E E E E E-07 T/6.6 T/7.8 T/8.8 T/9.8 T/6.6 T/7.8 T/8.8 T/9.8 RJ Var RJ Var Sim. BER Est. BER Sim. BER Est. BER Region 1 (50KHz SJ + RJ) 1.00E-0 Region (1 MHz SJ + RJ) 1.00E E E E-04 BER 1.00E E-05 BER 1.00E E E E-07 T/6.6 T/7.8 T/8.8 T/9.8 RJ Var 1.00E-07 T/6.6 T/7.8 T/8.8 T/9.8 RJ Var Sim. BER Est. BER Region 3 (10MHz SJ + RJ) Sim. BER Est. BER Region 4 (100MHz SJ + RJ) 8/6/04 34

18 Experiment Results 1.00E-0 BER 1.00E E E E E-07 T/6.6 T/7.8 T/8.8 T/9.8 RJ Var In this experiment, three SJ components (50KHz, 1MHz, and 10MHz) are injected with RJ Sim. BER Est. BER <% errors between simulated and estimated BER s Proposed technique seems promising for estimating the BER 8/6/04 35 Summary and On-Going Work Jitter spectral analysis Accurate extraction of sinusoidal and random jitter components Estimation of BER using Frequencies and amplitudes of SJs Variance of RJ Characteristics of the CDR circuit Simulation results are promising On-going work Include non-idealities of the CDR circuit Incorporate the Data Dependent Jitter (DDJ) Validate by hardware measurement 8/6/04 36