Implementation of High-throughput Access Points for IEEE a/g Wireless Infrastructure LANs

Transcription

1 Implementation of High-throughput Access Points for IEEE a/g Wireless Infrastructure LANs Hussein Alnuweiri Ph.D. and Diego Perea-Vega M.A.Sc. Abstract In this paper we discuss the implementation of a development platform for IEEE a/g Wireless Infrastructure LANs. The implemented algorithms for the physical layer are based on a MATLAB simulation model developed by the group. These algorithms are implemented in the custom logic of a FPGA. The algorithms for the MAC layer are written in C and are implemented in software. We discuss the hardware platform chosen for this system and how it can achieve the speed requirements. This hardware development platform is useful to implement the IEEE a/g standard and to test new algorithms proposed by the group.. is sent through the channel (PHY optimization) and third, adding scheduling algorithms that guarantee per flow QoS guarantees. Our group s research interests include designing new techniques to achieve all of these goals by independently tackling issues at the MAC and PHY layers of a wireless infrastructure network. Another step in these efforts includes the study of techniques to optimize resources in both layers by performing cross-layer optimization. Index Terms Wireless LAN, IEEE standard, OFDM. W I. INTRODUCTION IRELESS infrastructure LANs (WLANs) provide users with a mechanism to access resources within their networks at homes or offices without the inconvenience of being connected through a physical wire. As an example, current laptop computers include wireless cards for the IEEE a/g standard that use Access Points to connect to the Ethernet wired network at data rates up to 54 Mbps. Because of this allowed freedom in mobility users also want to use portable devices like telephones and hand-help computers to transmit real time data, like voice and video, over their home/office wireless networks. Figure 1 illustrates this scenario. To achieve this goal wireless infrastructure network should guarantee access to the channel in a timely manner and at high data rates to provide a reliable communication. In order to support multimedia data and to increase throughput in the system, improvements have been made to the a/g [1] standard to support QoS (Quality of Service). Amendment IEEE e [2] uses new mechanisms for QoS support, namely the Enhanced the Distributed Coordination Function (EDCF) and the Hybrid Coordination Function (HCF). Due to the highly deployment of Wireless Infrastructure LANs, it is of interest to research different design parameters in the standard and new mechanisms that can improve performance under different scenarios. These efforts can be classified in three groups. First, improving the efficiency of the Media Access algorithms (MAC) optimization. Second,.increasing the data rate at which data Access Point Fig. 1. A Basic Service Set in IEEE infrastructure wireless networks Figure 2 shows the layer architecture of the standard. For the PHY layer optimization, our group has developed a complete simulation model of the physical (PHY) layer for a point-to-point communication in a IEEE a/g wireless infrastructure network [3]. This model is used to estimate the BER performance obtained when using different parameters and configurations in the system, it showed that the introduction of a spectrum-shaping filter reduces the interference of adjacent channels. It also evaluated the effects of using soft vs. hard decision in Viterbi decoding and studied its effect on channel estimation. For the MAC layer optimization, our group studied the effect of changing the Contention Window Parameters (CW) on the saturation throughput of a wireless network. In [4], a centralized MAC adaptation algorithm for e wireless networks that changes the Contention Window Parameters was proposed. This algorithm has advantages over the fixedparameter e wireless networks.

2 In addition, the group proposed a scheduling framework that builds on top of the capabilities of the e standard, and provides deterministic per-flow QoS guarantees to multimedia sessions over WLANs [5]. This scheduler module resides in the e access point and shows lower probability of delay for multimedia data transmitted over the network. The results of these research efforts need to be implemented in a prototype in order to test the proposed changes on real networks. At the same time, by implementing the system in hardware the group can become aware of implementation challenges and propose more optimal implementations for critical parts of the system. The objective of this paper is to discuss the implementation of the MAC and PHY layers of IEEE a/g wireless networks in a hardware platform that serves the double purpose of implementing the standard and validating new algorithms. The core of the physical layer of IEEE a/g wireless networks is the modulator and demodulator pair. In section 2 we describe the principles of Orthogonal Frequency Division Multiplexing (OFDM) modulation used in the IEEE a/g standard. Consequently, we describe the Matlab model for the transmitter and receiver in section 3 and provide a high level description of the MAC layer software in section 4. Finally, we present the high level design of a hardware development platform for such systems in section 5. large apart to avoid interference, in OFDM systems the carriers overlap making a more efficient use of the spectrum. In order to avoid interference between carriers in OFDM systems, carrier frequencies are chosen such the signals are orthogonal. This is achieved by picking the carrier frequencies separation f 0 to be equal to the inverse of the symbol period T. s k ( t ) = sin(2π kf t 0 ) k = 1,2,... M For 0< t< T and s k ( t) = 0 otherwise. (1) As an example, Figure 3 shows the spectrum of each of five sub-carriers, and the discrete frequency samples seen by an OFDM receiver Figure 3 Spectrum of five OFDM sub-carriers OFDM systems transmit a large number of narrowband carriers closely spaced in the frequency domain. At the transmitter, each OFDM carrier corresponds to one element of the discrete Fourier spectrum. The amplitudes and phases of the carriers depend on the data to be transmitted. The data transitions are synchronized at the carriers and can be processed together, symbol by symbol. Figure 2 Layer architecture of the standard. II. OFDM MODULATION A. OFDM principles OFDM makes use of the same principle of frequency division multiplexing (FDM) systems in the sense that uses different frequency carriers to transmit information over a channel, but contrary to FDM systems that require carrier frequencies to be B. OFDM FFT-based implementation In order to avoid a large number of modulators and filters at the transmitter, and complementary filters and demodulators at the receiver, the inverse Fourier transform FFT algorithm is used. Figure 4 illustrates the process of a typical FFT-based OFDM system. The incoming serial data is first converted form serial to parallel and grouped into x bits each to form a complex number. The number x determines the signal constellation of the corresponding sub-carrier, such as 1 bit for BPSK or 2 bits for QPSK, etc. The complex numbers are modulated in baseband by the inverse FFT (IFFT) and converted back to serial data for transmission. A guard interval is inserted between symbols to avoid intersymbol interference (ISI) caused by multipath distortion. The discrete symbols are converted to analog and low-pass filtered for RF up-conversion. The receiver performs the inverse process of the transmitter

3 Figure 4. A typical FFT-based OFDM system Because of its spectral efficiency, performance on slowfading channels and practical implementation using the FFT algorithm, OFDM has been chosen as the modulation scheme for IEEE a/g systems. In the IEEE g standard a frequency band in the 2.4 GHz ISM band is used that fits three 20 MHz channels, whereas the IEEE a utilizes 300 MHz of bandwidth in the 5 GHz unlicensed U.S.A. National Information Infrastructure (U-NII) band [1]. Twelve 20 MHz channels are accommodated in this bandwidth. The high data rate on OFDM systems is accomplished by combining many lower-speed subcarriers to create one highspeed channel. Each of these channels is divided into 52 subcarriers, each approximately 300 KHz wide. From these 52 subcarriers 4 are used to carry pilot signals (tones) that help estimating and equalizing the channel at the receptor. In addition, forward error correction coding (convolutional coding) and time diversity techniques are used to improve performance. Table 1 illustrates the data bit rates supported using different combinations of modulation and coding rates. The signal field consists of 24 bits, defining data rate and frame length. The IEEE a version of OFDM uses a combination of binary phase shift keying (BPSK) quadrature PSK (QPSK), and quadrature amplitude modulation (QAM), depending on the chosen data rate as shown in Table 1. The length field identifies the number of octets in the frame. The PLCP preamble and signal field are convolutionally encoded and sent at 6 Mbps using BPSK regardless of the data rate used in the signal field, The convolutional encoding rate depends on the chosen data rate. III. PHY LAYER TRANSMITTER AND RECEIVER In a more detailed view, an OFDM modulator includes the following sub-blocks: Modulation bank Pilot signals generation Training sequence generation OFDM Framer IFFT block Append cycle prefix TX Spectrum shaping Figure 6 illustrates these blocks as implemented in Matlab Simulink for the BPSK case. TABLE I MODULATION SCHEMES IN IEEE A/G PHY LAYER Figure 6. PHY Matlab Simulink transmitter model Figure 5 illustrates the frame format for an IEEE a frame. The PLCP preamble field is present for the receiver to acquire an incoming OFDM signal and synchronize the demodulator. The preamble consists of 12 symbols. Ten of the symbols are short for establishing Automatic Gain Control (AGC) and the coarse frequency estimate of the carrier signal. The receiver uses the long symbols for fine-tuning. With this preamble, it takes 16 microseconds to train the receiver after first receiving the frame. Figure 5. PHY Frame Format [1] To feed the simulation model, we generate random data from a Gaussian source which is then convolutionally encoded, interleaved and punctured according to the standard [1]. The encoded data is fed to an OFDM modulator. Table 1 shows the possible combinations of coding rate and modulation schemes. We illustrate the case of BPSK modulation, ½ coding rate in this paper. In a real scenario, feedback from the receiver controls which combination is selected. The OFDM frame assembler places the OFDM symbols on designated subcarriers and adds the zero, pilot subcarriers and training sequences. An inverse Fast Fourier Transform (IFFT) is performed on the subcarriers to form the time domain OFDM frame, which is cyclically prefixed and spectrally shaped before being serially transmitted over the channel.

4 In the receiver direction the opposite operations of the transmitter are performed. In addition, channel equalization is performed to compensate the effects of the channel in the transmitted signal as illustrated in Figure 7. V. HARDWARE IMPLEMENTATION In order to achieve the maximum rate of 54 Mbps, a system that implements the IEEE standard has demanding requirements in terms of processing power and data transfer speed. At the same time we want to have a flexible platform that allows us to modify parameters in the standard and include new features. All theses factors were taken into account for the selection of the hardware development platform. We considered the following options: Custom board design DSP development board with analog interface FPGA development board with analog interface Figure 7. PHY receiver model The OFDM receiver and transmitter blocks require a high number of DSP operations that need to be implemented in specialized hardware architectures or in very fast DSP processors. IV. MAC ALGORITHM In contrast to the PHY layer, the MAC algorithm consists of timers, queues and management functions that can be implemented in software running in a serial processor without detriment in system performance. Figure 8 illustrates a high level description of the MAC layer sub-modules for For more details on how the MAC algorithm works the reader is referred to the standard [1]. Figure 8 MAC layer architecture The design and implementation of a custom board was discarded because of the cost and time we would incur in such task. The DSP versus FPGA solutions brings a trade-off between processing speed and flexibility in the development. Ideally, we would like to have both the speed offered by a hardware implementation (FPGA solution) and the flexibility offered by C language in a software-based implementation (DSP-based solution). In the literature several approaches have been taken to implement such systems. In [7], a real-time baseband implementation of an OFDM QPSK based WLAN system was developed using the Texas Instruments fixed point processor in the TMS320C6201 DSP development board and a custom daughter board to accommodate buffer memory and high speed A/D converters. At the application layer an uncoded user data rate of 1.7 Mb/s was achieved. The authors estimated that to achieve full data rate (i.e. 54 Mbps) some form of strategic hardware acceleration is required to support the DSP. In [8], a software based IEEE a digital baseband transmitter was implemented on a highly parallel single-chip DSP processor. The authors claimed their transmitter is the first fully-compliant a software implementation. However to achieve full-rate they used a 22- processor DSP array. In [9], the Virtex 2 FPGA from Xilinx was used to implement the PHY layer of the a standard, achieving data rates up to 72 Mbits/s. We decided upon one FPGA-based solution that contains an embedded PowerPC processor in order to have the best of both worlds. At the same time the chosen development board provides the Analog/Digital interfaces required to connect to the RF module, and the adequate development environment in terms of software tools and user interfaces. We chose the Xilinx Xtreme DSP board which provides a platform for developing DSP applications using the Virtex II PRO FPGA [6]. Figure 9 illustrates a functional diagram of the board. In this hardware platform the sequential processor and the userdefined circuits are implemented on a single chip. The key features of this board are:

5 Virtex II PRO user FPGA with a hardcoded PowerPC. 2 independent ADC channels (14 bits up to 105 Mbps) 2 independent DAC channels (14 bits up to 160 Mbps) A Virtex II FPGA for clock management. A Spartan FPGA for PCI and USB interface. In our design, the MAC layer of the is written in C and executed in the PowerPC processor of the Virtex II FPGA. The PHY layer is implemented in hardware using the Custom logic of the FPGA. A memory interface is used between the MAC and PHY layer to exchange data as illustrated in Figure 10. wireless network standard named n is expected in the year This will increase transmission speeds to 108 Mbps and beyond using MIMO (Multiple Input Multiple Output) technology. The number of digital processing blocks needed for such MIMO systems increases with the number of RF chains to be processed. Therefore, technical challenges are raised as the hardware complexity of such systems increase dramatically. Some of the questions that are raised are: What is the best combination of configuration parameters for a specific application? What is the complexity cost of their implementation? How a trade-off of performance and complexity can be achieved? Future work will address these questions by presenting performance results using different parameter configurations available in the n standard, such us the number of transmitter and receiver antennas and the different diversity and coding schemes. These results will be obtained through simulations using a complete Matlab model that implements the transmitter and receiver operations over quasi-static channel models. These results will be useful to study the effect of these parameters on specific scenarios, and to estimate the hardware resources needed for practical implementation of such systems. Figure 9 Xilinx Xtreme DSP functional diagram [6] REFERENCES [1] IEEE a: Wireless LAN medium access control (MAC) and Physical Layer (PHY) specifications: high speed physical layer in the 5 GHz band, December 1999 (Revised, 2000). [2] IEEE e: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications Amendment 8: Medium Access Control (MAC) Quality of Service Enhancements, November [3] Khan, Salman, Performance Evaluation of OFDM WLANs with Least Square Error Channel Estimation, Soft Decision Viterbi Decoding and Digital Baseband Spectral Shaping Filter, M.A.Sc. thesis, Dept. of Electrical and Computer Eng., University of British Columbia, Canada, May [4] S. El Housseini, and H. Alnuweiri, "Adaptive Contention-Window MAC Algorithms for QoS-Enabled Wireless LANs", IEEE International Conference on Wireless Networks, Communications and Mobile Computing, Volume 1, June 2005 Page(s): Figure 10. Processor block architecture VI. CONCLUSIONS AND FUTURE WORK In this paper, we have presented a design for the implementation on a FPGA device of a a/g access point. Based on previous reported works, we expect this design to achieve data rates up to 72 Mbit/sec. We also described the Matlab model which contains all functionality for modulation, demodulation and frequency domain equalization. We are in the process of migrating the VHDL code for the PHY transmitter to the Virtex II FPGA, and the C code for the MAC layer to the PowerPC of the same FPGA. [5] Pourmohammadi-Fallah Y., Elfeitori, A., Alnuweiri. H., "A Unified Scheduling Approach for Guaranteed Services over IEEE e Wireless LANs", Broadband Networks, First Int. Conf. on Oct Page(s): [6] Xilinx corporation, Xtreme DSP Developer kit User Guide document reference: NT Dec.-2004, December [7] M. F. Tariq, Y. Baltaci, T. Horseman, M. Butler, and A. Nix, Development of an OFDM based high speed wireless LAN platform using the TI C6x DSP, in IEEE International Conference on Communications, 2002, vol. 1, pp [8] Meeuwsen, M.J., Sattari, O., Baas, B.M., A full-rate software implementation of an IEEE a compliant digital baseband transmitter, IEEE Workshop on Signal Processing Systems, SIPS Page(s): As for future work, an enhancement to the IEEE a/g

6 [9] Manavi, F.; Shayan, Y.R., Implementation of OFDM modem for the physical layer of IEEE a standard based on Xilinx Virtex-II FPGA, IEEE 59th Vehicular Technology Conference, Volume 3, May 2004 Page(s): Vol.3. Hussein Alnuweiri obtained his Ph.D. Degree in 1989 from the University of Southern California. He is currently a Professor in the Department of Electrical and Computer Engineering at the University of British Columbia. His research interests cover all aspects of traffic engineering and quality-ofservice mechanisms in wired and wireless packet networks including constraint-based routing, packet scheduling, switching and routing in optical networks, and real-time multimedia communications. Dr. Alnuweiri has authored or co-authored over 100 journal and conference papers, and holds three US and International patents. Diego Perea-Vega obtained a M.A.Sc. in Electrical Engineering from the University of British Columbia (2000), a B.Sc. in physics from Universidad Nacional de Colombia (1996) and a B.Sc. in electronic engineering from Pontificia Universidad Javeriana (1991). After his M.A.Sc., he worked on the design of DSP algorithms for voice over IP media gateways at Spectrum Signal Processing (Burnaby, BC) and is currently a research engineer in the Department of Electrical and Computer Engineering at the University of British Columbia (Vancouver, BC). Mr. Perea-Vega research interests include digital signal processing applications and the design and implementation of new techniques to optimize the MAC and PHY layers of wireless infrastructure networks.