Design and Implementation of Universal Serial Bus Transceiver with Verilog

Transcription

1 TELKOMNIKA Indonesian Journal of Electrical Engineering Vol.12, No.6, June 2014, pp ~ 4595 DOI: /telkomnika.v12i Design and Implementation of Universal Serial Bus Transceiver with Verilog Liqun Xu, Likun Zheng*, Yali Chen, Zheying Li Beijing Key lab of Information Service, Beijing Union University, Beijing Key lab of Information Service, Information school of Beijing Union University, No.97 Beisihuan East Road Chaoyang District Beijing, China *Corresponding author, zlklovey365@163.com Abstract In this paper, a simplified Universal Serial Bus (USB) transceiver is designed, which is special used for mobile terminals such as smart mobile phone, IPad, smart sensor, and so on. The transceiver includes functions such as data serialization, bit stuffing, NRZI encoding and NRZI decoding, bit unstuffing, deserialization. The transceiver is designed and implemented with Verilog HDL in Modelsim. And the transceiver has been verified with FPGA and synthesized using 0.18um 1P6M CMOS process technology. The simulation and FPGA results show that the transceiver satisfies all design specification and can be used as an IP core for smart mobile terminals. Keyword: universal serial bus (USB), transceiver macrocell interface, verilog HDL Copyright 2014 Institute of Advanced Engineering and Science. All rights reserved. 1. Introduction The Universal Serial Bus (USB) is a device communication standard. For the interface of multimedia data between personal computers and peripheral components, USB has become a kind of mainstream interface technology, and has wide application foreground. With the popularity of mobile terminals, there is growing demand for communication directly between mobile terminals. The new USB has put forward, which is used for interconnection and data transmission between mobile devices [1]. The USB Transceiver Macrocell Interface (UTMI) is one of the important functional blocks of USB controller, which is connected to Serial Interface Engine (SIE) via a 8-bit parallel interface and communicates with the host(pc or Hub) through USB differential cable. UTMI is a bidirectional serial bus interface between USB devices through D+ and D- lines. To satisfy the low power consumption requirement from some smart mobile trerminal application, a simplified UTMI was designed in this paper. The simplified UTMI is only us for single data pipline therefore some circuitry part can be cutoff from nomal UTMI. In this paper, part 2 discussed and designed a USB UTMI circuitry architecture special used for mobile terminals; part3 gave and discussed Verilog HDL simulation and FPGA verification results of the UTMI, and part 4 gives a IP synthesis result. 2. Architecture and Function of USB Transceiver UTMI handles the low level USB protocol and signaling. Figure 1 shows the functional block diagram of the USB transceiver in the USB Transceiver Macrocell Interface specification [3]. It defines three types of UTMI implementations depends on data transmission rates, those are Low Speed (LS)(1.5MHz) only, Full Speed (FS)(12MHz) only and High Speed (HS)(480MHz)/Full speed (FS)(12MHz). In this paper, considering special used for mobile terminals only needs full speed model, the High Speed type is deleted to reduce power consumption of UTMI. The last functional block diagram is shown in Figure 2. Received December 28, 2013; Revised February 27, 2014; Accepted March 13, 2014

2 4590 ISSN: Data+ Data- Rcv Status/ Control HSXCVR Xmit Rcv Status/ Control HS DLL Elasticity Buffer FS DLL Data Recovery M u x NRZI Decoder Receive State Machine Transmit State Machine Bit Unstuffer 8 bit Rx 8 bit Tx 8 bit Rx 8 bit Tx FSXCVR Xmit NRZI Encoder Bit stuffer Analog Front End External Crystal Figure 1. UTM Functional Block Diagram Clock Multiplier Control Logic Figure 2. Functional Block Diagram of USB Transceiver Figure 2 shows the block diagram of USB Transceiver. This includes features such as: data serialization and deserialization, bit stuffing, bit destuffing and clock recovery and synchronization with Full Speed. The parallel data from SIE is taken into the transmit hold register and this data is sent to transmit shift register from where the data is converted serially. This serial data is bit stuffed to perform data transitions for clock recovery and Non Return to Zero Invert(NRZI) encoding. Then the encoded data is sent on to the serial bus. When the data is received on the serial bus, it is decoded, bit unstuffed and is sent to receive shift register. After the shift register is full, the data is sent to receive hold register. This data will be presented on the parallel interface where it is sampled by the SIE The Transmitter Module. The transmitter module has been implemented by considering the following specifications [2-3]. Verilog is used to design the transmitter module. The SYNC pattern has to be transmitted immediately after the transmitter is initiated by the SIE. TELKOMNIKA Vol. 12, No. 6, June 2014:

3 TELKOMNIKA ISSN: After six consecutive 1 s occur in the data stream a zero to be inserted. The data should be encoded using Non Return to Zero Invert (NRZI) on encoding technique. It can effectively prevent the transmission of data appearing continuous and no level change sequence. Figure 3 is shown the timing diagram of signals generated. Figure 3. Timing Diagram of Signals Generated The EOP pattern two single ended zeroes (D+ and D- lines are carrying zero for two clock cycles) and a bit one have to be transmitted after each packet or after SIE suspends the transmitter. The block diagram of the UTMI transmitter model is shown in Figure 4. Figure 4. Block Diagram of the UTMI Transmitter The transmitter module of the UTMI consists of various blocks such as SYNC generator, transmit hold and shift register, bit stuffer, NRZI encoder and EOP generator. A transmit state machine is developed by considering all the states given by USB 2.0 transmit state machine. The transmit state machine is shown in Figure 5. Figure 5. Ttransmit State Machine Design and Implementation of Universal Serial Bus Transceiver with Verilog (Liqun Xu)

4 4592 ISSN: Initially the transmitter is at Reset state where the reset signal is high. If reset signal goes low state the state of the transmitter is changed to Tx_wait state where it is waiting for assertion of Tx_valid signal by the SIE. When the Tx_valid signal is asserted by the SIE, transmit state machine enters into Send Sync state where a signal called of the clock out side the state machine. When this signal is enabled sync enable is asserted. This signal is checked at every rising edge, a sync pattern is send to the NRZI encoder. The data byte placed on the data lines by the SIE sampled by the UTMI at the rising edge of the clock. For this purpose, an 8-bit vector is declared in the entity declaration of the transmitter module. This 8-bit vector is considered as transmit hold and shift register. The transmit hold and shift register is loaded with 8-bit parallel data from SIE at the rising edge of the clock. At this movement the transmit state machine is in Data load state. After the register is loaded, the data is sent to the other modules serially. Each bit of the register is sent to the Bit stuff module. After all the bits are serially sent to the Bit stuff module, Tx_ready signal is asserted by the transmit state machine. During parallel to serial conversion data, the transmit state machine is in Data wait state. When Tx_valid signal is negated by the SIE, the transmit state machine enters into send EOP state where it enables a signal called eop_enable. This signal is checked out side the state machine for every clock. If this signal is high then the EOP pattern: two single ended zeroes (DP, DM lines contain zeroes) and a J ( a 1 on DP line and a 0 on DM line) is transmitted on to DP, DM lines The Receiver Module The receiver module has been implemented by considering the following specifications [2-3]. When SYNC pattern is detected that should be intimated to the SIE. If a zero is not detected after six consecutive 1 s an error should be reported to the SIE. When EOP pattern is detected that should be intimated to the SIE. The block diagram of the UTMI receiver is shown in Figure 6. Figure 6. Block Diagram of the UTMI Receiver The receiver module is designed by considering all the above specifications. Verilog is used to design the receiver module. The receiver module of the UTMI consists of various blocks such as SYNC detector, NRZI decoder, bit unstuffer, receive shift and hold ister and EOP detector. A receive state machine is developed by considering all the states given by USB receive state machine. The receive state machine is shown in Figure 7. Figure 7. Receive State Machine TELKOMNIKA Vol. 12, No. 6, June 2014:

5 TELKOMNIKA ISSN: Initially the receiver is at Reset state where the reset signal is high and Rx_active and Rx_valid signals are low. If reset signal goes low the state of the receiver is changed to Rx_wait state where it is waiting for SYNC pattern. When the receiver detects encoded SYNC pattern , the Receive state machine will enter into strip sync state where the SYNC pattern is stripped off. To detect the SYNC pattern a state machine is developed. It checks every bit for every rising edge of the clock. If the pattern is detected, a signal called sync detected is enabled. This signal is checked by the Receive state machine. If the signal is high, the Receive state machine will enter into strip sync state where Rx_active signal is asserted and the state machine will enter into Rx_data state. The received data on DP, DM lines are NRZI decoded. The NRZI Decoder simply XOR the present bit with the provisionally received bit. During NRZI decoding, the receive state machine is in Rx_wait state. The serial data received from the bit Unstuffer is shifted into the receive shift register. After the shift ister is full, it is held there for one clock duration and then the data is placed on to the data out bus. This 8-bit data is sampled by the SIE at the next rising edge of the clock during shifting, the receive state machine is in Rx_data wait state. During holding, the receive state machine is in Rx_data state where it asserts Rx_valid signal. A state machine is developed for EOP detection, which is invoked at every rising edge of the clock. When two single ended zeroes fallowed by a J state is detected, it asserts a signal called EOP_detect which is checked by the Receive state machine at every rising edge of the clock. When this signal is high, the receive state machine will enter in to Strip eop state where the EOP pattern is stripped off and Rx_active, Rx_valid signals are negated. At the next rising edge of the clock. The Receive state machine will enter into the Rx_wait state. 3. Results and Discussion The Figure 8 shows the Simulation results of UTMI transmitter. When send the data, UTMI need to let txoe signal go low so that the driver is in data send state. At the same time, Tx_Vaild signal goes high, it show that data on parallel lines are waiting to send. Then encoded SYNC pattern is transmitted and the signal txready is asserted. The data present on the data bus is NRZI encoded and transmitted on to the txdp/txdn lines. The signal txready goes low when the data is sampled by the Tx hold register. When a set of data finished UTMI send a eop_done signal and the signal txoe goes high. Figure 8 UTMI Transmitter Module The Figure 9 shows the simulation results of UTMI receiver. When SYNC pattern is detected RxActive is asserted. The data present on rxdp, rxdn lines is decoded, serial to parallel converted and sent to the SIE through data out bus by asserting Rx_Valid signal. The RxActive is invalid show that a set of data completed. This design has been verified utilizing Altera's Cyclone II type EP2C35F672C8 FPGA. Verilog code is synthesized and the downloadable file is generated using Quartus II, through the JTAG download the file to FPGA and debug it. Figure 10 shows the FPGA result. FPGA development board and PHY chip connect to the computer using USB cable, the equipment Design and Implementation of Universal Serial Bus Transceiver with Verilog (Liqun Xu)

6 4594 ISSN: configuration information is obtained by the computer, then the transceiver can properly communicates with computer. Figure 9. UTMI Receiver Module FPGA JTAG Figure 10. FPGA Result 4. Synthesis Implementation The Synopsys company s Synthesis Tool Design Complier[6] is used in the design of the circuit. This process converts the Verilog code to an optimized gate netlist according to correlative design constraints. The most important design constraints are speed and operating conditions. The design has been synthesized using 0.18um 1P6M CMOS process technology, and the timing report and area report are given. Figure 11 Area Report Figure 11 shows the design circuit logic cell is 11k. The report information is used to estimate the chip area. Figure 12 shows the value of slack, the slack describe the difference between the require time and the actual time in timing sequence path. The value is positive illustrates the circuit design conforms to the constraints. TELKOMNIKA Vol. 12, No. 6, June 2014:

7 TELKOMNIKA ISSN: Figure 12. Timing Report 5. Conclusion USB transceiver is an important part of the USB device. The individual modules of USB transceiver have been designed using Verilog and verified functionally with the ModelSim and FPGA. A design tool Verilog HDL and the corresponding synthesis tool are used. It makes a good contribution to the research and development of the USB chip. It also can be used as an IP core in the Soc design. References [1] Jang-Jin Nam, Yong-Jun Kim, Kwang-Hee Choi, Hong-June Park. A UTMI-compatible physical-layer USB2.0 transceiver chip. Soc Conference. Proceedings. IEEE International [Systems-on-Chip. 2003: [2] Universal Serial Bus Specification revision 2.0. HP, Compaq, Intel, Microsoft, Philips, NEC, and Lucent. Mar [3] USB 2.0 Transceiver Macrocell Interface (UTMI) Specification. Intel. version [4] A Vamshidhar Reddy et al, Implementation of USB Transceiver Macrocell Interface. IJRET /P2012_01_03_016.pdf [5] Babulu, K Rajan KS. FPGA Implementation of USB Transceiver Macrocell Interface with USB2.0 Specifications. Emerging Trends in Engineering and Technology, ICETET 08.First International Conference on. 2008: [6] Advanced ASIC chip synthesis: Using Synopsys Design Complier and Prime Time. Second edition. Himanshu Bhanagar. Kluwer Academic Publisher Design and Implementation of Universal Serial Bus Transceiver with Verilog (Liqun Xu)