Stratix V GT Device Design Guidelines

Transcription

1 AN-681 Subscribe Altera s Stratix V devices provide four duplex transceiver GT channels, each capable of a serial data rate up to 8.05 Gbps. Stratix V GT devices support chip-to-chip and chip-to-module applications. The GT transceivers can achieve a very low bit error ratio (BER) of <1e-15 to meet the requirements of high speed serial data applications. This application note assumes you have experience designing for Altera s Stratix V GX transceivers. Building on the Stratix V design guidelines (AN 65) and the Altera Transceiver PHY IP Core User Guide, this document provides specific recommendations for designing with the Stratix V GT channels. It discusses channel loss design to ensure your Stratix V GT system can meet the low BER, GT channel implementation, timing closure design consideration, and dynamic reconfiguration. Related Information AN 65: Stratix V Device Design Guidelines Altera Transceiver PHY IP Core User Guide Channel Loss Design and Case Studies Your system s performance depends to a large extent on how well your board is designed. For your Stratix V GT system to achieve low BER at 8 Gbps, design the boards so the GT links do not exceed -10 db of insertion loss. The link loss is determined by the trace length, board material, via structures, AC coupling capacitors, and any connectors that are part of the link. The board trace impedances must be well matched and the channel losses minimized. Perform an analysis of your GT links as part of the board design process. Stratix V GT channels can drive four inches of stripline Nelco trace with one connector and additional trace at 8 Gbps. This link topology has channel loss comparable to the requirements of the CEI-8G-VSR specifications. Stratix V GT channels may drive longer traces with higher insertion loss at lower data rates. To ensure your link operates at 8 Gbps, keep the link insertion loss to no more than -10 db. For additional margin, reduce the insertion loss even more to provide optimal performance. The table below shows the different link topologies where Stratix V GT channels successfully demonstrated a BER of < 1e-15 at 8 Gbps using the Stratix V GT signal integrity board All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:008 Registered Innovation Drive, San Jose, CA 95134

2 Designing for Stratix V GT Channels Table 1: Stratix V GT BER Test Link Topologies AN-681 Link Topology Direct external loopback on Megtron 6 microstrip trace + MMPX connectors 4 Nelco stripline trace with connector + MMPX connectors 8 Megtron 6 microstrip trace + MMPX connectors 6 LC Rogers microstrip trace + MMPX connectors Estimated Link Insertion Loss (db) (1) Each transceiver link needs optimized analog settings to ensure it meets the low BER. Apply signal conditioning techniques such as adjustments to the transmitter pre-emphasis and receiver equalization to fine-tune the links. Refer to Altera s board design guidelines AN 67 and AN 684 for more information about optimizing your board design for high speed serial links. Related Information AN 67: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission AN 684: Design Guidelines for 100 Gbps - CFP Interface Designing for Stratix V GT Channels The following sections provide recommendations for designing with Stratix V GT channels. Reference Clock Selection For best transmitter jitter performance, use the dedicated reference clocks of the same transceiver bank. Because each transceiver bank provides two dedicated reference clock sources, you can set different reference clocks to drive the ATX PLL and the RX CDR, as shown in the following figure. (1) Insertion loss is estimated and based on layout extraction and VNA measurements.

3 AN-681 Figure 1: Two Dedicated Reference Clock Sources Reference Clock Selection 3 Fractional PLL Reference Clock Line Reference Clock Network Fractional PLL Reference Clock Buffer (1) Fractional PLL ATX PLL N N / Stratix V GX Transceiver Channel Channel PLL Dedicated refclk 1 Transmitter Receiver Dedicated Reference Clock for RX CDR refclk0 Stratix V GT Receiver Channel CDR Receiver Fractional PLL Reference Clock Buffer (1) Fractional PLL ATX PLL () N Stratix V GT Transmitter Channel / CMU PLL (3) Dedicated refclk 0 Transmitter Dedicated Reference Clock for ATX PLL N N Stratix V GX Transceiver Channel Channel PLL Transmitter Receiver Fractional PLL Reference Clock Buffer (1) N (4) Fractional PLL Reference Clock Line Dedicated refclk Reference Clock Network Clocks or Data Unused resource Notes: (1) The fractional PLL refclk buffers allow you to segment the reference clock line into multiple segments, such that fractional PLLs in different transceiver banks can drive the same fractional PLL reference clock line. () The bottom ATX PLL of a GT transceiver bank provides the serial clock to the GT transmitter channel. (3) The CMU PLL of the GT transmitter channel drives an x1 clock line that can be used by the top and bottom GX transceiver channels in the GT transceiver bank. (4) N equals twice the number of GT channels. To minimize the number of reference clock sources required, you can also choose one of the two dedicated reference clocks to drive both the ATX PLL and the RX CDR. In this case, use the dedicated reference clock to drive the ATX PLL directly and use the reference clock network to drive the RX CDR for best performance.

4 4 Low Latency PHY IP Figure : One Dedicated Reference Clock Source AN-681 Fractional PLL Reference Clock Line Reference Clock Network Fractional PLL Reference Clock Buffer (1) Fractional PLL ATX PLL N N / Stratix V GX Transceiver Channel Channel PLL Dedicated refclk 1 Transmitter Receiver Fractional PLL Reference Clock Buffer (1) Fractional PLL ATX PLL () Reference Clock Network for RX CDR N refclk0 Stratix V GT Receiver Channel Stratix V GT Transmitter Channel / CDR CMU PLL (3) Receiver Dedicated refclk 0 Transmitter Dedicated Reference Clock for ATX PLL N N Stratix V GX Transceiver Channel Channel PLL Transmitter Receiver Fractional PLL Reference Clock Buffer (1) N (4) Fractional PLL Reference Clock Line Dedicated refclk Reference Clock Network Clocks or Data Unused resource Notes: (1) The fractional PLL refclk buffers allow you to segment the reference clock line into multiple segments, such that fractional PLLs in different transceiver banks can drive the same fractional PLL reference clock line. () The bottom ATX PLL of a GT transceiver bank provides the serial clock to the GT transmitter channel. (3) The CMU PLL of the GT transmitter channel drives an x1 clock line that can be used by the top and bottom GX transceiver channels in the GT transceiver bank. (4) N equals twice the number of GT channels. Low Latency PHY IP Each GT transceiver bank supports one GT channel that can operate as a duplex, TX, or RX channel. Stratix V GT channels are implemented in a physical medium attachment (PMA) direct mode using the Altera transceiver Low Latency PHY IP. Each channel requires its own PHY IP instantiation, which can be either a duplex or simplex channel. The following figure shows the transceiver bank locations for Stratix V GT devices.

5 AN-681 Low Latency PHY IP 5 Figure 3: Transceiver Bank Locations GXB_L3 6 Ch 3 Ch 1 GTB GXB GTB_R3 Ch GXB Ch 1 GTB Ch 0 GXB GXB_L 6 Ch 3 Ch 1 GTB GXB GTB_R GXB_L1 GXB_L0 6 Ch 6 Ch PCIe Hard IP 3 Ch 1 GTB GXB 3 Ch 1 GTB GXB GTB_R1 GTB_R0 Transceiver Bank Names Number of Channels Per Bank Number of Channels Per Bank Transceiver Bank Names Notes: 1. GT transceiver banks are made up of 1 GT channel and GX channels. The GT channel is the middle channel in the bank.. GT devices only come with one PCIe HIP block located across GX banks L0 and L1. The following figures show the MegaWizard Plug-In Manager instantiating a Low Latency PHY IP to implement a duplex GT channel running at 8 Gbps. Enter the appropriate settings for your specific design requirements.

6 6 Low Latency PHY IP Figure 4: MegaWizard General Tab for Low Latency PHY IP GT channels have a 18-bit width and require a GT data path and an ATX PLL. AN-681

7 AN-681 Figure 5: MegaWizard Additional Options Tab for Low Latency PHY IP Low Latency PHY IP 7

8 8 Low Latency PHY IP Figure 6: MegaWizard Reconfiguration Tab for Low Latency PHY IP The messages in the bottom pane provide information about the reconfiguration interfaces. AN-681

9 AN-681 Figure 7: MegaWizard Analog Options Tab for Low Latency PHY IP Reconfiguration Controller 9 Note: The Altera 40G/100G Ethernet PHY IP for CAUI-4 (4x5) will instantiate the GT channels automatically. If you want to integrate the Low Latency PHY IP into your Qsys design, you must create a Qsys component for the Low Latency PHY IP. After the Low Latency PHY IP component is created, you can connect it to other components in your Qsys design. Refer to the Qsys documentation for creating a component. Related Information Creating Qsys Components Refer to the "Stratix V GT Device Configurations" section of the Transceiver Configurations in Stratix V Devices chapter Reconfiguration Controller The reconfiguration controller provides a number of features that are used for calibrating the transceiver PLLs and for tuning the channels using dynamic reconfiguration. Every transceiver PHY IP instance must be connected to a transceiver reconfiguration controller. If the GX channels and the GT channel from the same transceiver bank are used, they must be connected to the same reconfiguration controller. For simplicity, you can connect all the transceiver PHY IP instances, including those from other banks, to the same reconfiguration controller.

10 10 Logical Channel Mapping In the following figure, the MegaWizard Plug-In Manager is used to connect four duplex GT channels to the reconfiguration controller. This design requires 1 interfaces because each duplex GT channel consists of three logical interfaces: RX, TX, and ATX PLL. The interfaces are bundled as four separate groups, one for each GT channel. Bundling the interfaces into groups makes the connections between the reconfiguration controller and the GT channel more straightforward. The Enable channel/pll reconfiguration option in the Reconfiguration Features section must be turned on for the GT channels. This setting enables the MIF mode streamer module, which allows dynamic reconfiguration of the GT channels. The Analog Features section is for the GX channels. Turn on the analog features options that you want to implement for your GX channels. Figure 8: Transceiver Reconfiguration Controller for GT Channels AN-681 Logical Channel Mapping The RX, TX, and ATX PLL of each transceiver PHY IP are each assigned a logical channel address that uniquely identifies it. The logical channel address allows you to access a specific channel through the reconfiguration controller to perform dynamic reconfiguration. This logical mapping is based on the PHY IP instances, such as duplex or simplex, and the order in which they are connected to the reconfiguration controller. The following figure shows the fitter report of the logical channel mapping information for a design with four duplex GT channels. You will need this information when you perform dynamic reconfiguration.

11 AN-681 Figure 9: Logical Channel Mapping Example Timing Closure 11 Timing Closure Closing timing ensures your design functions correctly by meeting setup and hold requirements. In general, the Quartus II software can place and route the GT channels and close timing without any special design accommodation. The following figure shows the TX and RX parallel recovered clocks and the parallel data bus size for the register transfer between the PMA and the core. The parallel clocks, tx_clkout and rx_clkout, are inverted in the PMA before they drive the core.

12 1 Dynamic Reconfiguration Figure 10: Stratix V GT Channel PMA and Core Register Transfer AN-681 FPGA Fabric (Core) Transmitter PMA Register tx_parallel_data 18 Serializer tx_serial_data Invert parallel clock to provide full clock cycle tx_clkout Divider Receiver PMA ATX PLL Register rx_parallel_data 18 Deserializer CDR rx_serial_data rx_clkout Parallel Clock Serial Clock You can close timing for the RX PMA to core transfer in a half clock cycle, so no special design accommodation is required. However, the core to TX PMA transfer may require an extra half clock cycle because of the delay associated with the clock and data running in opposite directions. Closing timing can be challenging at these high data rates, especially with the 18-bit data width. A simple approach to provide more time for the transfer is to invert the tx_clkout before driving it to the core. Applying this design technique provides a full clock cycle for the core to TX PMA register transfer. Dynamic Reconfiguration Dynamic reconfiguration allows you to change the transceiver settings without performing a full reconfiguration of the device. Accessing the feature is done through the reconfiguration controller, which has a set of memory mapped registers. The following figure shows an example of a system block diagram of the reconfiguration controller and how it interfaces with the transceiver PHY IP.

13 AN-681 Figure 11: System Block Diagram Dynamic Reconfiguration 13 Altera V-Series FPGA User Application Including MAC Streaming Data Transceiver PHY TX and RX Serial Data Reconfiguration Management Interface to and from Embedded Controller S Transceiver Reconfiguration Controller Master M M reconfig_from_xcvr[<n>:0] reconfig_to_xcvr[<n>:0] S... Registers to reconfigure... reconfig_mif_address[31:0] reconfig_mif_read S MIF ROM reconfig_mif_readdata[15:0] reconfig_mif_waitrequest M Avalon-MM master interface S Avalon-MM slave interface The following figure shows the reconfiguration controller and the various features that are available for the transceiver channels. For the Stratix V GT channel, dynamic reconfiguration is accessed through the streamer module, which is enabled by checking the Channel/PLL Reconfiguration option during the reconfiguration controller IP instantiation.

14 14 Streamer Module Figure 1: Transceiver Reconfiguration Controller AN-681 Transceiver Reconfiguration Controller Signal Integrity Features Address Offset PMA Analog 0x00 Avalon-MM Registers PMA 0x0B EyeQ (1)... EyeQ (1) 0x13 DFE Embedded Controller M Direct Addressing Avalon-MM Interface reconfig_mgmt_* S 0x7F... DFE... ADCE... ATX... Streamer... PLL... 0x1B 0xB 0x33 0x3B 0x43 ADCE ATX Tuning MIF Streamer MIF streamer module (mode 3) allows dynamic reconfiguration of the GT channel PLL Reconfig Note: (1) EyeQ for GT channels is available as a demo feature using the Quartus II Transceiver Toolkit. To access EyeQ for GX channels, refer to the Altera Transceiver PHY IP Core User Guide. Related Information Altera Transceiver PHY IP Core User Guide Streamer Module The following table lists the addresses for the streamer module memory mapped registers and describes the functions of each register. For the Stratix V GT channel, dynamic reconfiguration is performed using MIF mode 3, which is different from the regular modes described in the Altera Transceiver PHY IP Core User Guide. MIF mode 3 gives you direct access to the actual hardware registers. You must perform read modified write (RMW) operations when using this mode. Select MIF mode 3 by writing b11 to address 0x3A bits [3:]. Table : Streamer Module Register Address Register Name PHY Address Bits R/W Description Logical channel number 7'h38 [9:0] RW The logical channel number.

15 AN-681 Offsets 15 Register Name PHY Address Bits R/W Description Physical channel address 7'h39 [9:0] R The physical channel number. You must initiate an indirect read before you can correctly read the physical channel number. [9] R Error flag. Indicates one of following: Channel address is invalid, PHY address is invalid, or Offset register address is invalid. [8] R Busy flag. Indicates reconfiguration in progress. Control and status 7'h3A [3:] RW 'b00: MIF file 'b01: Direct write 'b10: Reserved 'b11: MIF mode 3 direct physical address [1] W Read. Initiate an indirect read. Self clear. [0] W Write. Initiate an indirect write. Self clear. Offset 7'h3B [15:0] RW Specify the parameter offset address. Data 7'h3C [31:0] RW Reads back or specifies value of the parameter. Offsets The transceiver PHY IP (RX, TX, and ATX PLL) contains a set of memory mapped registers, called offsets, which correspond to the different analog parameters. In the following table, the Offset column lists the transceiver PHY IP offset address for each parameter. Only a subset of the bits for each offset register is defined. For example, the TX VOD offset address is at 0x8C and only bits [6:] are defined for the VOD parameter setting. Some parameters, such as RX DC Gain and RX AC Gain, are defined across multiple offsets. Table 3: Stratix V GT Channel Offsets Parameter Offset Comment TX Termination TX Common Mode TX VOD TX Main Tap Switches TX Pre-Tap TX Pre-Tap Switches 0x8B[11:8] 0x8B[6:3] 0x8C[6:] 0x8E[9:6] 0x8E[14:10] 0x4E9[1:0] Fine tune 100 Ω termination Switches depend on VOD setting Switches depend on pre-tap setting

16 16 Switches and Valid Settings AN-681 Parameter Offset Comment TX Pre-Tap Invert TX Post-Tap TX Post-Tap Switches RX Termination RX Common Mode RX DC Gain RX AC Gain RX Eye Enable RX Eye Phase Step RX Eye Vertical Step 0x8F[6] 0x8F[4:0] 0x4E9[3:] 0x37[9:6] 0x37[13:10] 0x34[7:],0x34[0] 0x35[15:0],0x34[15:8] 0x36[9] 0x90[15:10] 0x36[15:10] Switches depend on post-tap setting Fine tune 100 Ω termination Note: When you perform a dynamic reconfiguration, you must perform a read-modify-write operation to an offset register and avoid corrupting other bits. Inadvertently modifying other bits may change the transceiver setting and render the channel non-functional. For a list of the Stratix V GT channel offset addresses and the bit setting values, refer to Appendix A. Related Information Appendix A Offset Addresses on page 0 Switches and Valid Settings The Stratix V GT TX channel contains switches for the main tap, pre-tap, and post-tap. Enabling more switches means more drive current, which requires higher power. Based on the tap settings in your design, the Quartus II software sets the appropriate number of switches to provide optimal performance while minimizing power consumption. However, when you perform dynamic reconfiguration to change the main-tap, pre-tap, and the post-tap settings, you must ensure that those combinations and the number of switches are valid. Invalid combinations of settings and switches may result in overstressing the TX buffer. To ensure the device is operating under optimal conditions, adhere to two sets of rules. The first defines how many switches you must enable to avoid overstressing the TX buffer, as shown in the following figure. By default, the Quartus II software sets the TX VOD (main-tap) to 6 ma (600 mv) with two switches enabled. The same table applies to the pre-tap and post-tap settings. For example, if the pre-tap or post-tap setting is ma (a Quartus II setting of 10 or less), only one switch needs to be enabled. If the setting is > ma (a Quartus II setting of 11 or higher), then both switches must be enabled.

17 AN-681 Figure 13: Valid TX VOD Settings Switches and Valid Settings 17 The second set of rules ensures that the combination of TX VOD and pre-emphasis settings are valid. The V max and V min for the VOD are calculated based on 100 Ω termination. 1. a + b + c 1 ma. b a c > 1.65 ma 3. (V max / V min 1)% < 600% where: a = Pre-tap setting in ma (in steps of 0. ma) b = TX VOD setting in ma (in steps of ma) c = Post-tap setting in ma (in steps of 0. ma) V max = R termination * ( a + b + c ) V min = R termination * ( b a c ) Example 1. The Quartus II software has the following default settings: Pre-tap: a = 0 ma (0 * 0. ma) TX VOD: b = 6 ma (3 * ma) Post-tap: c = 1 ma (5 * 0. ma) The second set of rules is met as follows: 1. a + b + c = 0 ma + 6 ma + 1 ma = 7mA, which is 1 ma. b a c = 6 ma - 0 ma 1 ma = 5 ma, which is > 1.65 ma 3. (V max / V min 1)% = ((100 Ω * 7 ma) / (100 Ω * 5 ma) 1)% = 40%, which is < 600% Example. In this example, one of the rules is violated. Pre-tap: a = 1 ma (5 * 0. ma) TX VOD: b = 4 ma ( * ma) Post-tap: c = 1.6 ma (8 * 0. ma)

18 18 Performing Dynamic Reconfiguration The values for the second set of rules are calculated as follows: 1. a + b + c = 1 ma + 4 ma ma = 6.6 ma, which is 1 ma. b a c = 4 ma 1 ma 1.6 ma = 1.4 ma, which is < 1.65 ma [violates rule] 3. (V max / V min 1)% = ((100 Ω * 6.6 ma) / (100 Ω * 1.4 ma) 1)% = 371%, which is < 600% AN-681 In Example, you can reduce the pre-tap or post-tap setting or you can increase the TX VOD setting so the rules are met. When performing dynamic reconfiguration, follow both sets of rules to ensure the GT channel operates at its optimal condition. Performing Dynamic Reconfiguration To perform a dynamic reconfiguration of the GT channels, apply a sequence of read and write operations to the streamer module registers of the reconfiguration controller. Use the following procedure to change the analog settings of the GT channel: 1. Write logical channel. Write control/status register to specify MIF mode 3 3. Write offset register to select parameter 4. Initiate indirect read; results stored in data register 5. Read current parameter value from data register 6. Modify parameter value 7. Write data register with new parameter value 8. Initiate indirect write 9. Read control/status register and check if busy signal (bit 8) is cleared The following Tcl script examples demonstrate dynamic reconfiguration of the Stratix V GT channel. Only a portion of the complete code is shown for simplicity. The first example shows how to change the GT channel TX VOD setting from the default 3 (600 mv) to (400 mv). The second example shows how to enable or disable the reverse serial loopback. Multiple offset addresses are accessed to enable and disable the reverse serial loopbacks. For the complete Tcl scripts of the two examples that you can run with the system console, refer to Appendix B and Appendix C. Example 1. Excerpts of Tcl Script to Change Stratix V GT TX VOD Setting to # Define reconfiguration controller base address, VOD offset # address, mask, start bit, and VOD value (0x3) set ADDR_RECONFIG 0x0000 set ADDR_TXVOD 0x8c set MASK_TXVOD 0xffffff83 set STARTBIT_TXVOD set value 0x3 # Write logical channel; for one duplex channel, # TX logical channel = 1 wr3 $ADDR_RECONFIG 0x38 1 # Write control/status register to specify MIF mode 3; 0xc = 4'b1100 wr3 $ADDR_RECONFIG 0x3a 0xc # Write offset register to select parameter; VOD offset is 0x8c wr3 $ADDR_RECONFIG 0x3b $ADDR_TXVOD # Initiate indirect read, 0xe = 4'b1110; results are stored in

19 AN-681 Performing Dynamic Reconfiguration 19 # data register wr3 $ADDR_RECONFIG 0x3a 0xe # Read current parameter value from data register, and modify # parameter value set curval [rd3 $ADDR_RECONFIG 0x3c] set tmpval [expr $curval & $MASK_TXVOD] set newval [expr $tmpval ($value << $STARTBIT_TXVOD)] set hexval [format "0x%x" $newval] # Write data register with new parameter value wr3 $ADDR_RECONFIG 0x3c $hexval # Initiate indirect write; 0xd = 4'b1101 wr3 $ADDR_RECONFIG 0x3a 0xd # Read control/status register and check if busy signal (bit 8) # is cleared set busy [rd3 $ADDR_RECONFIG 0x3a] while {($busy & 0x100) == 0x100 { puts "Reconfiguration controller busy." Example. Excerpts of Tcl Script to Enable and Disable Stratix V GT Channel Reverse Serial Loopback # Procedure for setting reverse serial loopback; arguments are # physical channel and loopback type proc setrslpbk {chan setting { # Reconfiguration controller base address and reverse serial # loopback offsets and values set ADDR_RECONFIG 0x0000 set ADDR_RXRSLPBKA 0x8c set ADDR_RXRSLPBKB 0x33 set ADDR_TXRSLPBK 0x8b set MASK_RXRSLPBKA 0xffffff5f set MASK_RXRSLPBKB 0xfffffffb set MASK_TXRSLPBK 0xffffcfff set STARTBIT_RXRSLPBKA 5 set STARTBIT_RXRSLPBKB set STARTBIT_TXRSLPBK 1 switch $setting { "postcdr" { set rxvaluea 0x5 set rxvalueb 0x0 set txvalue 0x3 "precdr" { set rxvaluea 0x0 set rxvalueb 0x1 set txvalue 0x0 "disable" { set rxvaluea 0x0 set rxvalueb 0x0 set txvalue 0x0 default { puts "Invalid reverse serial loopback setting (must be \"postcdr\", \"precdr\", or \"disable\")" return

20 0 Appendix A Offset Addresses # Calculate logical channel set rxchan [ expr 3*$chan + 0 ] set txchan [ expr 3*$chan + 1 ] # Reconfigure transceiver to change reverse serial loopback setting write $ADDR_RECONFIG $rxchan $ADDR_RXRSLPBKA $MASK_RXRSLPBKA $STARTBIT_RXRSLPBKA $rxvaluea write $ADDR_RECONFIG $rxchan $ADDR_RXRSLPBKB $MASK_RXRSLPBKB $STARTBIT_RXRSLPBKB $rxvalueb write $ADDR_RECONFIG $txchan $ADDR_TXRSLPBK $MASK_TXRSLPBK $STARTBIT_TXRSLPBK $txvalue AN-681 Appendix A Offset Addresses The following tables list the offset address and bit setting values for the Stratix V GT channel. Items in bold are default settings. Refer to the Dynamic Reconfiguration section for further explanations about legal combination of settings. Table 4: Loopback Types Serial loopback Loopback Type Reverse serial loopback enable (includes CDR) Reverse serial pre-cdr loopback enable Disable reverse serial loopbacks Offset Address and Bit Setting Use PHY management register access to enable/disable serial loopback for PHY IP instance Offset address: 0x61 (0=disable, 1=enable) Enabling serial loopback overrides reverse serial loopbacks RX: 0x8C[7]=1, 0x8C[5]=1, 0x33[]=0 TX: 0x8B[13:1]=11 RX: 0x8C[7]=0, 0x8C[5]=0, 0x33[]=1 TX: 0x8B[13:1]=00 RX: 0x8C[7]=0, 0x8C[5]=0, 0x33[]=0 TX: 0x8B[13:1]=00 Table 5: TX Termination The default setting provides 100-Ω termination. TX Termination (Quartus II Setting) 0 1 0x8B[11:8] Value R_SETTING_16 R_SETTING_15 R_SETTING_14

21 AN-681 Appendix A Offset Addresses 1 TX Termination (Quartus II Setting) x8B[11:8] Value R_SETTING_13 R_SETTING_1 R_SETTING_11 R_SETTING_10 R_SETTING_9 R_SETTING_8 R_SETTING_7 R_SETTING_6 R_SETTING_5 R_SETTING_4 R_SETTING_3 R_SETTING_ R_SETTING_1 Table 6: TX Common Mode TX Common Mode (Quartus II Setting) VOLT_0P80V VOLT_0P75V VOLT_0P70V VOLT_0P65V VOLT_0P60V VOLT_0P55V VOLT_0P50V VOLT_0P35V 0x8B[6:3] Table 7: TX VOD The actual output voltage depends on the termination resistor setting. TX VOD 0x8C[6:] (Quartus II Setting) Value ma

22 Appendix A Offset Addresses AN-681 TX VOD (Quartus II Setting) x8C[6:] Value ma 4 ma 6 ma 8 ma 10 ma Table 8: TX Main Tap Switches TX Main Tap Switches No switches on One switch on Two switches on Three switches on Four switches on 0x8E[9:6] Table 9: TX Pre-Tap Values TX Pre-Tap (Quartus II Setting) x8E[14:10] Value 0 ma 0. ma 0.4 ma 0.6 ma 0.8 ma 1.0 ma 1. ma 1.4 ma 1.6 ma 1.8 ma.0 ma

23 AN-681 Appendix A Offset Addresses 3 TX Pre-Tap (Quartus II Setting) x8E[14:10] Value. ma.4 ma.6 ma.8 ma 3.0 ma Table 10: TX Pre-Tap Switches TX Pre-Tap Switches No switches on One switch on Two switches on 0x4E9[1:0] Table 11: TX Pre-Tap Invert TX Pre-Tap Invert (Quartus II Setting) Off On 0x8F[6] 0 1 Table 1: TX Post-Tap Values TX Post-Tap (Quartus II Setting) x8F[4:0] Value Disabled 0. ma 0.4 ma 0.6 ma 0.8 ma 1.0 ma 1. ma 1.4 ma 1.6 ma

24 4 Appendix A Offset Addresses AN-681 TX Post-Tap (Quartus II Setting) x8F[4:0] Value 1.8 ma.0 ma. ma.4 ma.6 ma.8 ma 3.0 ma 3. ma 3.4 ma 3.6 ma 3.8 ma 4.0 ma 4. ma 4.4 ma 4.6 ma 4.8 ma 5.0 ma 5. ma 5.4 ma 5.6 ma 5.8 ma 6.0 ma 6. ma Table 13: TX Post-Tap Switches TX Post-Tap Switches No switches on One switch on 0x4E9[3:] 00 01

25 AN-681 Appendix A Offset Addresses 5 TX Post-Tap Switches Two switches on 0x4E9[3:] 11 Table 14: RX Termination Value The default setting provides 100-Ω termination. RX Termination (Quartus II Setting) x37[9:6] Value MIN_RTERM RTERM_1 RTERM_ RTERM_3 RTERM_4 RTERM_5 RTERM_6 RTERM_7 DEF_RTERM RTERM_9 RTERM_10 RTERM_11 RTERM_1 RTERM_13 RTERM_14 MAX_RTERM Table 15: RX Common Mode RX Common Mode (Quartus II Setting) VTT_0P8V VTT_0P75V VTT_0P7V VTT_0P65V VTT_0P6V VTT_0P55V 0x37[13:10]

26 6 Appendix A Offset Addresses AN-681 RX Common Mode (Quartus II Setting) VTT_0P5V VTT_0P35V 0x37[13:10] Table 16: RX DC Gain The DC gains are based on simulation results. RX DC Gain (Quartus II Setting) x34[7:],0x34[0] , , , , , , , , , , , , , , , , , , , ,1 Value -.1 db -1.3 db -0.7 db -0. db 0.6 db 1. db 1.7 db.5 db 3.1 db 3.6 db 5.6 db 5.9 db 6.1 db 6.3 db 6.5 db 6.7 db 6.9 db 7. db 7.4 db 7.6 db

27 AN-681 Table 17: RX AC Gain Appendix A Offset Addresses 7 The AC gains are based on simulation results. RX AC Gain (Quartus II Setting) 0x35[15:0],0x34[15:8] Value (at 9.5 GHz) , , , , , , , , , db 11.8 db 1.1 db 1.4 db 1.6 db 1.9 db 13.1 db 13.4 db 13.9 db Table 18: RX Eye Enable RX Eye Enable Disable Enable 0x36[9] 0 1 Table 19: RX Eye Phase Step RX Eye Phase Step x90[15:10] Value STEP1 STEP STEP3 STEP4 STEP5 STEP6 STEP7 STEP8 STEP9 STEP10

28 8 Appendix A Offset Addresses AN-681 RX Eye Phase Step x90[15:10] Value STEP11 STEP1 STEP13 STEP14 STEP15 STEP16 STEP17 STEP18 STEP19 STEP0 STEP1 STEP STEP3 STEP4 STEP5 STEP6 STEP7 STEP8 STEP9 STEP30 STEP31 STEP3 STEP33 STEP34 STEP35 STEP36 STEP37 STEP38

29 AN-681 Appendix A Offset Addresses 9 RX Eye Phase Step x90[15:10] Value STEP39 STEP40 STEP41 STEP4 STEP43 STEP44 STEP45 STEP46 STEP47 STEP48 STEP49 STEP50 STEP51 STEP5 STEP53 STEP54 STEP55 STEP56 STEP57 STEP58 STEP59 STEP60 STEP61 STEP6 STEP63 STEP64

30 30 Appendix A Offset Addresses Table 0: RX Eye Vertical Step AN-681 RX Eye Vertical Step x36[15:10] Value VERT_0MV VERT_10MV VERT_0MV VERT_30MV VERT_40MV VERT_50MV VERT_60MV VERT_70MV VERT_80MV VERT_90MV VERT_100MV VERT_110MV VERT_10MV VERT_130MV VERT_140MV VERT_150MV VERT_160MV VERT_170MV VERT_180MV VERT_190MV VERT_00MV VERT_10MV VERT_0MV VERT_30MV VERT_40MV VERT_50MV VERT_60MV

31 AN-681 Appendix A Offset Addresses 31 RX Eye Vertical Step x36[15:10] Value VERT_70MV VERT_80MV VERT_90MV VERT_300MV VERT_310MV VERT_30MV VERT_330MV VERT_340MV VERT_350MV VERT_360MV VERT_370MV VERT_380MV VERT_390MV VERT_400MV VERT_410MV VERT_40MV VERT_430MV VERT_440MV VERT_450MV VERT_460MV VERT_470MV VERT_480MV VERT_490MV VERT_500MV VERT_510MV VERT_50MV VERT_530MV VERT_540MV

32 3 Appendix B Example 1 AN-681 RX Eye Vertical Step x36[15:10] Value VERT_550MV VERT_560MV VERT_570MV VERT_580MV VERT_590MV VERT_600MV VERT_610MV VERT_60MV VERT_630MV Related Information Dynamic Reconfiguration on page 1 Appendix B Example 1 Example 1 provides an executable system console Tcl script that applies dynamic reconfiguration to change the Stratix V GT channel TX VOD setting from the default value 3 (600 mv) to (400 mv) # Procedure to open JTAG connection proc open_jtag { { set path [ lindex [ get_service_paths master ] 0 ] open_service master $path # Procedure to close JTAG connection proc close_jtag { { set path [ lindex [ get_service_paths master ] 0 ] close_service master $path # Procedure to read from Avalon memory mapped register proc rd3 {base offset { set path [ lindex [ get_service_paths master ] 0 ] set address [format "0x%x" [expr $base + ($offset<<)]] set val [ master_read_3 $path $address 1 ] puts "Reading address = $offset ($address); value = $val" return $val # Procedure to write to Avalon memory mapped register proc wr3 {base offset value { set path [ lindex [ get_service_paths master ] 0 ] set address [format "0x%x" [expr $base + ($offset<<)]] set val [format "0x%x" $value] puts "Writing address = $offset ($address); value = $val" master_write_3 $path $address $val

33 AN-681 Appendix C Example 33 # Define reconfiguration controller base address, VOD offset # address, mask, start bit, and VOD value (0x3) set ADDR_RECONFIG 0x0000 set ADDR_TXVOD 0x8c set MASK_TXVOD 0xffffff83 set STARTBIT_TXVOD set value 0x3 # Write logical channel; for one duplex channel, # TX logical channel = 1 wr3 $ADDR_RECONFIG 0x38 1 # Write control/status register to specify MIF mode 3; 0xc = 4'b1100 wr3 $ADDR_RECONFIG 0x3a 0xc # Write offset register to select parameter; VOD offset is 0x8c wr3 $ADDR_RECONFIG 0x3b $ADDR_TXVOD # Initiate indirect read, 0xe = 4'b1110; results are stored in # data register wr3 $ADDR_RECONFIG 0x3a 0xe # Read current parameter value from data register, and modify # parameter value set curval [rd3 $ADDR_RECONFIG 0x3c] set tmpval [expr $curval & $MASK_TXVOD] set newval [expr $tmpval ($value << $STARTBIT_TXVOD)] set hexval [format "0x%x" $newval] # Write data register with new parameter value wr3 $ADDR_RECONFIG 0x3c $hexval # Initiate indirect write; 0xd = 4'b1101 wr3 $ADDR_RECONFIG 0x3a 0xd # Read control/status register and check if busy signal (bit 8) # is cleared set busy [rd3 $ADDR_RECONFIG 0x3a] while {($busy & 0x100) == 0x100 { puts "Reconfiguration controller busy." Appendix C Example Example provides an executable system console Tcl script that applies dynamic reconfiguration to enable and disable the Stratix V GT Channel reverse serial loopbacks. After executing the Tcl script in the system console, run any of the following commands to enable or disable the loopbacks. Replace the <physical_channel> with the appropriate channel number. setrslpbk <physical_channel> postcdr setrslpbk <physical_channel> precdr setrslpbk <physical_channel> disable # Procedure to open JTAG connection proc open_jtag { { set path [ lindex [ get_service_paths master ] 0 ] open_service master $path

34 34 Appendix C Example AN-681 # Procedure to close JTAG connection proc close_jtag { { set path [ lindex [ get_service_paths master ] 0 ] close_service master $path # Procedure to read from Avalon memory mapped register proc rd3 {base offset { set path [ lindex [ get_service_paths master ] 0 ] set address [format "0x%x" [expr $base + ($offset<<)]] set val [ master_read_3 $path $address 1 ] puts "Reading address = $offset ($address); value = $val" return $val # Procedure to write to Avalon memory mapped register proc wr3 {base offset value { set path [ lindex [ get_service_paths master ] 0 ] set address [format "0x%x" [expr $base + ($offset<<)]] set val [format "0x%x" $value] puts "Writing address = $offset ($address); value = $val" master_write_3 $path $address $val # Procedure for writing to reconfiguration controller to perform # dynamic reconfiguration proc write {base chan offset mask startbit value { open_jtag wr3 $base 0x38 $chan wr3 $base 0x3a 0xc wr3 $base 0x3b $offset wr3 $base 0x3a 0xe set curval [rd3 $base 0x3c] set tmpval [expr $curval & $mask] set newval [expr $tmpval ($value << $startbit)] set hexval [format "0x%x" $newval] wr3 $base 0x3c $hexval wr3 $base 0x3a 0xd set busy [rd3 $base 0x3a] while {($busy & 0x100) == 0x100 { puts "Reconfiguration controller busy." close_jtag # Procedure for reading from PHY IP through the reconfiguration # controller proc read {base chan offset mask startbit { open_jtag wr3 $base 0x38 $chan wr3 $base 0x3a 0xc wr3 $base 0x3b $offset wr3 $base 0x3a 0xe set busy [rd3 $base 0x3a] while {($busy & 0x100) == 0x100 { puts "Reconfiguration controller busy." set tmpmask [expr $mask ^ 0xffffffff] set curval [rd3 $base 0x3c] set tmpval [expr ($tmpmask & $curval) >> $startbit] set hexval [format "0x%x" $tmpval] close_jtag return $hexval

35 AN-681 # Procedure for setting reverse serial loopback; arguments are # physical channel and loopback type proc setrslpbk {chan setting { # Reconfiguration controller base address and reverse serial # loopback offsets and values set ADDR_RECONFIG 0x0000 set ADDR_RXRSLPBKA 0x8c set ADDR_RXRSLPBKB 0x33 set ADDR_TXRSLPBK 0x8b set MASK_RXRSLPBKA 0xffffff5f set MASK_RXRSLPBKB 0xfffffffb set MASK_TXRSLPBK 0xffffcfff set STARTBIT_RXRSLPBKA 5 set STARTBIT_RXRSLPBKB set STARTBIT_TXRSLPBK 1 switch $setting { "postcdr" { set rxvaluea 0x5 set rxvalueb 0x0 set txvalue 0x3 "precdr" { set rxvaluea 0x0 set rxvalueb 0x1 set txvalue 0x0 "disable" { set rxvaluea 0x0 set rxvalueb 0x0 set txvalue 0x0 default { puts "Invalid reverse serial loopback setting (must be \"postcdr\", \"precdr\", or \"disable\")" return # Calculate logical channel set rxchan [ expr 3*$chan + 0 ] set txchan [ expr 3*$chan + 1 ] Document Revision History # Reconfigure transceiver to change reverse serial loopback setting write $ADDR_RECONFIG $rxchan $ADDR_RXRSLPBKA $MASK_RXRSLPBKA $STARTBIT_RXRSLPBKA $rxvaluea write $ADDR_RECONFIG $rxchan $ADDR_RXRSLPBKB $MASK_RXRSLPBKB $STARTBIT_RXRSLPBKB $rxvalueb write $ADDR_RECONFIG $txchan $ADDR_TXRSLPBK $MASK_TXRSLPBK $STARTBIT_TXRSLPBK $txvalue 35 Document Revision History Table 1: Document Revision History Date January 014 Version Changes Added note to Figure 1. Removed "EyeQ for Stratix V GT Channels" section.

36 36 Document Revision History AN-681 Date March 013 Version Initial release. Changes