Arria 10 Device Datasheet

Transcription

1 Subscribe This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Arria 10 devices. Arria 10 devices are offered in extended and industrial grades. Extended devices are offered in E1 (fastest), E2, and E3 speed grades. Industrial grade devices are offered in the I1, I2, and I3 speed grades. The suffix after the speed grade denotes the power options offered in Arria 10 devices. L Low static power S Standard power M Enabled with the V CC PowerManager feature (you can power V CC and V CCP at nominal voltage of 0.90 V or lower voltage of 0.83 V) V Supported with the SmartVID feature (lowest static power) Related Information Arria 10 Device Overview Provides more information about the densities and packages of devices in the Arria 10 family. Electrical Characteristics The following sections describe the operating conditions and power consumption of Arria 10 devices. Operating Conditions Arria 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Arria 10 devices, you must consider the operating requirements described in this section All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered Innovation Drive, San Jose, CA 95134

2 2 Absolute Maximum Ratings Absolute Maximum Ratings This section defines the maximum operating conditions for Arria 10 devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions. Caution: Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Table 1: Absolute Maximum Ratings for Arria 10 Devices Preliminary Symbol Description Condition Minimum Maximum Unit V CC Core voltage power supply V V CCP Periphery circuitry and transceiver fabric interface power supply V V CCERAM Embedded memory power supply V V CCPT V CCBAT Power supply for programmable power technology and I/O pre-driver Battery back-up power supply for design security volatile key register V V V CCPGM Configuration pins power supply (1) V V CCIO I/O buffers power supply 3 V I/O V LVDS I/O V V CCA_PLL Phase-locked loop (PLL) analog power supply V V CCT_GXB Transmitter power V V CCR_GXB Receiver power V V CCH_GXB Transmitter output buffer power V V CCL_HPS HPS core voltage and periphery circuitry power supply V V CCIO_HPS HPS I/O buffers power supply 3 V I/O V LVDS I/O V (1) The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.

3 Maximum Allowed Overshoot and Undershoot Voltage 3 Symbol Description Condition Minimum Maximum Unit V CCIOREF_HPS HPS I/O pre-driver power supply V V CCPLL_HPS HPS PLL power supply V I OUT DC output current per pin ma T J Operating junction temperature C T STG Storage temperature (no bias) C Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to 2.0 V for input currents less than 100 ma and periods shorter than 20 ns. The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 2.70 V for LVDS I/O can only be at 2.70 V for ~4% over the lifetime of the device. Table 2: Maximum Allowed Overshoot During Transitions for Arria 10 Devices Preliminary This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. The LVDS I/O values are applicable to the VREFP_ADC and VREFN_ADC I/O pins. Symbol Description LVDS I/O (2) Condition (V) 3 V I/O Overshoot Duration as % at T J = 100 C % % Unit Vi (AC) AC input voltage % % % > 2.70 > 4.00 No overshoot allowed % (2) The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.

4 4 Recommended Operating Conditions Recommended Operating Conditions This section lists the functional operation limits for the AC and DC parameters for Arria 10 devices. Recommended Operating Conditions Table 3: Recommended Operating Conditions for Arria 10 Devices Preliminary This table lists the steady-state voltage values expected from Arria 10 devices. Power supply ramps must all be strictly monotonic, without plateaus. V CC V CCP Symbol Description Condition Minimum (3) Typical Maximum (3) Unit V CCPGM Core voltage power supply Periphery circuitry and transceiver fabric interface power supply Configuration pins power supply Standard and low power (4) 0.93 V V CC PowerManager (5) 0.8, , , 0.93 V SmartVID (6) V Standard and low power (4) 0.93 V V CC PowerManager (5) 0.8, , , 0.93 V SmartVID (6) V 1.8 V V 1.5 V V 1.2 V V V CCERAM Embedded memory power supply 0.9 V (4) 0.93 V (3) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (4) You can operate 1 and 2 speed grade devices at 0.9 V or 0.95 V typical value. You can operate -3 speed grade device at only 0.9 V typical value. Core performance shown in this datasheet is applicable for the operation at 0.9 V. Operating at 0.95 V results in higher core performance and higher power consumption. For more information about the performance and power consumption of 0.95 V operation, refer to the Quartus Prime software timing reports, PowerPlay Power Analyzer report, and Early Power Estimator (EPE). (5) You can operate V CC PowerManager devices at either 0.83 V or 0.9 V. Power V CC and V CCP at 0.9 V to achieve 1 speed grade performance. Power V CC and V CCP at 0.83 V to achieve lower performance using the lowest power. (6) SmartVID is supported in devices with 2V and 3V speed grades only.

5 Recommended Operating Conditions 5 Symbol Description Condition Minimum (3) Typical Maximum (3) Unit V CCBAT (7) V CCPT V CCIO V CCA_PLL V REFP_ADC V I (9) Battery back-up power supply (For design security volatile key register) Power supply for programmable power technology and I/O pre-driver I/O buffers power supply PLL analog voltage regulator power supply Precision voltage reference for voltage sensor DC input voltage 1.8 V V 1.2 V V 1.8 V V 3.0 V (for 3 V I/O only) V 2.5 V (for 3 V I/O only) V 1.8 V V 1.5 V V 1.35 V (8) 1.35 (8) V 1.25 V V 1.2 V (8) 1.2 (8) V V V 3 V I/O V LVDS I/O V V O Output voltage 0 V CCIO V T J Operating junction temperature Extended C Industrial C (3) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (7) If you do not use the design security feature in Arria 10 devices, connect V CCBAT to a 1.5-V or 1.8-V power supply. Arria 10 power-on reset (POR) circuitry monitors V CCBAT. Arria 10 devices do not exit POR if V CCBAT is not powered up. (8) For minimum and maximum voltage values, refer to the I/O Standard Specifications section. (9) The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.

6 6 Transceiver Power Supply Operating Conditions Symbol Description Condition Minimum (3) Typical Maximum (3) Unit t RAMP (10)(11) Power supply ramp time Related Information I/O Standard Specifications on page 17 Transceiver Power Supply Operating Conditions Table 4: Transceiver Power Supply Operating Conditions for Arria 10 GX/SX Devices Preliminary Standard POR 200 µs 100 ms Fast POR 200 µs 4 ms Symbol Description Condition (12) Minimum (13) Typical Maximum Unit V CCT_GXB[L,R] Transmitter power supply Chip-to-Chip 17.4 Gbps Or Backplane (14) 16.0 Gbps Chip-to-Chip 11.3 Gbps Or Backplane (14) Gbps V V (3) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (10) This is also applicable to HPS power supply. For HPS power supply, refer to t RAMP specifications for standard POR when HPS_PORSEL = 0 and t RAMP specifications for fast POR when HPS_PORSEL = 1. (11) t ramp is the ramp time of each individual power supply, not the ramp time of all combined power supplies. (12) These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GX/SX Devices for exact data rate ranges. (13) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (14) Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.

7 Transceiver Power Supply Operating Conditions 7 Symbol Description Condition (12) Minimum (13) Typical Maximum Unit V CCR_GXB[L,R] Receiver power supply Chip-to-Chip 17.4 Gbps Or Backplane (14) 16.0 Gbps Chip-to-Chip 11.3 Gbps Or Backplane (14) Gbps V V V CCH_GXB[L,R] Transceiver high voltage power V Note: Most VCCR_GXB and VCCT_GXB pins associated with unused transceiver channels can be grounded on a per-side basis to minimize power consumption. Refer to the Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines and the Quartus Prime pin report for information about pinning out the package to minimize power consumption for your specific design. (12) These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GX/SX Devices for exact data rate ranges. (13) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

8 8 Transceiver Power Supply Operating Conditions Table 5: Transceiver Power Supply Operating Conditions for Arria 10 GT Devices Preliminary Symbol Description Condition (15) Minimum (13) Typical Maximum Unit Chip-to-Chip < 28.3 Gbps (16) V Or Backplane (14) < 17.4 Gbps V CCT_GXB[L,R] V CCR_GXB[L,R] Transmitter power supply Receiver power supply Chip-to-Chip < 15 Gbps Or Backplane (14) < 14.2 Gbps Chip-to-Chip < 11.3 Gbps Or Backplane (14) < Gbps Chip-to-Chip < 28.3 Gbps Or Backplane (14) < 17.4 Gbps Chip-to-Chip < 15 Gbps Or Backplane (14) < 14.2 Gbps Chip-to-Chip < 11.3 Gbps Or Backplane (14) < Gbps V V V V V (15) These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GT Devices table for exact data rate ranges.

9 HPS Power Supply Operating Conditions 9 Symbol Description Condition (15) Minimum (13) Typical Maximum Unit V CCH_GXB[L,R] Related Information Transceiver high voltage power supply Transceiver Performance for Arria 10 GT Devices on page 26 Provides the data rate ranges for different transceiver speed grades. Transceiver Performance for Arria 10 GX/SX Devices on page 23 Provides the data rate ranges for different transceiver speed grades. Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines HPS Power Supply Operating Conditions Table 6: HPS Power Supply Operating Conditions for Arria 10 SX Devices Preliminary V This table lists the steady-state voltage and current values expected from Arria 10 system-on-a-chip (SoC) devices with ARM -based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for Arria 10 Devices table for the steady-state voltage values expected from the FPGA portion of the Arria 10 SoC devices. Symbol Description Condition Minimum (17) Typical Maximum (17) Unit V CCL_HPS V CCIO_HPS HPS core voltage and periphery circuitry power supply HPS I/O buffers power supply HPS processor speed = 1.2 GHz HPS processor speed = 1.5 GHz, 1 speed grade V V 3.0 V V 2.5 V V 1.8 V V (15) These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GT Devices table for exact data rate ranges. (16) 28.3 Gbps is the maximum data rate for GT channels Gbps is the maximum data rate for GX channels. (17) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

10 10 DC Characteristics Symbol Description Condition Minimum (17) Typical Maximum (17) Unit V CCIOREF_HPS HPS I/O pre-driver power supply V V CCPLL_HPS HPS PLL analog voltage regulator power supply Related Information Recommended Operating Conditions on page 4 Provides the steady-state voltage values for the FPGA portion of the device. DC Characteristics V The OCT variation after power-up calibration specifications will be available in a future release of the. Supply Current and Power Consumption Altera offers two ways to estimate power for your design the Excel-based Early Power Estimator (EPE) and the Quartus Prime PowerPlay Power Analyzer feature. Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources. The Quartus Prime PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-androute. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates. Related Information PowerPlay Early Power Estimator User Guide Provides more information about power estimation tools. PowerPlay Power Analysis chapter, Quartus Prime Handbook Provides more information about power estimation tools. (17) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

11 I/O Pin Leakage Current 11 I/O Pin Leakage Current Table 7: I/O Pin Leakage Current for Arria 10 Devices Preliminary If V O = V CCIO to V CCIOMAX, 300 μa of leakage current per I/O is expected. Symbol Description Condition Min Max Unit I I Input pin V I = 0 V to V CCIOMAX µa I OZ Tri-stated I/O pin V O = 0 V to V CCIOMAX µa Bus Hold Specifications The bus-hold trip points are based on calculated input voltages from the JEDEC standard. Table 8: Bus Hold Parameters for Arria 10 Devices Preliminary V CCIO (V) Parameter Symbol Condition Min Max Min Max Min Max Min Max Min Max Unit Bus-hold, low, sustaining current I SUSL V IN > V IL (max) 8 (18), 12 (18), 30 (18), µa 26 (19) 32 (19) 55 (19) Bus-hold, high, sustaining current I SUSH V IN < V IH (min) 8 (18), 12 (18), 30 (18), µa 26 (19) 32 (19) 55 (19) Bus-hold, low, overdrive current I ODL 0 V < V IN µa < V CCIO (18) This value is only applicable for LVDS I/O bank. (19) This value is only applicable for 3 V I/O bank.

12 12 OCT Calibration Accuracy Specifications Parameter Symbol Condition V CCIO (V) Min Max Min Max Min Max Min Max Min Max Unit Bus-hold, high, overdrive current I ODH 0 V < V IN µa < V CCIO Bus-hold trip point V TRIP V OCT Calibration Accuracy Specifications If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block. Table 9: OCT Calibration Accuracy Specifications for Arria 10 Devices Preliminary Calibration accuracy for the calibrated on-chip series termination (R S OCT) and on-chip parallel termination (R T OCT) are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change. Symbol Description Condition (V) Calibration Accuracy E1, I1 E2, I2 E3, I3 Unit 48-Ω, 60-Ω, 80-Ω, and 240-Ω R S Internal series termination with calibration (48-Ω, 60-Ω, 80-Ω, and 240-Ω setting) 34-Ω and 40-Ω R S Internal series termination with calibration (34-Ω and 40-Ω setting) 25-Ω R S Internal series termination with calibration 50-Ω R S Internal series termination with calibration V CCIO = 1.2 ±15 ±15 ±15 % V CCIO = 1.5, 1.35, 1.25, 1.2 ±15 ±15 ±15 % V CCIO = 1.8, 1.5, 1.2 ±15 ±15 ±15 % V CCIO = 1.8, 1.5, 1.2 ±15 ±15 ±15 %

13 OCT Without Calibration Resistance Tolerance Specifications 13 Symbol Description Condition (V) 34-Ω, 40-Ω, 48-Ω, and 60-Ω R S 34-Ω, 40-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and 240-Ω R T Internal series termination with calibration (34-Ω, 40-Ω, 48-Ω, and 60-Ωsetting) Internal parallel termination with calibration (34-Ω, 40-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and 240-Ω setting) 60-Ω and 120-Ω R T Internal parallel termination with calibration (60-Ω and 120-Ω setting) 30-Ω and 40-Ω R T Internal parallel termination with calibration (30-Ω and 40-Ω setting) 50-Ω R T Internal parallel termination with calibration (50-Ω setting) OCT Without Calibration Resistance Tolerance Specifications POD12 I/O standard, V CCIO = 1.2 POD12 I/O standard, V CCIO = 1.2 V CCIO = 1.5, 1.35, 1.25, 1.2 Calibration Accuracy E1, I1 E2, I2 E3, I3 Unit ±15 ±15 ±15 % ±15 ±15 ±15 % 10 to to to +40 % V CCIO = 1.5, 1.35, to to to +40 % V CCIO = 1.8, 1.5, to to to +40 % Table 10: OCT Without Calibration Resistance Tolerance Specifications for Arria 10 Devices Preliminary This table lists the Arria 10 OCT without calibration resistance tolerance to PVT changes. Symbol Description Condition (V) Internal series termination without 25-Ω R S calibration (25-Ω setting) Internal series termination without 34-Ω R S calibration (34-Ω setting) Resistance Tolerance E1, I1 E2, I2 E3, I3 V CCIO = 2.5, to +30 ± 40 ± 40 % V CCIO = 1.8, to +30 ± 50 ± 50 % V CCIO = to +30 ± 50 ± 50 % V CCIO = 1.5, 1.35, to +30 ± 50 ± 50 % V CCIO = to +30 ± 50 ± 50 % POD12 I/O standard 50 to +30 ± 50 ± 50 % Unit

14 14 OCT Without Calibration Resistance Tolerance Specifications Symbol Description Condition (V) Internal series termination without 40-Ω R S calibration (40-Ω setting) 48-Ω R S Internal series termination without calibration(48-ω setting) Internal series termination without 50-Ω R S calibration (50-Ω setting) 60-Ω R S Internal series termination without calibration (60-Ω setting) 100-Ω R D Internal differential termination (100-Ω setting) 120-Ω R S Internal series termination without calibration (120-Ω setting) Figure 1: Equation for OCT Variation Without Recalibration Preliminary Resistance Tolerance E1, I1 E2, I2 E3, I3 V CCIO = 1.5, 1.35, to +30 ± 50 ± 50 % V CCIO = to +30 ± 50 ± 50 % POD12 I/O standard 50 to +30 ± 50 ± 50 % V CCIO = to +30 ± 50 ± 50 % POD12 I/O standard 50 to +30 ± 50 ± 50 % VCCIO = 2.5, to +30 ± 40 ± 40 % V CCIO = 1.8, to +30 ± 50 ± 50 % V CCIO = to +30 ± 50 ± 50 % V CCIO = to +30 ± 50 ± 50 % V CCIO = 1.8, 1.5 ± 25 ± 35 ± 40 % V CCIO = to +30 ± 50 ± 50 % Unit

15 Pin Capacitance 15 The definitions for the equation are as follows: The R OCT value calculated shows the range of OCT resistance with the variation of temperature and V CCIO. R SCAL is the OCT resistance value at power-up. ΔT is the variation of temperature with respect to the temperature at power up. ΔV is the variation of voltage with respect to the V CCIO at power up. dr/dt is the percentage change of R SCAL with temperature. dr/dv is the percentage change of R SCAL with voltage. Pin Capacitance Table 11: Pin Capacitance for Arria 10 Devices Preliminary Symbol Description Value Unit C IO_COLUMN Input capacitance on column I/O pins 2.5 pf C OUTFB Input capacitance on dual-purpose clock output/feedback pins 2.5 pf Internal Weak Pull-Up and Weak Pull-Down Resistor All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. The weak pull-down feature is only available for the pins as described in the Internal Weak Pull-Down Resistor Values for Arria 10 Devices table.

16 16 Internal Weak Pull-Up and Weak Pull-Down Resistor Table 12: Internal Weak Pull-Up Resistor Values for Arria 10 Devices Preliminary Symbol Description Condition (V) (20) Value (21) Unit R PU Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. Table 13: Internal Weak Pull-Down Resistor Values for Arria 10 Devices Preliminary V CCIO = 3.0 ±5% 25 kω V CCIO = 2.5 ±5% 25 kω V CCIO = 1.8 ±5% 25 kω V CCIO = 1.5 ±5% 25 kω V CCIO = 1.35 ±5% 25 kω V CCIO = 1.25 ±5% 25 kω V CCIO = 1.2 ±5% 25 kω Pin Name Description Condition (V) Value (21) Unit nio_pullup TCK MSEL[0:2] Dedicated input pin that determines the internal pull-ups on user I/O pins and dualpurpose I/O pins. Dedicated JTAG test clock input pin. Configuration input pins that set the configuration scheme for the FPGA device. V CC = 0.9 ±3.33% 25 kω V CCPGM = 1.8 ±5 % 25 kω V CCPGM = 1.5 ±5% 25 kω V CCPGM = 1.2 ±5% 25 kω V CCPGM = 1.8 ±5% 25 kω V CCPGM = 1.5 ±5% 25 kω V CCPGM = 1.2 ±5% 25 kω Related Information Arria 10 Device Family Pin Connection Guidelines Provides more information about the pins that support internal weak pull-up and internal weak pull-down features. (20) Pin pull-up resistance values may be lower if an external source drives the pin higher than V CCIO. (21) Valid with ±25% tolerances to cover changes over PVT.

17 I/O Standard Specifications 17 I/O Standard Specifications Tables in this section list the input voltage (V IH and V IL ), output voltage (V OH and V OL ), and current drive characteristics (I OH and I OL ) for various I/O standards supported by Arria 10 devices. For minimum voltage values, use the minimum V CCIO values. For maximum voltage values, use the maximum V CCIO values. You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards. Related Information Recommended Operating Conditions on page 4 Single-Ended I/O Standards Specifications Table 14: Single-Ended I/O Standards Specifications for Arria 10 Devices Preliminary I/O Standard 3.0-V LVTTL 3.0-V LVCMOS V CCIO (V) V IL (V) V IH (V) V OL (V) V OH (V) I OL (22) Min Typ Max Min Max Min Max Max Min (ma) I OH (22) (ma) V CCIO V V V CCIO 0.65 V CCIO V CCIO V CCIO V V CCIO 0.65 V CCIO V CCIO V CCIO 0.75 V CCIO V V CCIO 0.65 V CCIO V CCIO V CCIO 0.75 V CCIO 2 2 (22) To meet the I OL and I OH specifications, you must set the current strength settings accordingly. For example, to meet the 3.0-V LVTTL specification (2 ma), you should set the current strength settings to 2 ma. Setting at lower current strength may not meet the I OL and I OH specifications in the datasheet.

18 18 Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Table 15: Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Arria 10 Devices Preliminary I/O Standard SSTL-18 Class I, II SSTL-15 Class I, II V CCIO (V) V REF (V) V TT (V) Min Typ Max Min Typ Max Min Typ Max V REF 0.04 V REF V REF V CCIO 0.5 V CCIO 0.51 V CCIO 0.49 V CCIO 0.5 V CCIO 0.51 V CCIO SSTL V CCIO 0.5 V CCIO 0.51 V CCIO 0.49 V CCIO 0.5 V CCIO 0.51 V CCIO SSTL V CCIO 0.5 V CCIO 0.51 V CCIO 0.49 V CCIO 0.5 V CCIO 0.51 V CCIO SSTL V CCIO 0.5 V CCIO 0.51 V CCIO 0.49 V CCIO 0.5 V CCIO 0.51 V CCIO HSTL-18 Class I, II HSTL-15 Class I, II HSTL-12 Class I, II V CCIO / V CCIO / V CCIO 0.5 V CCIO 0.53 V CCIO V CCIO /2 HSUL V CCIO 0.5 V CCIO 0.51 V CCIO POD V CCIO 0.7 V CCIO 0.71 V CCIO V CCIO

19 Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications 19 Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Table 16: Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Arria 10 Devices Preliminary I/O Standard SSTL-18 Class I SSTL-18 Class II SSTL-15 Class I SSTL-15 Class II V IL(DC) (V) V IH(DC) (V) V IL(AC) (V) V IH(AC) (V) V OL (V) V OH (V) I OL (23) Min Max Min Max Max Min Max Min 0.3 V REF V REF V CCIO V REF 0.25 V REF V TT V TT V REF V REF V CCIO V REF 0.25 V REF V CCIO V REF 0.1 V REF V REF V REF V CCIO 0.8 V CCIO 8 8 V REF 0.1 V REF V REF V REF V CCIO 0.8 V CCIO SSTL-135 V REF 0.09 V REF V REF 0.16 V REF V CCIO 0.8 V CCIO SSTL-125 V REF 0.09 V REF V REF 0.15 V REF V CCIO 0.8 V CCIO SSTL-12 V REF 0.10 V REF V REF 0.15 V REF V CCIO 0.8 V CCIO HSTL-18 Class I HSTL-18 Class II HSTL-15 Class I HSTL-15 Class II HSTL-12 Class I V REF 0.1 V REF V REF 0.2 V REF V CCIO V REF 0.1 V REF V REF 0.2 V REF V CCIO V REF 0.1 V REF V REF 0.2 V REF V CCIO V REF 0.1 V REF V REF 0.2 V REF V CCIO V REF 0.08 V REF V CCIO V REF 0.15 V REF V CCIO 0.75 V CCIO 8 8 (ma) I OH (23) (ma) (23) To meet the I OL and I OH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 ma), you should set the current strength settings to 8 ma. Setting at lower current strength may not meet the I OL and I OH specifications in the datasheet.

20 20 Differential SSTL I/O Standards Specifications I/O Standard HSTL-12 Class II V IL(DC) (V) V IH(DC) (V) V IL(AC) (V) V IH(AC) (V) V OL (V) V OH (V) I OL (23) Min Max Min Max Max Min Max Min 0.15 V REF 0.08 V REF V CCIO V REF 0.15 V REF V CCIO 0.75 V CCIO HSUL-12 V REF 0.13 V REF V REF 0.22 V REF V CCIO 0.9 V CCIO POD V REF 0.08 V REF V CCIO V REF 0.15 V REF ( ) V CCIO ( ) V CCIO Differential SSTL I/O Standards Specifications Table 17: Differential SSTL I/O Standards Specifications for Arria 10 Devices Preliminary I/O Standard SSTL-18 Class I, II SSTL-15 Class I, II V CCIO (V) V SWING(DC) (V) V SWING(AC) (V) V IX(AC) (V) Min Typ Max Min Max Min Max Min Typ Max V CCIO V CCIO V CCIO / (24) 2(V IH(AC) V REF ) SSTL (24) 2(V IH(AC) V REF ) SSTL (24) 2(V IH(AC) V REF ) SSTL (24) 2(V IH(AC) V REF ) 2(V REF V IL(AC) ) 2(V IL(AC) V REF ) 2(V IL(AC) V REF ) 2(V IL(AC) V REF ) V CCIO / V CCIO / V CCIO / (ma) I OH (23) (ma) V CCIO / V CCIO / V CCIO /2 V CCIO / V CCIO /2 V CCIO / V REF 0.15 V CCIO /2 V REF POD V REF 0.08 V REF (23) To meet the I OL and I OH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 ma), you should set the current strength settings to 8 ma. Setting at lower current strength may not meet the I OL and I OH specifications in the datasheet. (24) The maximum value for V SWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (V IH(DC) and V IL(DC) ).

21 Differential HSTL and HSUL I/O Standards Specifications 21 Differential HSTL and HSUL I/O Standards Specifications Table 18: Differential HSTL and HSUL I/O Standards Specifications for Arria 10 Devices Preliminary I/O Standard HSTL-18 Class I, II HSTL-15 Class I, II HSTL-12 Class I, II V CCIO (V) V DIF(DC) (V) V DIF(AC) (V) V IX(AC) (V) V CM(DC) (V) Min Typ Max Min Max Min Max Min Typ Max Min Typ Max V CCIO HSUL (V IH(DC) V REF ) Differential I/O Standards Specifications 2(V REF V IH(DC) ) 0.3 V CCIO (V IH(AC) V REF ) 2(V REF V IH(AC) ) Table 19: Differential I/O Standards Specifications for Arria 10 Devices Preliminary Differential inputs are powered by V CCPT which requires 1.8 V. I/O Standard PCML 0.5 V CCIO 0.4 V CCIO 0.5 V CCIO 0.6 V CCIO 0.5 V CCIO V CCIO V CCIO V CCIO V CCIO V CCIO V CCIO (V) V ID (mv) (25) V ICM(DC) (V) V OD (V) (26) V OCM (V) (26) Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max Transmitter, receiver, and input reference clock pins of high-speed transceivers use the CML I/O standard. For transmitter, receiver, and reference clock I/O pin specifications, refer to Transceiver Specifications for Arria 10 GX, SX, and GT Devices table. (25) The minimum V ID value is applicable over the entire common mode range, V CM. (26) R L range: 90 R L 110 Ω.

22 22 Switching Characteristics I/O Standard V CCIO (V) V ID (mv) (25) V ICM(DC) (V) V OD (V) (26) V OCM (V) (26) Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max LVDS (27) RSDS (HIO) (28) V CM = 1.25 V V CM = 1.25 V 0 D MAX 700 Mbps 1 D MAX > 700 Mbps Mini-LVDS (HIO) (29) LVPECL (30) D MAX 700 Mbps 1 D MAX > 700 Mbps Related Information Transceiver Specifications for Arria 10 GX, SX, and GT Devices on page 29 Provides the specifications for transmitter, receiver, and reference clock I/O pin Switching Characteristics This section provides the performance characteristics of Arria 10 core and periphery blocks for extended grade devices. (25) The minimum V ID value is applicable over the entire common mode range, V CM. (26) R L range: 90 R L 110 Ω. (27) For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 700 Mbps and 0 V to 1.85 V for data rates below 700 Mbps. (28) For optimized RSDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.4 V. (29) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.4 V to V. (30) For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and 0.45 V to 1.95 V for data rates below 700 Mbps.

23 Transceiver Performance Specifications 23 Transceiver Performance Specifications Transceiver Performance for Arria 10 GX/SX Devices Table 20: Transmitter and Receiver Data Rate Performance Preliminary Symbol/Description Condition Transceiver Speed Grade 1 Transceiver Speed Grade 2 Transceiver Speed Grade 3 Transceiver Speed Grade 4 Transceiver Speed Grade 5 (31) Unit Chip-to-Chip (32) Maximum data rate V CCR_GXB = V CCT_GXB = 1.03 V Maximum data rate V CCR_GXB = V CCT_GXB = 0.95 V Gbps Gbps Minimum Data Rate 1.0 (33) Gbps Maximum data rate V CCR_GXB = V CCT_GXB = 1.03 V Gbps Backplane (32) Maximum data rate V CCR_GXB = V CCT_GXB = 0.95 V Gbps Minimum Data Rate 1.0 (33) Gbps (31) Transceiver speed grade 5 supports PCI Express (PCIe ) Gen3. (32) Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE. (33) Arria 10 transceivers can support data rates down to 125 Mbps with over sampling.

24 24 Transceiver Performance for Arria 10 GX/SX Devices Table 21: ATX PLL Performance Preliminary Symbol/Description Supported Output Frequency Condition Maximum Frequency Minimum Frequency Transceiver Speed Grade 1 Transceiver Speed Grade 2 Transceiver Speed Grade 3 Transceiver Speed Grade 4 Transceiver Speed Grade GHz Unit 500 MHz Table 22: Fractional PLL Performance Preliminary Symbol/ Description Supported Output Frequency Condition Maximum Frequency Minimum Frequency Transceiver Speed Grade 1 Transceiver Speed Grade 2 Transceiver Speed Grade 3 Transceiver Speed Grade 4 Transceiver Speed Grade GHz Unit 500 MHz Table 23: CMU PLL Performance Preliminary Symbol/ Description Supported Output Frequency Condition Maximum Frequency Minimum Frequency Transceiver Speed Grade 1 Transceiver Speed Grade 2 Transceiver Speed Grade 3 Transceiver Speed Grade 4 Transceiver Speed Grade GHz Unit 500 MHz Related Information Transceiver Power Supply Operating Conditions on page 6

25 High-Speed Serial Transceiver-Fabric Interface Performance for Arria High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10 GX/SX Devices Table 24: High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10 GX/SX Devices Preliminary Symbol/Description Condition (V) -E1M / -I1M Core Speed Grade with Power Options -E1L / -E1S / -I1L -E2L / -I2L -E3S / -I3S / M3 20-bit interface - FIFO V CC = MHz 20-bit interface - Registered V CC = MHz 32-bit interface - FIFO V CC = MHz 32-bit interface - Registered V CC = MHz 64-bit interface - FIFO V CC = MHz 64-bit interface - Registered V CC = MHz PCIe Gen3 HIP-Fabric interface V CC = MHz 20-bit interface - FIFO V CC = MHz 20-bit interface - Registered V CC = MHz 32-bit interface - FIFO V CC = MHz 32-bit interface - Registered V CC = MHz 64-bit interface - FIFO V CC = MHz 64-bit interface - Registered V CC = MHz PCIe Gen3 HIP-Fabric interface V CC = MHz Unit

26 26 Transceiver Performance for Arria 10 GT Devices Transceiver Performance for Arria 10 GT Devices Table 25: Transmitter and Receiver Data Rate Performance Preliminary Symbol/Description Condition Transceiver Speed Grade 2 Maximum data rate V CCR_GXB = V CCT_GXB = 1.12 V Transceiver Speed Grade 3 Transceiver Speed Grade 4 Unit GT Channel (35) 28.3/28.1 (36) Gbps GX Channel Gbps Chip-to-chip (34) Maximum data rate V CCR_GXB = V CCT_GXB = 1.03 V Maximum data rate V CCR_GXB = V CCT_GXB = 0.95 V GX Channel Gbps GX Channel Gbps Minimum data rate GT Channel GX Channel 1.0 (37) Gbps (34) Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE. (35) GT channels are only available when V CCT_GXB = 1.12 V and V CCR_GXB = 1.12 V. (36) To achieve 28.3 Gbps, you must use a -1 core speed grade and a -2 transceiver speed grade device configuration. To achieve 28.1 Gbps, you must use a -2 core speed grade and a -2 transceiver speed grade device configuration. (37) Arria 10 transceivers can support data rates down to 125 Mbps with over sampling.

27 Transceiver Performance for Arria 10 GT Devices 27 Symbol/Description Condition Transceiver Speed Grade 2 Maximum data rate V CCR_GXB = V CCT_GXB = 1.12 V Transceiver Speed Grade 3 Transceiver Speed Grade 4 Unit GX Channel Gbps Backplane (34) Maximum data rate V CCR_GXB = V CCT_GXB = 1.03 V Maximum data rate V CCR_GXB = V CCT_GXB = 0.95 V GX Channel Gbps GX Channel Gbps Table 26: ATX PLL Performance Preliminary Minimum data rate GX Channel 1.0 (37) Gbps Symbol/Description Condition Transceiver Speed Grade 2 Supported Output Frequency Transceiver Speed Grade 3 Transceiver Speed Grade 4 Maximum frequency GHz Minimum frequency 500 MHz Table 27: Fractional PLL Performance Preliminary Symbol/Description Condition Transceiver Speed Grade 2 Supported Output Frequency Transceiver Speed Grade 3 Transceiver Speed Grade 4 Maximum frequency 6.25 GHz Minimum frequency 500 MHz Unit Unit

28 28 High-Speed Serial Transceiver-Fabric Interface Performance for Arria Table 28: CMU PLL Performance Preliminary Symbol/Description Condition Transceiver Speed Grade 2 Supported Output Frequency Transceiver Speed Grade 3 Transceiver Speed Grade 4 Maximum frequency GHz Minimum frequency 500 MHz Related Information Transceiver Power Supply Operating Conditions on page 6 High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10 GT Devices Table 29: High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10 GT Devices Preliminary Symbol/Description Condition (V) Core Speed Grade with Power Options bit interface - FIFO V CC = MHz 20-bit interface - Registered V CC = MHz 32-bit interface - FIFO V CC = MHz 32-bit interface - Registered V CC = MHz 64-bit interface - FIFO V CC = MHz 64-bit interface - Registered V CC = MHz PCIe Gen3 HIP-Fabric interface V CC = MHz Unit Unit

29 Transceiver Specifications for Arria 10 GX, SX, and GT Devices 29 Transceiver Specifications for Arria 10 GX, SX, and GT Devices Table 30: Reference Clock Specifications Preliminary Symbol/Description Supported I/O Standards Input Reference Clock Frequency (CMU PLL) Input Reference Clock Frequency (ATX PLL) Input Reference Clock Frequency (fpll PLL) Condition Dedicated reference clock pin RX reference clock pin Transceiver Speed Grades 1, 2, 3, 4, and 5 Min Typ Max CML, Differential LVPECL, LVDS, and HCSL CML, Differential LVPECL, and LVDS Unit MHz MHz MHz Rise time 20% to 80% 400 ps Fall time 80% to 20% 400 ps Duty cycle % Spread-spectrum modulating clock frequency PCIe khz Spread-spectrum downspread PCIe 0 to 0.5 % On-chip termination resistors 100 Ω Absolute V MAX Dedicated reference clock pin 1.6 V RX reference clock pin 1.2 V Absolute V MIN 0.4 V Peak-to-peak differential input voltage mv

30 30 Transceiver Specifications for Arria 10 GX, SX, and GT Devices Symbol/Description V ICM (AC coupled) V ICM (DC coupled) Transmitter REFCLK Phase Noise (622 MHz) (38) Transmitter REFCLK Phase Jitter (100 MHz) Condition Transceiver Speed Grades 1, 2, 3, 4, and 5 Min Typ Max V CCR_GXB = 0.95 V 0.95 V V CCR_GXB = 1.03 V 1.03 V V CCR_GXB = 1.12 V 1.12 V HCSL I/O standard for PCIe reference clock Unit mv 100 Hz 70 dbc/hz 1 khz 90 dbc/hz 10 khz 100 dbc/hz 100 khz 110 dbc/hz 1 MHz 120 dbc/hz 1.5 to 100 MHz (PCIe) 4.2 ps (rms) R REF 2.0 k ±1% Ω T SSC-MAX-PERIOD-SLEW Max SSC df/dt 0.75 Table 31: Transceiver Clocks Specifications Preliminary Symbol/Description CLKUSR pin for transceiver calibration Condition Transceiver Calibration Transceiver Speed Grades 1, 2, 3, 4, and 5 Unit Min Typ Max MHz (38) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 622 MHz + 20*log(f/622).

31 Transceiver Specifications for Arria 10 GX, SX, and GT Devices 31 Symbol/Description reconfig_clk Condition Reconfiguration interface Transceiver Speed Grades 1, 2, 3, 4, and 5 Unit Min Typ Max MHz Table 32: Transceiver Clock Network Maximum Data Rate Specifications Clock Network Maximum Performance ATX (39) fpll CMU Channel Span x channels Gbps x N/A 6 channels Gbps x6 PLL feedback N/A Side-wide Gbps xn at 0.95 V N/A Up two banks and down two banks xn at 1.03 V N/A Up two banks and down two banks xn at 1.12 V N/A Up two banks and down two banks Table 33: Receiver Specifications Preliminary Symbol/Description Supported I/O Standards Condition Transceiver Speed Grades 1, 2, 3, 4, and 5 Min Typ Max High Speed Differential I/O, CML, Differential LVPECL, and LVDS Absolute V MAX for a receiver pin (40) 1.2 V Unit Gbps Gbps Gbps Unit (39) ATX maximum data rate support per speed grade.

32 32 Transceiver Specifications for Arria 10 GX, SX, and GT Devices Symbol/Description Condition Transceiver Speed Grades 1, 2, 3, 4, and 5 Min Typ Max Absolute V MIN for a receiver pin (40) -0.4 V Maximum peakto-peak differential input voltage V ID (diff p-p) before device configuration (41) Maximum peakto-peak differential input voltage V ID (diff p-p) after device configuration (41) Minimum differential eye opening at receiver serial input pins (42) Differential onchip termination resistors 1.6 V V CCR_GXB = 1.12 V 2.0 V V CCR_GXB = 1.03 V 2.0 V V CCR_GXB = 0.95 V 2.4 V 50 mv 85-Ω setting 85 ± 30% Ω 100-Ω setting 100 ± 30% Ω Unit (40) The device cannot tolerate prolonged operation at this absolute maximum. (41) DC coupling specifications are pending silicon characterization. (42) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.

33 Transceiver Specifications for Arria 10 GX, SX, and GT Devices 33 Symbol/Description V ICM (AC and DC coupled) Condition Transceiver Speed Grades 1, 2, 3, 4, and 5 Min Typ Max V CCR_GXB = 0.95 V 600 mv V CCR_GXB = 1.03 V 700 mv V CCR_GXB = 1.12 V 700 mv t LTR (43) 10 µs t LTD (44) 4 µs t LTD_manual (45) 4 µs t LTR_LTD_manual (46) 15 µs Run Length 200 UI CDR PPM tolerance Programmable DC Gain PCIe-only PPM All other protocols PPM DC Gain Setting = 0-10 db DC Gain Setting = db DC Gain Setting = 2-3 db DC Gain Setting = db DC Gain Setting = 4 4 db Unit (43) t LTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset. (44) t LTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high. (45) t LTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode. (46) t LTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode.

34 34 Transceiver Specifications for Arria 10 GX, SX, and GT Devices Table 34: Transmitter Specifications Preliminary Symbol/Description Supported I/O Standards Differential onchip termination resistors V OCM (AC coupled) V OCM (DC coupled) Condition Transceiver Speed Grades 1, 2, 3, 4, and 5 Min Typ Max High Speed Differential I/O (47) 85-Ω setting 85 ± 20% Ω 100-Ω setting 100 ± 20% Ω 120-Ω setting 120 ± 20% Ω 150-Ω setting 150 ± 20% Ω V CCT = 0.95 V 450 mv V CCT = 1.03 V 500 mv V CCT = 1.12 V 550 mv V CCT = 0.95 V 450 mv V CCT = 1.03 V 500 mv V CCT = 1.12 V 550 mv Rise time (48) 20% to 80% ps Fall time (48) 80% to 20% ps Intra-differential pair skew (49) TX V CM = 0.5 V and slew rate of 15 ps 15 ps Unit (47) High Speed Differential I/O is the dedicated I/O standard for the transmitter in Arria 10 transceivers. (48) The Quartus Prime software automatically selects the appropriate slew rate depending on the configured data rate or functional mode. (49) In QPI mode, if V CM < 0.17 V, the input Vid must be greater than 100 mv. If V CM > 0.17 V, the input Vid must be greater than 70 mv.

35 Transceiver Specifications for Arria 10 GX, SX, and GT Devices 35 Table 35: Typical Transmitter V OD Settings Preliminary Symbol V OD Setting V OD /V CCT Ratio V OD differential value = V OD /V CCT ratio x V CCT

36 36 Core Performance Specifications Core Performance Specifications Clock Tree Specifications Table 36: Clock Tree Performance for Arria 10 Devices Preliminary Parameter Global clock, regional clock, and small periphery clock E1L, E1M (50), E1S, I1L, I1M (50), I1S Performance E2L, E2S, I2L, I2S E1M (51), I1M (51), E3S, I3S MHz Large periphery clock MHz PLL Specifications Fractional PLL Specifications Table 37: Fractional PLL Specifications for Arria 10 Devices Preliminary Symbol Parameter Condition Min Typ Max Unit f IN Input clock frequency MHz f INPFD f VCO Input clock frequency to the phase frequency detector (PFD) PLL voltage-controlled oscillator (VCO) operating range Unit MHz GHz t EINDUTY Input clock duty cycle % (50) When you power V CC and V CCP at nominal voltage of 0.90 V. (51) When you power V CC and V CCP at lower voltage of 0.83 V. (52) This specification is limited in the Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.

37 Fractional PLL Specifications 37 Symbol Parameter Condition Min Typ Max Unit f OUT f DYCONFIGCLK t LOCK t DLOCK Output frequency for internal global or regional clock Dynamic configuration clock for reconfig_clk Time required to lock from end-ofdevice configuration or deassertion of pll_powerdown Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) 644 MHz 100 MHz 1 ms 1 ms f CLBW PLL closed-loop bandwidth TBD MHz t PLL_PSERR Accuracy of PLL phase shift ±50 ps t ARESET t INCCJ (53)(54) t FOUTPJ (55) t FOUTCCJ (55) t OUTPJ (55) Minimum pulse width on the pll_ powerdown signal Input clock cycle-to-cycle jitter Period jitter for clock output in fractional mode Cycle-to-cycle jitter for clock output in fractional mode Period jitter for clock output in integer mode 10 ns F REF 100 MHz TBD UI (p-p) F REF < 100 MHz TBD ps (p-p) F OUT 100 MHz TBD ps (p-p) F OUT < 100 MHz TBD mui (p-p) F OUT 100 MHz TBD ps (p-p) F OUT < 100 MHz TBD mui (p-p) F OUT 100 MHz TBD ps (p-p) F OUT < 100 MHz TBD mui (p-p) (53) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps. (54) F REF is f IN /N, specification applies when N = 1. (55) External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Arria 10 Devices table.

38 38 I/O PLL Specifications Symbol Parameter Condition Min Typ Max Unit t OUTCCJ (55) dk BIT Cycle-to-cycle jitter for clock output in integer mode Bit number of Delta Sigma Modulator (DSM) F OUT 100 MHz TBD ps (p-p) F OUT < 100 MHz TBD mui (p-p) Related Information Memory Output Clock Jitter Specifications on page 58 Provides more information about the external memory interface clock output jitter specifications. I/O PLL Specifications Table 38: I/O PLL Specifications for Arria 10 Devices Preliminary f IN 32 bit Symbol Parameter Condition Min Typ Max Unit Input clock frequency 1 speed grade (56) MHz 2 speed grade (56) MHz 3 speed grade (56) MHz f INPFD Input clock frequency to the PFD MHz f VCO PLL VCO operating range 1 speed grade MHz 2 speed grade MHz 3 speed grade MHz f CLBW PLL closed-loop bandwidth MHz t EINDUTY f OUT Input clock or external feedback clock input duty cycle Output frequency for internal global or regional clock (C counter) % 1, 2, 3 speed grade 644 MHz (56) This specification is limited in the Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.