Stratix V Device Handbook Volume 3: Datasheet

Transcription

1 Stratix V Device Handbook Volume 3: Datasheet Stratix V Device Handbook Volume 3: Datasheet 101 Innovation Drive San Jose, CA SV5V

2 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Stratix V Device Handbook Volume 3: Datasheet December 2010 Altera Corporation

3 Contents Chapter Revision Dates v Chapter 1. DC and Switching Characteristics for Stratix V Devices Electrical Characteristics Operating Conditions Absolute Maximum Ratings Recommended Operating Conditions DC Characteristics Internal Weak Pull-Up Resistor I/O Standard Specifications Power Consumption Switching Characteristics Transceiver Performance Specifications Core Performance Specifications Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications JTAG Configuration Specifications Temperature Sensing Diode Specifications Periphery Performance High-Speed I/O Specification OCT Calibration Block Specifications Duty Cycle Distortion (DCD) Specifications I/O Timing Programmable IOE Delay Programmable Output Buffer Delay Glossary Document Revision History Additional Information How to Contact Altera Info 1 Typographic Conventions Info 1

4 iv Contents Stratix V Device Handbook Volume 3: Datasheet December 2010 Altera Corporation

5 Chapter Revision Dates The chapters in this document, Stratix V Device Handbook Volume 3, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. DC and Switching Characteristics for Stratix V Devices Revised: December 2010 Part Number: SV

6 vi Chapter Revision Dates Stratix V Device Handbook Volume 3: Datasheet December 2010 Altera Corporation

7 December 2010 SV DC and Switching Characteristics for Stratix V Devices SV Electrical Characteristics This chapter covers the electrical and switching characteristics for Stratix V devices. Electrical characteristics include operating conditions and power consumption. Switching characteristics include transceiver specifications, core, and periphery performance. This chapter also describes I/O timing, including programmable I/O element (IOE) delay and programmable output buffer delay. f For information regarding the densities and packages of devices in the Stratix V family, refer to the Stratix V Device Family Overview chapter. Operating Conditions When you use Stratix V devices, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Stratix V devices, you must consider the operating requirements described in this chapter. Stratix V devices are offered in commercial and industrial grades. Commercial devices are offered in 2 (fastest), 3, and 4 speed grades. Industrial devices are offered in 3, and 4 speed grades. Absolute Maximum Ratings Absolute maximum ratings define the maximum operating conditions for Stratix V devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions. c Conditions other than those listed in Table 1 1 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Table 1 1. Absolute Maximum Ratings for Stratix V DevicesPreliminary (Part 1 of 2) Symbol Description Minimum Maximum Unit V CC Core voltage and periphery circuitry power supply V V CCPT Power supply for programmable power technology V V CCPGM Configuration pins power supply V V CCAUX Auxiliary supply for the programmable power technology V V CCBAT Battery back-up power supply for design security volatile key register V V CCPD I/O pre-driver power supply V I/O power supply V V CCD_FPLL PLL digital power supply V 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Stratix V Device Handbook Volume 3: Datasheet December 2010 Subscribe

8 1 2 Chapter 1: DC and Switching Characteristics for Stratix V Devices Electrical Characteristics Table 1 1. Absolute Maximum Ratings for Stratix V DevicesPreliminary (Part 2 of 2) Symbol Description Minimum Maximum Unit V CCA_FPLL PLL analog power supply V V I DC input voltage V I OUT DC output current per pin ma T J Operating junction temperature C T STG Storage temperature (No bias) C Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage shown in Table 1 2 and undershoot to -2.0 V for input currents less than 100 ma and periods shorter than 20 ns. Table 1 2 lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 3.95 V can only be at 3.95 V for ~5% over the lifetime of the device; for a device lifetime of 10 years, this amounts to half of a year. Table 1 2. Maximum Allowed Overshoot During TransitionsPreliminary Symbol Description Condition (V) Overshoot Duration as T J = 100 C Unit % % % % Vi (AC) AC input voltage 4 12 % % % % % Stratix V Device Handbook Volume 3: Datasheet December 2010 Altera Corporation

9 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 3 Electrical Characteristics Recommended Operating Conditions This section lists the functional operation limits for the AC and DC parameters for Stratix V devices. Table 1 3 lists the steady-state voltage and current values expected from Stratix V devices. Power supply ramps must all be strictly monotonic, without plateaus. Table 1 3. Recommended Operating Conditions for Stratix V DevicesPreliminary Symbol Description Condition Minimum Typical Maximum Unit V CC Core voltage and periphery circuitry power supply V V CCPT Power supply for programmable power technology V V CCAUX Auxiliary supply for the programmable power technology V V CCPD (1) I/O pre-driver (3.0 V) power supply V I/O pre-driver (2.5 V) power supply V I/O buffers (3.0 V) power supply V I/O buffers (2.5 V) power supply V I/O buffers (1.8 V) power supply V I/O buffers (1.5 V) power supply V I/O buffers (1.35 V) power supply V I/O buffers (1.25 V) power supply V I/O buffers (1.2 V) power supply V V CCPGM Configuration pins (2.5 V) power supply V Configuration pins (3.0 V) power supply V Configuration pins (1.8 V) power supply V V CCA_FPLL PLL analog voltage regulator power supply V V CCD_FPLL PLL digital voltage regulator power supply V V CCBAT (2) Battery back-up power supply (For design security volatile key register) V V I DC input voltage V V O Output voltage 0 V T J Operating junction temperature Commercial 0 85 C Industrial C t RAMP (3) Power supply ramp time Normal POR (PORSEL=0) 200 µs 100 ms Fast POR (PORSEL=1) 200 µs 4 ms Notes to Table 1 3: (1) V CCPD must be 2.5 V when is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. V CCPD must be 3.0 V when is 3.0 V. (2) If you do not use design security feature in Stratix V devices, connect V CCBAT to a 2.5-V or 3.0-V power supply. Stratix V POR circuitry monitors V CCBAT. Stratix V devices will not exit POR if V CCBAT stays at logic low. (3) Each power supply must reach the recommended operating range with 200µs.

10 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 4 Electrical Characteristics Table 1 4 lists the transceiver power supply recommended operating conditions for Stratix V GX devices. Table 1 4. Transceiver Power Supply Operating Conditions for Stratix V GX and GS DevicesPreliminary Symbol Description Minimum Typical Maximum Unit V CCA_GXBL (1) V CCA_GXBR (1) V CCHIP_L V CCHIP_R V CCHSSI_L V CCHSSI_R V CCR_GXBL (2) V CCR_GXBR (2) V CCT_GXBL (2) V CCT_GXBR (2) V CCH_GXBL V CCH_GXBR Transceiver high voltage power (left side) Transceiver high voltage power (right side) Transceiver HIP digital power (left side) Transceiver HIP digital power (right side) Transceiver PCS power (left side) Transceiver PCS power (right side) Receiver power (left side) Receiver power (right side) Transmitter power (left side) Transmitter power (right side) Transmitter output buffer power (left side) Transmitter output buffer power (right side) 2.85, , , V V V 0.80, , , 1.05 V 0.80, , , 1.05 V V Notes to Table 1 4: (1) This supply must be connected to 3.0 V if the CMU PLL, receiver CDR, or both, are configured at a base data rate > 6.5 Gbps. Up to 6.5 Gbps, you can connect this supply to either 3.0 V or 2.5 V. (2) This supply must be connected to 1.0 V if the transceiver is configured at a data rate > 6.5 Gbps. Up to 6.5 Gbps, you can connect this supply to either 1.0 V or 0.85 V. DC Characteristics This section lists the supply current, I/O pin leakage current, input pin capacitance, on-chip termination tolerance, and hot socketing specifications. Supply Current Standby current is the current drawn from the respective power rails used for power budgeting. Use the Excel-based Early Power Estimator (EPE) to get supply current estimates for your design because these currents vary greatly with the resources you use. f For more information about power estimation tools, refer to the PowerPlay Early Power Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II Handbook. I/O Pin Leakage Current Table 1 5 lists the Stratix V I/O pin leakage current specifications. Table 1 5. I/O Pin Leakage Current for Stratix V DevicesPreliminary Symbol Description Conditions Min Typ Max Unit I I Input pin V I = 0 V to MAX µa I OZ Tri-stated I/O pin V O = 0 V to MAX µa

11 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 5 Electrical Characteristics Bus Hold Specifications Table 1 6 lists the Stratix V device family bus hold specifications. Table 1 6. Bus Hold ParametersPreliminary Parameter Symbol Conditions 1.2 V 1.5 V 1.8 V 2.5 V 3.0 V Unit Low sustaining current High sustaining current Low overdrive current High overdrive current Bus-hold trip point I SUSL I SUSH V IN > V IL (maximum) V IN < V IH (minimum) Min Max Min Max Min Max Min Max Min Max µa µa I ODL 0V < V IN < µa I ODH 0V < V IN < µa V TRIP V On-Chip Termination (OCT) Specifications If you enable OCT calibration, calibration is automatically performed at power-up for I/Os connected to the calibration block. Table 1 7 lists the Stratix V OCT termination calibration accuracy specifications. Table 1 7. Stratix V OCT Calibration Accuracy SpecificationsPreliminary (Part 1 of 2) (Note 1) Symbol Description Conditions Internal series termination 25- R S with calibration (25- setting) Internal series termination 50- R S with calibration (50- setting) Internal series termination 34- and 40- R S with calibration (34- and 40- setting) Internal series termination and with calibration ( R S 60- and 80- setting) Internal parallel 50- R T termination with calibration (50- setting) = 3.0, 2.5, 1.8, 1.5, 1.2 V = 3.0, 2.5, 1.8, 1.5, 1.2 V = 1.5, 1.35, 1.25, 1.2 V Calibration Accuracy C2 C3,I3 C4,I4 Unit ± 15 ± 15 ± 15 % ± 15 ± 15 ± 15 % ± 15 ± 15 ± 15 % = 1.2 V ± 15 ± 15 ± 15 % = 2.5, 1.8, 1.5, 1.2 V -10 to to to +40 %

12 1 6 Chapter 1: DC and Switching Characteristics for Stratix V Devices Electrical Characteristics Table 1 7. Stratix V OCT Calibration Accuracy SpecificationsPreliminary (Part 2 of 2) (Note 1) Symbol Description Conditions 20-, 30-, 40-,60- and 120- R T Internal parallel termination with calibration (20-, and 120- setting) Internal parallel termination with 60- and 120- R T calibration (60- and 120- setting) Internal left shift series termination with 25- R S_left_shift calibration (25- R S_left_shift setting) Note to Table 1 7: (1) OCT calibration accuracy is valid at the time of calibration only. = 1.5, 1.35, 1.25 V -10 to to to +40 % = to to to +40 % = 3.0, 2.5, 1.8, 1.5, 1.2 V Calibration Accuracy C2 C3,I3 C4,I4 ± 15 ± 15 ± 15 % Calibration accuracy for the calibrated series and parallel OCTs are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change. Table 1 8 lists the Stratix V OCT without calibration resistance tolerance to PVT changes. Table 1 8. Stratix V OCT Without Calibration Resistance Tolerance SpecificationsPreliminary (Part 1 of 2) (Note 1) Symbol Description Conditions Internal series termination 25- R S without calibration (25- setting) Internal series termination 25- R S without calibration (25- setting) Internal series termination 25- R S without calibration (25- setting) Internal series termination 50- R S without calibration (50- setting) Internal series termination 50- R S without calibration (50- setting) Internal series termination 50- R S without calibration (50- setting) Resistance Tolerance C2 C3,I3 C4,I4 Unit = 3.0 and 2.5 V ± 30 ± 40 ± 40 % = 1.8 and 1.5 V ± 30 ± 40 ± 40 % Unit = 1.2 V ± 35 ± 50 ± 50 % = 3.0 and 2.5 V ± 30 ± 40 ± 40 % = 1.8 and 1.5 V ± 30 ± 40 ± 40 % = 1.2 V ± 35 ± 50 ± 50 % Stratix V Device Handbook Volume 3: Datasheet December 2010 Altera Corporation

13 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 7 Electrical Characteristics Table 1 8. Stratix V OCT Without Calibration Resistance Tolerance SpecificationsPreliminary (Part 2 of 2) (Note 1) Symbol Description Conditions 100- R D Internal differential termination (100- setting) Note to Table 1 8: (1) Pending silicon characterization. Resistance Tolerance C2 C3,I3 C4,I4 Unit = 2.5 V ± 25 ± 25 ± 25 % OCT calibration is automatically performed at power-up for OCT-enabled I/Os. Table 1 9 lists OCT variation with temperature and voltage after power-up calibration. Use Table 1 9 to determine the OCT variation after power-up calibration and Equation 1 1 to determine the OCT variation without re-calibration. Equation 1 1. OCT Variation Without Re-CalibrationPreliminary (Note 1), (2), (3), (4), (5), (6) dr R OCT R SCAL dr = T V dt dv Notes to Equation 1 1: (1) The R OCT value calculated from Equation 1 1 shows the range of OCT resistance with the variation of temperature and. (2) R SCAL is the OCT resistance value at power-up. (3) T is the variation of temperature with respect to the temperature at power-up. (4) V is the variation of voltage with respect to the at power-up. (5) dr/dt is the percentage change of R SCAL with temperature. (6) dr/dv is the percentage change of R SCAL with voltage. Table 1 9 lists the on-chip termination variation after the power-up calibration. Table 1 9. OCT Variation after Power-Up CalibrationPreliminary (Note 1), (2) Symbol Description (V) Typical Unit dr/dv OCT variation with voltage without re-calibration %/mv dr/dt OCT variation with temperature without re-calibration %/ C Note to Table 1 9: (1) Valid for range of ±5% and temperature range of 0 to 85 C. (2) Pending silicon characterization.

14 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 8 Electrical Characteristics Pin Capacitance Table 1 10 lists the Stratix V device family pin capacitance. Table Pin Capacitance for Stratix V DevicesPreliminary Symbol Description Typical Unit C IOTB Input capacitance on top/bottom I/O pins 5.5 pf C IOLR Input capacitance on left/right I/O pins 5.5 pf C OUTFB Input capacitance on dual-purpose clock output/feedback pins 5.5 pf Hot Socketing Table 1 11 lists the hot socketing specifications for Stratix V devices. Table Hot Socketing Specifications for Stratix V DevicesPreliminary Symbol Description Maximum I IOPIN (DC) DC current per I/O pin 300 A I IOPIN (AC) AC current per I/O pin 8 ma (1) I XCVR-TX (DC) (2) DC current per transceiver TX pin 100 ma I XCVR-RX (DC) (2) DC current per transceiver RX pin 50 ma Notes to Table 1 11: (1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, I IOPIN = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew rate. (2) These specifications are preliminary. Internal Weak Pull-Up Resistor Table 1 12 lists the weak pull-up resistor values for Stratix V devices. Table Stratix V Internal Weak Pull-Up ResistorPreliminary (Note 1), (2) Symbol Description Conditions (3) Min Typ Max Unit = 3.0 V ±5% 25 k R PU Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled. = 2.5 V ±5% 25 k = 1.8 V ±5% 25 k = 1.5 V ±5% 25 k = 1.35 V ±5% 25 k = 1.25 V ±5% 25 k = 1.2 V ±5% 25 k Notes to Table 1 12: (1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins. (2) The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak pull-down resistor is approximately 25 k (3) Pin pull-up resistance values may be lower if an external source drives the pin higher than.

15 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 9 Electrical Characteristics I/O Standard Specifications Table 1 13 through Table 1 18 list the input voltage (V IH and V IL ), output voltage (V OH and V OL ), and current drive characteristics (I OH and I OL ) for various I/O standards supported by Stratix V devices. These tables also show the Stratix V device family I/O standard specifications. The V OL and V OH values are valid at the corresponding I OH and I OL, respectively. For an explanation of terms used in Table 1 13 through Table 1 18, refer to Glossary on page Table Single-Ended I/O StandardsPreliminary I/O Standard (V) V IL (V) V IH (V) V OL (V) V OH (V) Min Typ Max Min Max Min Max Max Min LVTTL LVCMOS V V V V * 0.65 * * 0.65 * * 0.65 * I OL (ma) I OH (ma) * 0.75 * * 0.75 * 2-2 Table Single-Ended SSTL and HSTL I/O Reference Voltage SpecificationsPreliminary I/O Standard SSTL-2 SSTL-18 SSTL-15 SSTL 135 SSTL 125 SSTL 12 HSTL-18 HSTL-15 HSTL-12 (V) V REF (V) V TT (V) Min Typ Max Min Typ Max Min Typ Max 0.49 * 0.51 * V * CCIO 0.04 V REF * 0.5 * 0.51 * 0.49 * 0.5 * VCCIO V REF 0.04 V REF * 0.49 * 0.5 * 0.51 * 0.49 * 0.5 * 0.51 * 0.49 * 0.51 * 0.49 * 0.5 * 0.5 * V CCIO VCCIO 0.49 * 0.51 * 0.49 * 0.5 * 0.5 * V CCIO VCCIO 0.51 * 0.51 * / / HSUL * 0.53 * 0.5 * V CCIO / * 0.51 * 0.5 * V CCIO

16 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 10 Electrical Characteristics Table Single-Ended SSTL and HSTL I/O Standards Signal SpecificationsPreliminary I/O Standard SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II SSTL-15 Class I SSTL-15 Class II SSTL 135 SSTL 125 SSTL 12 HSTL-18 Class I HSTL-18 Class II HSTL-15 Class I HSTL-15 Class II HSTL-12 Class I HSTL-12 Class II V IL(DC) (V) V IH(DC) (V) V IL(AC) (V) V IH(AC) (V) V OL (V) V OH (V) Min Max Min Max Max Min Max Min HSUL Note to Table 1 15: (1) Pending silicon characterization V TT V TT V TT V TT V TT V TT I ol (ma) I oh (ma) * 0.8 * * 0.8 * TBD (1) TBD (1) TBD (1) TBD (1) 0.15 TBD (1) TBD (1) TBD (1) TBD (1) 0.15 TBD (1) TBD (1) TBD (1) TBD (1) * 0.75* * 0.75* * 0.9* TBD (1) TBD (1)

17 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 11 Electrical Characteristics Table Differential SSTL I/O StandardsPreliminary I/O Standard SSTL-2 SSTL-18 SSTL-15 SSTL 135 SSTL 125 SSTL 12 (V) V SWING(DC) (V) V X(AC) (V) V SWING(AC) (V) V OX(AC) (V) Min Typ Max Min Max Min Typ Max Min Max Min Typ Max /2-0.2 / / / / / / / / Note to Table 1 16: (1) Pending silicon characterization. TBD (1) TBD (1) V REF /2 TBD (1) /2 V REF / TBD (1) 0.15 TBD (1) TBD (1) TBD (1) V REF TBD (1) TBD (1) TBD (1) TBD (1) V REF TBD (1) TBD (1) Table Differential HSTL I/O StandardsPreliminary I/O Standard HSTL-18 HSTL-15 HSTL-12 (V) V DIF(DC) (V) V X(AC) (V) V CM(DC) (V) V DIF(AC) (V) Min Typ Max Min Max Min Typ Max Min Typ Max Min Max HSUL * * 0.5* 0.5* * 0.5* 0.6* * 0.5* 0.6* Table Differential I/O Standard SpecificationsPreliminary (Note 1) (Part 1 of 2) I/O Standard PCML 2.5 V LVDS RSDS (HIO) (V) V ID (mv) V ICM(DC) (V) V OD (V) (2) V OCM (V) (2) Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For transmitter, receiver, and reference clock I/O pin specifications, refer to Table 1 19 on page V CM = 1.25 V V CM = 1.25 V D MAX 700 Mbps D MAX > 700 Mbps

18 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 12 Switching Characteristics Table Differential I/O Standard SpecificationsPreliminary (Note 1) (Part 2 of 2) I/O Standard Mini- LVDS (HIO) LVPECL (V) V ID (mv) V ICM(DC) (V) V OD (V) (2) V OCM (V) (2) Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max D MAX 700 Mbps D MAX > 700 Mbps 1.8 (3) 1.6 (3) Notes to Table 1 18: (1) The 1.4-V and 1.5-V PCML transceiver I/O standard specifications are described in Transceiver Performance Specifications on page (2) RL range: 90 RL 110. (3) For D MAX > 700 Mbps, the minimum input voltage is 0.85 V; the maximum input voltage is 1.75 V. For F MAX 700 Mbps, the minimum input voltage is 0.45 V; the maximum input voltage is 1.95 V. Power Consumption Altera offers two ways to estimate power consumption for a designthe Excel-based Early Power Estimator and the Quartus II PowerPlay Power Analyzer feature. 1 You typically use the interactive Excel-based Early Power Estimator before designing the FPGA to get a magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yields very accurate power estimates. f For more information about power estimation tools, refer to the PowerPlay Early Power Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II Handbook. Switching Characteristics This section provides performance characteristics of Stratix V core and periphery blocks for commercial grade devices. These characteristics can be designated as Preliminary or Final. Preliminary characteristics are created using simulation results, process data, and other known parameters. The title of these tables show the designation as Preliminary. Final numbers are based on actual silicon characterization and testing. The numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. There are no designations on finalized tables.

19 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 13 Switching Characteristics Transceiver Performance Specifications This section describes transceiver performance specifications. Table 1 19 lists the Stratix V GX and GS transceiver specifications. Table Transceiver Specifications for Stratix V GX and GS DevicesPreliminary (Part 1 of 3) (Note 1) Symbol/ Description Conditions 2 Commercial Speed Grade 3 Commercial/Industrial Speed Grade 4 Commercial/Industrial Speed Grade Unit Min Typ Max Min Typ Max Min Typ Max Reference Clock Supported I/O Standards 1.2 V PCML, 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL, LVDS, HCSL Input frequency from REFCLK input pins MHz Duty cycle % Spread-spectrum modulating clock frequency Spread-spectrum downspread PCI Express (PCIe) PCIe khz 0 to -0.5% 0 to -0.5% 0 to -0.5% On-chip termination resistors V ICM (AC coupled) 1000/850 (2) 1000/850 (2) 1000/850 (2) mv HCSL I/O V ICM (DC coupled) standard for PCIe reference clock mv R REF 2000 ±1% 2000 ± 1% 2000 ± 1% Transceiver Clocks fixedclk clock frequency Avalon-MM PHY management clock frequency PCIe Receiver Detect MHz < 150 MHz Receiver Supported I/O Standards 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, LVDS Data rate (Standard PCS) Mbps Data rate (10G PCS) Mbps Absolute V MAX for a receiver pin (3) V Absolute V MIN for a receiver pin V

20 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 14 Switching Characteristics Table Transceiver Specifications for Stratix V GX and GS DevicesPreliminary (Part 2 of 3) (Note 1) Symbol/ Description Maximum peak-to-peak differential input voltage V ID (diff p-p) before device configuration Maximum peak-to-peak differential input voltage V ID (diff p-p) after device configuration Minimum differential eye opening at receiver serial input pins (4) Differential on-chip termination resistors Programmable equalization Programmable DC gain Conditions V V CCR_GXB = 1.0 V and V ICM = 0.65V V CCR_GX B = 0.85V and V ICM = 0.55V V V mv 85 setting setting setting setting db DC Gain Setting = 0 DC Gain Setting = 1 DC Gain Setting = 2 DC Gain Setting = 3 DC Gain Setting = 4 2 Commercial Speed Grade 3 Commercial/Industrial Speed Grade 4 Commercial/Industrial Speed Grade Min Typ Max Min Typ Max Min Typ Max db db db db db Unit Transmitter Supported I/O Standards 1.4 V PCML, 1.5 V PCML Data rate (Standard PCS) Mbps Data rate (10G PCS) Mbps V OCM 0.65 V setting mv 85 setting Differential on-chip 100 setting termination resistors 120 setting setting

21 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 15 Switching Characteristics Table Transceiver Specifications for Stratix V GX and GS DevicesPreliminary (Part 3 of 3) (Note 1) Symbol/ Description Conditions 2 Commercial Speed Grade 3 Commercial/Industrial Speed Grade 4 Commercial/Industrial Speed Grade Unit Min Typ Max Min Typ Max Min Typ Max Transmitter Rise time (5) ps Fall time (5) ps CMU PLL Supported Data Range Mbps ATX PLL Supported Data Range Mbps Input Reference Clock Frequency (6) MHz Transceiver-FPGA Fabric Interface Interface speed MHz Notes to Table 1 19: (1) Speed grades shown in Table 1 19 refer to the Transceiver Speed Grade in the device ordering code. For more information about device ordering codes, refer to the Stratix V Device Family Overview chapter. (2) The reference clock common mode voltage is equal to the V CCR_GXB power supply level. (3) The device cannot tolerate prolonged operation at this absolute maximum. (4) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. (5) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode. (6) The input reference clock frequency options depend on the data rate and the device speed grade. Core Performance Specifications This section describes the clock tree, phase-locked loop (PLL), digital signal processing (DSP), memory blocks, configuration, and JTAG specifications. Clock Tree Specifications Table 1 20 lists the clock tree specifications for Stratix V devices. Table Clock Tree Performance for Stratix V DevicesPreliminary Performance Unit Symbol 2 Speed Grade 3 Speed Grade 4 Speed Grade GCLK and RCLK MHz PCLK MHz PLL Specifications Table 1 21 lists the Stratix V PLL specifications when operating in both the commercial junction temperature range (0 to 85 C) and the industrial junction temperature range (-40 to 100 C).

22 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 16 Switching Characteristics Table PLL Specifications for Stratix V Devices (Part 1 of 2)Preliminary (Note 1) Symbol Parameter Min Typ Max Unit f IN Input clock frequency ( 3 speed grade) (2) MHz Input clock frequency ( 2 speed grade) (2) MHz Input clock frequency ( 4 speed grade) (2) MHz f INPFD Input frequency to the PFD MHz f FINPFD Fractional Input clock frequency to the PFD MHz f VCO PLL VCO operating range ( 3 speed grade) MHz PLL VCO operating range ( 2 speed grade) MHz PLL VCO operating range ( 4 speed grade) MHz t EINDUTY Input clock or external feedback clock input duty cycle % f OUT Output frequency for internal global or regional clock ( 2 speed grade) Output frequency for internal global or regional clock ( 3 speed grade) Output frequency for internal global or regional clock ( 4 speed grade) 1600 (3) MHz 1334 (3) MHz 1066 (3) MHz f OUT_EXT Output frequency for external clock output ( 3 speed grade) 667 (3) MHz Output frequency for external clock output ( 2 speed grade) 800 (3) MHz Output frequency for external clock output ( 4 speed grade) 533 (3) MHz t OUTDUTY Duty cycle for external clock output (when set to 50%) % t FCOMP External feedback clock compensation time 10 ns t CONFIGPHASE Time required to reconfigure phase shift TBD (1) f DYCONFIGCLK Dynamic Configuration Clock 100 MHz t LOCK Time required to lock from end-of-device configuration or de-assertion of areset 1 ms t DLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) 1 ms f CLBW PLL closed-loop medium bandwidth 1.5 MHz PLL closed-loop low bandwidth 0.3 MHz PLL closed-loop high bandwidth (8) 4 MHz t PLL_PSERR Accuracy of PLL phase shift ±50 ps t ARESET Minimum pulse width on the areset signal 10 ns t INCCJ (4), (5) Input clock cycle to cycle jitter (F REF 100 MHz) 0.15 UI (p-p) Input clock cycle to cycle jitter (F REF < 100 MHz) ps (p-p) t OUTPJ_DC (6) Period Jitter for dedicated clock output (F OUT 100 MHz) TBD (1) ps (p-p) Period Jitter for dedicated clock output (F OUT < 100 MHz) TBD (1) mui (p-p) t OUTCCJ_DC (6) Cycle to Cycle Jitter for dedicated clock output (F OUT 100 MHz) TBD (1) ps (p-p) Cycle to Cycle Jitter for dedicated clock output (F OUT < 100 MHz) TBD (1) mui (p-p)

23 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 17 Switching Characteristics Table PLL Specifications for Stratix V Devices (Part 2 of 2)Preliminary (Note 1) t OUTPJ_IO (6), (9) t OUTCCJ_IO (6), (9) t CASC_OUTPJ_DC (6), (7) f DRIFT Symbol Parameter Min Typ Max Unit Period Jitter for clock output on regular I/O (F OUT 100 MHz) Period Jitter for clock output on regular I/O (F OUT < 100 MHz) Cycle to Cycle Jitter for clock output on regular I/O (F OUT 100 MHz) Cycle to Cycle Jitter for clock output on regular I/O (F OUT < 100 MHz) Period Jitter for dedicated clock output in cascaded PLLs (F OUT 100 MHz) Period Jitter for dedicated clock output in cascaded PLLs (F OUT < 100 MHz) Frequency drift after PFDENA is disabled for duration of 100 µs TBD (1) ps (p-p) TBD (1) mui (p-p) TBD (1) ps (p-p) TBD (1) mui (p-p) TBD (1) ps (p-p) TBD (1) mui (p-p) ±10 % dk BIT Bit number of Delta Sigma Modulator (DSM) 24 Bits k VALUE Numerator of Fraction f RES Resolution of VCO frequency (f INPFD =100 MHz) 5.96 Hz Notes to Table 1 21: (1) Pending silicon characterization. (2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. (3) This specification is limited by the lower of the two: I/O F MAX or F OUT of the PLL. (4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source < 120 ps. (5) F REF is fin/n when N = 1. (6) Peak-to-peak jitter with a probability level of (14 sigma, % confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different measurement method and are available in Table 1 33 on page (7) The cascaded PLL specification is only applicable with the following condition: a. Upstream PLL: 0.59Mhz Upstream PLL BW < 1 MHz b. Downstream PLL: Downstream PLL BW > 2 MHz (8) High bandwidth PLL settings are not supported in external feedback mode. (9) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 1 31 on page 1 26.

24 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 18 Switching Characteristics DSP Block Specifications Table 1 22 lists the Stratix V DSP block performance specifications. Table Block Performance Specifications for Stratix V DSP DevicesPreliminary (Note 1) Mode Modes using One DSP 2 Speed Grade Performance 3 Speed Grade 4 Speed Grade Three MHz One MHz Two partial (or 16 16) MHz One MHz One MHz One sum of two (One sum of ) MHz One sum of square MHz One plus 36 (a b) + c MHz Modes using Two DSPs Three MHz One sum of four MHz One sum of two MHz One sum of two MHz One complex MHz One MHz Modes using Three DSPs One complex MHz Modes using Four DSPs One complex MHz Note to Table 1 22: (1) The numbers are preliminary pending silicon characterization. Unit

25 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 19 Switching Characteristics Memory Block Specifications Table 1 23 lists the Stratix V memory block specifications. Table Memory Block Performance Specifications for Stratix V DevicesPreliminary (Note 1), (2), (3) Memory MLAB M20K Block Mode Resources Used ALUTs Memory C2 Speed Grade Performance C3,I3 Speed Grade C4,I4 Speed Grade Single port, all supported widths MHz Simple dual-port, all supported widths MHz ROM, all supported widths MHz Single-port, all supported widths MHz Single port with the read-during-write option set to MHz Old Data, all supported widths Simple dual-port, all supported widths MHz Simple dual-port with the read-during-write option set to MHz Old Data, all supported widths Simple dual-port with ECC enabled, MHz Simple dual-port with ECC and optional pipeline registers MHz enabled, True dual port, all supported widths MHz True dual-port with the read-during-write option set to MHz Old Data, all supported widths ROM, all supported widths MHz Min Pulse Width (clock high time) ps Min Pulse Width (clock low time) ps Unit Notes to Table 1 23: (1) The numbers are preliminary pending silicon characterization. (2) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes. (3) When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in F MAX.

26 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 20 Switching Characteristics JTAG Configuration Specifications Table 1 24 lists the JTAG timing parameters and values for Stratix V devices. Table JTAG Timing Parameters and Values for Stratix V DevicesPreliminary (Note 1) Symbol Description Min Max Unit t JCP TCK clock period 30 ns t JCH TCK clock high time 14 ns t JCL TCK clock low time 14 ns t JPSU (TDI) TDI JTAG port setup time 1 ns t JPSU (TMS) TMS JTAG port setup time 3 ns t JPH JTAG port hold time 5 ns t JPCO JTAG port clock to output 11 (2) ns t JPZX JTAG port high impedance to valid output 14 (2) ns t JPXZ JTAG port valid output to high impedance 14 (2) ns Notes to Table 1 24: (1) The numbers are preliminary pending silicon characterization. (2) A 1 ns adder is required for each voltage step down from 3.0 V. For example, t JPCO = 12 ns if of the TDO I/O bank = 2.5 V, or 13 ns if it equals 1.8 V. Temperature Sensing Diode Specifications Table 1 25 lists the specifications for the Stratix V temperature sensing diode. Table External Temperature Sensing Diode SpecificationsPreliminary Description Min Typ Max Unit I bias, diode source current A V bias, voltage across diode V Series resistance < 5 Diode ideality factor Periphery Performance This section describes periphery performance, including high-speed I/O and external memory interface. I/O performance supports several system interfaces, such as the LVDS high-speed I/O interface, external memory interface, and the PCI/PCI-X bus interface. General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-LVTTL/LVCMOS are capable of typical 167 MHz and 1.2 LVCMOS at 100 MHz interfacing frequency with 10 pf load. 1 Actual achievable frequency depends on design- and system-specific factors. You must perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

27 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 21 Switching Characteristics High-Speed I/O Specification Table 1 26 lists high-speed I/O timing for Stratix V devices. Table High-Speed I/O SpecificationsPreliminary (Note 1), (2), (3) (Part 1 of 2) Symbol f HSCLK_in (input clock frequency) True Differential I/O Standards f HSCLK_in (input clock frequency) Single Ended I/O Standards (4) f HSCLK_in (input clock frequency) Single Ended I/O Standards (3) f HSCLK_OUT (output clock frequency) Conditions Clock boost factor W = 1 to 40 (5) Clock boost factor W = 1 to 40 (5) Clock boost factor W = 1 to 40 (5) 2 Speed Grade 3 Speed Grade 4 Speed Grade Min Typ Max Min Typ Max Min Typ Max Unit MHz MHz MHz (6) (6) (6) MHz Transmitter True Differential I/O Standards - f HSDR (data rate) Emulated Differential I/O Standards with Three External Output Resistor Networks - f HSDR (data rate) (8) t x Jitter - True Differential I/O Standards t x Jitter - Emulated Differential I/O Standards with Three External Output Resistor Network t DUTY SERDES factor J = 3 to 10 (10) SERDES factor J = 2, Uses DDR Registers SERDES factor J = 1, Uses SDR Register (7) 1434 (7) 1250 (7) 1050 Mbps (7) (7) (7) (7) (7) (7) Mbps (7) (7) (7) (7) (7) (7) Mbps SERDES factor J = 4 to 10 (7) 1100 (7) 840 (7) 840 Mbps Total Jitter for Data Rate, 600 Mbps Gbps Total Jitter for Data Rate, < 600 Mbps Total Jitter for Data Rate, 600 Mbps Gbps Total Jitter for Data Rate < 600 Mbps Tx output clock duty cycle for both True and Emulated Differential I/O Standards ps UI ps UI %

28 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 22 Switching Characteristics Table High-Speed I/O SpecificationsPreliminary (Note 1), (2), (3) (Part 2 of 2) t RISE & t FALL TCCS Symbol Conditions True Differential I/O Standards ps Emulated Differential I/O Standards with Three External Output Resistor Networks ps True Differential I/O Standards ps Emulated Differential I/O Standards 2 Speed Grade 3 Speed Grade 4 Speed Grade Min Typ Max Min Typ Max Min Typ Max ps Unit Receiver True Differential I/O Standards - f HSDRDPA (data rate) f HSDR (data rate) SERDES factor J = 3 to Mbps SERDES factor J = 3 to 10 (7) (9) (7) (9) (7) (9) Mbps SERDES factor J = 2, Uses DDR Registers (7) (7) (7) (7) (7) (7) Mbps SERDES factor J = 1, Uses SDR Register (7) (7) (7) (7) (7) (7) Mbps DPA Mode DPA run length UI Soft CDR mode Soft-CDR PPM tolerance Non DPA Mode ± PPM Sampling Window ps Notes to Table 1 26: (1) When J = 3 to 10, use the serializer/deserializer (SERDES) block. (2) When J = 1 or 2, bypass the SERDES block. (3) This only applies to LVDS source synchronous mode. (4) This only applies to DPA and soft-cdr modes. (5) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate. (6) This is achieved by using the LVDS clock network. (7) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate. (8) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin. (9) You can estimate the achievable maximum data rate for non-dpa mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported. (10) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.

29 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 23 Switching Characteristics Figure 1 1 shows the DPA lock time specifications with the DPA PLL calibration option enabled. Figure 1 1. DPA Lock Time Specification with DPA PLL Calibration Enabled rx_reset rx_dpa_locked DPA Lock Time 256 data transitions 96 slow clock cycles 256 data transitions 96 slow clock cycles 256 data transitions Table 1 27 lists the DPA lock time specifications for Stratix V GX devices. Table DPA Lock Time SpecificationsStratix V GX Devices OnlyPreliminary (Note 1), (2), (3) Standard Training Pattern Number of Data Transitions in One Repetition of the Training Pattern Number of Repetitions per 256 Data Transitions (4) Maximum SPI data transitions Parallel Rapid I/O data transitions data transitions Miscellaneous data transitions data transitions Notes to Table 1 27: (1) The DPA lock time is for one channel. (2) One data transition is defined as a 0-to-1 or 1-to-0 transition. (3) The DPA lock time stated in this table applies to both commercial and industrial grade. (4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.

30 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 24 Switching Characteristics Figure 1 2 shows the LVDS soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate equal to or higher than 1.25 Gbps. Table 1 28 lists this information in table form. Figure 1 2. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to or Higher Than 1.25 Gbps LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification 25 Jitter Amphlitude (UI) F1 F2 F3 F4 Jitter Frequency (Hz) Table 1 28 lists the LVDS soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate equal to or higher than 1.25 Gbps. Table LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to or Higher than 1.25 GbpsPreliminary Jitter Frequency (Hz) Sinusoidal Jitter (UI) F1 10, F2 17, F3 1,493, F4 50,000,

31 Chapter 1: DC and Switching Characteristics for Stratix V Devices 1 25 Switching Characteristics Figure 1 3 shows the LVDS soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate less than 1.25 Gbps. Figure 1 3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps Sinusoidal Jitter Amplitude 20db/dec 0.1 UI P-P baud/ MHz Frequency DLL and DQS Logic Block Specifications Table 1 29 lists the DQS phase offset delay per stage for Stratix V devices. Table DQS Phase Offset Delay Per Setting for Stratix V DevicesPreliminary (Note 1), (2), (3) Speed Grade Min Max Unit ps ps ps Notes to Table 1 29: (1) The numbers are preliminary pending silicon characterization. (2) The typical value equals the average of the minimum and maximum values. (3) The delay settings are linear, with a cumulative delay variation of 40 ps for all speed grades. For example, when using a 2 speed grade and applying a 10 phase offset settings to a 90 phase shift at 400 MHz, the expected average cumulative delay is [625 ps + (10 10 ps) ± 20 ps] = 725 ps ± 20 ps. Table 1 30 lists the DQS phase shift error for Stratix V devices. Table DQS Phase Shift Error Specification for DLL-Delayed Clock (t DQS_PSERR ) for Stratix V DevicesPreliminary (Note 1), (2) (Part 1 of 2) Number of DQS Delay Buffer 2 Speed Grade 3 Speed Grade 4 Speed Grade Unit ps ps ps