NF1011 Frequency Translator and Jitter Attenuator

Transcription

1 NF1011 Frequency Translator and Jitter Attenuator 2111 Comprehensive Drive Aurora, Illinois Phone: Fax: P R O D U C T General Description The NF1011 is a high performance frequency translator and jitter attenuator which is designed to meet requirements for multiple applications where low phase noise and ultra low jitter outputs are required including: frequency translation supporting wireless communication, 40G,100G and 400G Synchronous Ethernet, Sonet, OTN and IEEE 1588 network elements, clock translation with low phase noise, and other applications demanding sub-picosecond jitter performance. The NF1011 consists of a PLL stage that attenuates the jitter of the reference input with the use of an integrated phase detector, charge pump and external VCXO. The NF1011 generates a single-ended LVCMOS clock output channel based on the frequency of the external VCXO. The NF1011 accepts one reference input. The REF input can accept a single-ended LVCMOS clock signal. The LVCMOS input can take any frequency from 8KHz to 160MHz. The NF1011 is supported by an external LVCMOS VCXO from 1MHz to 160MHz. Features Simple operation accepts one input and one output channel. Reference input accepts one single-ended LVCMOS clock signal from 8 khz up to 160MHz. Generates one output channel based on the frequency of the external VCXO which drives one single-ended LVCMOS output. Frequency range of LVCMOS output is 1MHz to 160MHz Internal one time programmable (OTP) memory bank Programmable phase detector rate of PLL is minimum 8kHz to 500 KHz Accepts a 3.3V LVCMOS VCXO at frequencies from 1MHz to 160MHz. Capable of <120fs jitter performance over 12kHz-20MHz band Programmable Charge Pump current Minimal external components required due to internal charge pump Caps Supports I2C bus interface Operating temperature range of -40oC to +85oC 3.3V operation 32-pin QFN package (4mm x 4mm) B R I E F Functional Block Diagram Bulletin TM131 Revision 3.1 Date 07 Dec 2017

2 General Description The NF1011 is a frequency translator and jitter attenuator. Fundamentally, the input PLL consists of a phase-frequency detector (PFD), charge pump, passive loop filter, and an external VCXO operating in a closed loop. The NF1011 PLL has the flexibility to operate with a loop bandwidth of approximately 10Hz to 200 Hz. This relatively narrow loop bandwidth gives the NF1011 the ability to suppress jitter that appears on the input reference. The output of the PLL then becomes a low jitter phase-locked version of the reference input system clock. The charge pump current and phase frequency detector are programmable in the NF1011. An external capacitor is required for the NF1011 s loop filter. Typically, this loop filter may operate at 100Hz when a 0.22uF capacitor is connected. The NF1011 is capable of attenuating the jitter of the reference input with approximately 40fs additive jitter to that of the external 3.3V VCXO system clock when properly configured and a design implementation incorporating low noise PCB layout techniques. Reference Inputs The NF1011 accepts one reference input source. The incoming reference input is single-ended mode (LVCMOS) supporting frequencies from 8KHz up to 160MHz. Clock Outputs continued The frequency range of the LVCMOS clock output is from 8 KHz to 200 MHz. The output RMS jitter performance of the NF1011 is determined by the jitter performance of the external VCXO used but is capable of <.2 picosecond level over integration range from 12kHz to 20MHz. Optimizing spurs may involve some trial and error. Phase detector spurs occur at an offset from the carrier equal to the phase detector frequency, fpd. To minimize this spur, a lower phase detector frequency should be considered. In some cases where the loop bandwidth is very wide relative to the phase detector frequency, some benefit might be gained from using a narrower loop bandwidth. Bypassing at the supply pins and board layout can also have an impact on this spur, especially at higher phase detector frequencies. It is important to set the PLL to best possible bandwidth to minimize output jitter. A high bandwidth ( 100-kHz) provides best input signal tracking and is therefore desired with a clean input reference (clock generator mode). A low bandwidth ( 1-kHz) is desired if the input signal quality is unknown (jitter cleaner mode). 100MHz LVCMOS Output (locked to 10MHz TXCO REF input) PLL Input Dividers The reference input feeds a dedicated reference divider block. The input divider provides division of the reference in integer. The size of the divider for single ended inputs is 16 bit. The divider provides the bulk of the frequency pre-scaling that is necessary to reduce the reference frequency to accommodate the bandwidth that is typically desired for the PLL. Phase Frequency Detector The phase frequency detector range of the NF1011 is 8KHz to 500KHz. Charge Pump The NF1011 charge pump current is programmable in a range of 0 to 320uA. PLL Loop Filter The PLL loop filter requires the connection of an external capacitor between pins PUMP_C+ (pin 23) and PUMP_C- (pin24). The value of the external capacitor depends upon the characteristics of the VCXO, as well as such configuration parameters as input clock rate and desired bandwidth. An external R-C low pass filter can also be used at the BUFOUT_1 (pin 21) and BUFOUT_2 (pin 22) optionally. This R-C network filters the noise associated with the VCXO voltage control pin to achieve the best phase noise performance. Clock Outputs The NF1011 supports a single ended VCXO into pin 18 (SI). The output clock is generated on Pin 17 (SO) at the same frequency of the VCXO. Lock Status and Loss of Signal Alarm Lock (LOCK) and Loss of Signal (LOS) are detected and two pins are available to indicate whether the PLL is in lock or if a loss of signal has occurred. Pin LOCK indicates when the PLL is locked to the incoming reference. Alarm pin, LOS, indicates loss of signal on the reference input. NF1011 Power Requirements The NF1011 requires a 3.3V digital power input (VDD) to pin V power supply is needed for analog power input (AVDD) to pin 19. For OTP programming, 6.5V is required at pin 30 (OTP_ VPP) during programming.. NF1011 Product Brief: TM131-PB Page 2 of 10 Rev: 3.1 Date: 12/07/17

3 Power-On Procedure Description 1. After the 3.3V power supply is stable, the NF1011 will load the I2C ID information from the one time programmable memory (OTP). A. If a valid I2C ID reads back, the NF1011 s I2C ID will be this new one. B. If a valid I2C ID read is not read back, the NF1011 s I2C ID will default to 0x The NF1011 will search the latest valid bank of OTP contents. When done, the latest valid bank will be stored in register 0x12, Latest Burned OTP Position. 3. When no valid bank is found (value of 0x12 is 0), go to Step When valid bank found (value of 0x12 is between 1 and 31), go to Step NF1011 will load the 16-byte contents from the latest valid bank, and store to register 0x00 ~ 0x NF1011 will check the CRC of the 16-byte, and store the result to register 0x11, CRC Result. CRC is success when the result is NF1011 will set register 0x19, Locking Mode, to 1 in order to put charge pump (CP) in locking mode. 8. NF1011 is ready to be accessed by user (I2C bus). One Time Programmable (OTP) Memory The NF1011 s registers can be set using an external memory source and accessing the NF1011 through the I2C pins. The NF1011 also has a bank of One Time Programmable (OTP) memory that can be programmed via software using the PTP_ VPP pin (pin 30). Although the memory type is one time programmable, the size of the internal memory allows for the NF1011 to essentially be programmed up to 30 times before all of the memory space is consumed. Each time it is programmed, the next incremental available memory space is used up. There are two methods to program the one time programmable memory (OTP). The first option is use an auto-burn command. The second option is to access the OTP directly. OTP Programming Method 1: By Auto-Burn/Check Command Auto Burn Command Description Writes the contents of OTP to registers and kick-off command. The NF1011 will do the OTP burning automatically. Procedures 1. Pin PTP_VPP should be 6.5V. 2. Set register 0x13/0x14/0x15, VCXO to 10K Divider. With the order of low byte first. 3. Check register 0x12, Latest Burned OTP Position. When the read value is less than 31, there is space to burn OTP. Otherwise, the OTP is full and can t be burned. 4. Set 0x00 ~ 0x10 registers for the new CP s parameters. 5. Set 1 to register 0x16, Burn/Check Command. To kickoff auto-burn command. 6. Check register 0x17, Burn/Check Status. The read value will be 0 when OTP auto-burn is complete. 7. Check register Latest Burned OTP Position, the value will be increased by Done and please disable 6.5V for pin OTP_VPP. Auto Check Command Description After an auto-burn command, the NF1011 can check the correctness by an auto-check command. Procedures 1. Set register 0x13/0x14/0x15, VCXO to 10K Divider. With the order of low byte first. 2. Set 0 to register 0x16, Burn/Check Command. To kickoff auto-check command. 3. Check register 0x17, Burn/Check Status. The read value will be 0 when OTP auto-check is done. 4. Check register 0x18, Check Status A. Bit[0] 0: The read back OTP contents are not the same as registers. 1: The read back OTP contents are the same as registers. B. Bit[1] 0: The read back CRC is not correct. 1: The read back CRC is correct. Method 2: OTP Read/Write Directly Write Procedures 1. Pin OTP_VPP be 6.5V 2. Read 0x17, Burn/Check Status. OTP is ready to access when this value is Set 0x13/0x14/0x15, VCXO to 10K Divider 4. Set 0x20 OTP PTM, to 2 b00 5. Set 0x21 OTP PROG, to 1 6. Set 0x22 OTP BANK, between 0 and 31. (Make sure it s an empty bank) 7. Write data to register OTP DATA, between 0x30 to 0x3F. These bytes are the 16-byte respectively of the specific OTP bank. 8. When all bytes complete. 9. Set 0x21 OTP PROG, to Done and please disable 6.5V for pin OTP_VPP. Read Procedures 1. Read 0x17, Burn/Check Status. OTP is ready to access when this value is Set 0x13/0x14/0x15, VCXO to 10K Divider 3. Set 0x20, OTP_PTM, to 2 b00 4. Set 0x21 OTP PROG, to 0 5. Set 0x22 OTP BANK, between 0 and Read registers OTP DATA, between 0x30 to 0x3F. These bytes are the 16-byte respectively of the specific OTP bank. 7. Done NF1011 Product Brief: TM131-PB Page 3 of 10 Rev: 3.1 Date: 12/07/17

4 OTP Format 1. There are 32 banks in total, from bank 0 to bank Bank 31 is used to store I2C ID, specially. 3. Bank 0 ~ 30 are used to store the Charge Pump s parameters. 4. A valid bank is the bank which has 0x55, 0xAA header bytes. 5. The latest valid bank is the highest bank (between bank 30 and bank 0) which has the valid header bytes. 6. To store the charge pump s parameters into OTP, use lower bank first. (From bank 0 to bank 30). BANK ADDR DESCRIPTION 31 Bank 31 is used for storing I2C ID 0x00 If this byte is 0x55, the next byte will be a valid parameter 0x01 I2C_ID[6:0] x02~0x0f Reserved 0 ~ 30 Bank 0 ~ 30 are used for storing CP parameters 0x00 0x55 (valid Header) 0x01 0xAA (Valid Header) 0x02 NF1011 Revision Number[7:0] 0x03 Reference to PFD Divider[7:0] 0x04 Reference to PFD divider[15:8] 0x05 VCXO to PFD Divider[7:0] 0x06 VCXO to PFD divider[15:8] 0x07 Reserved 0x08 Reserved 0x09 Pole0 R[7:0] 0x0A {Pole0 R range, Pole0 R[8]} 0x0B {Pole2 R[3:0], Pole1 C[2:0]} 0x0C Pump Current[7:0] 0x0D {Pump Current [9:8], Buffer Current[0], Buffer Gain[1:0]} 0x0E CRC16 check sum[7:0] 0x0F CRC16 check sum[15:8] NF1011 Product Brief: TM131-PB Page 4 of 10 Rev: 3.1 Date: 12/07/17

5 NF1011 Register Table ADDR NAME TYPE BITS DEFAULT DESCRIPTION 0x00 Revision RW 7 ~ 0 From OTP User defined Revision number 0x01 Reference to RW 15 ~ 0 From OTP Valid values are from 0 ~ x02 PFD Divider Value If 0: There is no divided out clock 0x03 VCXO to PFD RW 15 ~ 0 From OTP These registers are the divider value for single-end VCXO clock. 0x04 Divider Value Valid value from 0 ~ If 0: There is no divided out clock 0x05 Reserved 0x06 Reserved 0x08 Pole0 R Range RW 0 ~ 0 From OTP Select Pole0 R Range. 0: 10k ~ 77.5k 1: 80k ~ 5110k 0x09 Pole0 R RW 8 ~ 0 From OTP Resistance Value of Pole 0 0x0A If (Pole0 R range == 0) Pole0 R[0]: 0/1: 0.4K/2.5K Pole0 R[1]: 0/1: 0.4K/5K Pole0 R[2]: 0/1: 0.4K/10K Pole0 R[3]: 0/1: 0.4K/20K Pole0 R[4]: 0/1: 0.4K/40K Pole0 R[8:5]: Don't Care Else Pole0 R[0] : 0/1: 1K/10K Pole0 R[1] : 0/1: 1K/20K Pole0 R[2] : 0/1: 1K/40K Pole0 R[3] : 0/1: 1K/80K Pole0 R[4] : 0/1: 1K/160K Pole0 R[5] : 0/1: 1K/320K Pole0 R[6] : 0/1: 1K/640K Pole0 R[7] : 0/1: 1K/1280K Pole0 R[8] : 0/1: 1K/2560K 0x0B Pole1 C RW 2 ~ 0 From OTP Capacitor Value of Pole 1 ` Equal to (Value[2:0] + 1) * 187.5pF ` Min: 187.5pF ` Max: 1500pF 0x0C Pole2 R RW 3 ~ 0 From OTP Resistor Value of Pole 2 ` Equal to (160k/Value[3:0]) Ohm (Value should not be 0) ` Min: 10.67K ` Max: 160K 0x0D Pump Current RW 9 ~ 0 From OTP Value of Pump Current 0x0E Equal to Value[9:0] * uA Min: 0 Max: 320uA 0x0F Buffer Gain RW 1 ~ 0 From OTP Multiplication of the Buffer for VCXO 0: X 2 1: X 2.5 2,3: X 3 0x10 Buffer Current RW 0 ~ 0 From OTP The output driving current of Buffer for VCXO 0: 1mA 1: 1.5mA 0x11 CRC Result RO 0 ~ 0 Derived After NF1011 power on, this register is the CRC checking result from OTP of OTP contents loading 0: Fail 1: Success 0x12 Latest Burned RO 4 ~ 0 Derived After NF1011 Power -On or AUTO-BURN command, the latest OTP Position from OTP OTP position is showed here. 0: There is no valid OTP bank 1 ~ 31: Latest burned OTP bank (Bank 0 ~ Bank 30) 0x13 VCXO to 10 KHz RW 16 ~ The divided value for VCXO clock to 10K clock frequency. 0x14 divider value 0x15 NF1011 Product Brief: TM131-PB Page 5 of 10 Rev: 3.1 Date: 12/07/17

6 NF1011 Register Table continued ADDR NAME TYPE BITS DEFAULT DESCRIPTION 0x16 Burn/Check RW 0 ~ 0 0 Write 1 to this register will initiate a process to burn the current Command registers to next empty OTP bank. Write 0 to this register will initiate a process to read back the contents from the latest OTP bank and compare them with cu rent registers. 0x17 Burn/Check RO 0 ~ 0 0 0: OTP is not busy Status 1: OTP is Busy,. When auto-burn/check OTP command initiated, this value will keep 1 until the process is complete. 0x18 Check Status RO 1 ~ 0 0 Bit[0] indicates whether the OTP contents read back by autocheck command (from the latest OTP position) are the same as the current registers. 0: NO 1: YES Bit[1] indicates the CRC check result of the read back contents by auto-check command. 0: FAIL 1: PASS 0x19 Locking Mode RW 0 ~ 0 1 0: Free-run Mode 1: Locking Mode After power on the value is 0, and the value will change to 1 when OTP loading complete. 0x20 OTP PTM RW 1~0 0 To control OTP PTM[1:0] 00: Normal Read/Write mode 10: Margin-1 Read mode 11: Margin-2 Read mode 0x21 OTP PROG RW 0~0 0 To control OTP PROG pin. 0x22 OTP BANK RW 4:0 0 OTP banks, from bank 0 to bank 31 0x30~ OTP DATA RW 7:0 0 Read/Write these bytes correspond to the 16 bytes of the OTP 0x3F bank, indicated by 0x22 (OTP BANK) 0x40~ I2C ID R 7:0 0 These registers are load from OTP. 0x41 If Data[0x40]==0x55, Data[0x41]=I2C ID 0x50 DEBUG RW 1~0 2 b10 Bit[0]: Reserved Bit[1]: DBG_OEN, Set 0 to enable debug mode When DBG_OEN==1 Pin LOS and LOCK are status signals. When DBG_OEN==0 (Debug Mode) Pin LOS and LOCK are signals from VCO s output VCO_OUT/CLK_F_OUT PLL Circuit Description Architecture: PD+CP+FILTER+ISO PD (phase detector): PFD Dividers: Two integer dividers, one on the reference clock and one on the feedback VCXO clock before feeding into the phase detector. CP (charge pump): current programmable. Filter: The filter after the charge pump, 3+-order LPF Filter (pole 0): R (internal, programmable) + C (external, connect to pin PUMP_C +/-) Filter (pole 1): C (internal, programmable) Filter (pole 2s): x4 internal R and x4 internal C cascaded as a distributed R/C. R (internal, programmable, all with same resistance you could program), C (internal, fixed, each one is 80pF). Impedance Isolator: a voltage buffer after the filter, the gain and current limitation are both programmable. This impedance isolator buffer drives into two internal resistors (in serial). Each of them has 1k ohm resistance. The end of the 1st resistor of the two post-buffer resistors has been tapped to pin 22. The end of the 2nd resistor of the two post-buffer resistors has been connected to pin 21. NF1011 Product Brief: TM131-PB Page 6 of 10 Rev: 3.1 Date: 12/07/17

7 Control Interfaces The NF1011 is controlled through serial port I2C on pins SCL and SDA. I2C Format 1. NF1011 default ID is 0x12, or loading from an OTP valid ID. 2. ID is 7-bit, ADR is 8-bit, and DATA is 8-bit. 3. Transmit order is MSB first including ID[6:0], ADR[7:0], DATA[7:0]. 4. Both read and write support single byte and multiple bytes access. 5. For multiple bytes mode, the accessed data is starting from the current address ADR[7:0]. 6. Abbreviation A: Acknowledge Ā: No acknowledge S: Start P: Stop R: Read W: Write Sr: Repeated Start Write Format Single Byte S ID[6:0] W A ADR[7:0] A WDATA[7:0] A P Multiple Bytes S ID[6:0] W A ADR[7:0] A WDATA1[7:0] A WDATA2[7:0] A P Read Format 1 Single Byte S ID[6:0] W A ADR[7:0] A Sr ID[6:0] R A RDATA[7:0] Ā P Multiple Bytes S ID[6:0] W A ADR[7:0] A Sr ID{6:0} R A RDATA1[7:0]A RDATA2[7:0] Ā P Read Format 2 Single Byte S ID[6:0] W A ADR[7:0] A P S ID[6:0] R A RDATA1[7:0] Ā P Multiple Bytes S ID[6:0] W A ADR[7:0] A P S ID[6:0] R A RDATA1[7:0] A RDATA2[7:0] Ā P PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the lead frame chip scale package (CP-32L) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the lead frame chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated into the thermal pad at a 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm and the via barrel should be plated with 1 oz copper to plug the via. The user should connect the printed circuit board thermal pad to AGND. NF1011 Product Brief: TM131-PB Page 7 of 10 Rev: 3.1 Date: 12/07/17

8 Figure 4: NF1011 Pin Diagram (Top View) Pin Description 1 Digital ground 3 SDA I2C SDA 4 SCL I2C SCL 5 Lock indication 6 Loss of signal (LOS) indication 7 LVCMOS reference input 17 VCXO buffer through IC 18 VCXO input 19 Analog +3.3v power supply 20 Analog ground 21 connect to VCXO voltage control pin (optional connecting to cap) 22 optional connecting to cap 23 Connect to C0 cap positive side 24 Connect to C0 cap negative side V OTP power supply when burning OTP 31 Internal digital 1.8v, should connect 1uF by pass cap 32 Digital +3.3V power supply *All undefined pins should be left floating NF1011 Product Brief: TM131-PB Page 8 of 10 Rev: 3.1 Date: 12/07/17

9 NF1011 Package Dimensions Notes: 1. All Dimensions are in Millimeters 2. Die thickness allowable is 0.305mm Maximum.012" Maximum 3. Dimensions & Tolerances conform to ASME Y14.5M, The Pin #1 identifier must be placed ont he top surface of the package body. 5. Exact shape and size of the feature is optional. 6. Package warpage MAX 0.08mm 7. Applied for exposed pad and terminals. Exclude embedding part of exposed pad from measuring. 8. Applied only to terminals. Millimeters Inches SYMBOL MIN NOM MAX MIN NOM MAX A A A A REF REF b D 4.00 BSC BSC D E 4.00 BSC BSC E L e 0.40 BSC BSC TOLERANCES OF FORM AND POSITION aaa bbb ccc NF1011 Product Brief: TM131-PB Page 9 of 10 Rev: 3.1 Date: 12/07/17

10 2111 Comprehensive Drive Aurora, Illinois Phone: Fax: