USING MICROPROCESSORS FOR TELEPHONE TUAFFIC MONITORING

Transcription

1 A FEASIBILITY STUD OF USING MICROPROCESSORS FOR TELEPHONE TUAFFIC MONITORING by PI:IZOUZ R.. PIENNIA Thesis submitted for the Degree of Master of Philosophy in the Faculty of Engineering of the University of London Department of Electrical Engineering Imperial College of Science and Technology. London ; September 1 97R

2 AB ST.RACT 0 In order to provide information upon which system planning can be based and future growth forecasting can be Wade, measurement of telephone traffic is necessary. This traffic is primarily composed of calls originated by subscribers and is, at present, periodically measured by electromechanical traffic recorders situated at the exchange. The recent introduction of exchanges employing sophisticated common control has extended the need for more detailed measurements. Studies are also needed on the manner of how subscribers use the services, and to ascertain the influence that the systems responses have upon the caller 9 s behaviour. Call Detail Analysis (CDA) has been successfully carried out, using. electronic data loggers and minicomputers, although on a small scale due to the relatively high cost of measuring equipment. Recent advances in microprocessor technology have brought a low cost and flexible CDA into the realms of possibility. The work reported in this thesis is an investigation into the problems and the feasibility of applying microprocessors to tele traffic data collection. During the course of the project an Intel 8080 microprocessor system was built and support software developed. To investigate the problems in teletraffic recording two of the most commonly used types of telephone exchange were studied. However, due to the legal restrictions on the tapping of telephone lines the College internal exchange was used as the model test exchange. A telephone monitoring programme was developed, using machine language (Octal format), which can scan up to 96 telephone lines and collect information from a group of active lines.

3 3. The programme and the interface circuit ; sere tested for an actual line and the effect of a group of lines was simulated in order to test the operation of the program applied to multiple lines. A main frame computer program was then written to process the collected data obtained from the microprocessor analyser, so providing comprehensive printout of information on each call.

4 To my Father and Mother

5 CONTENTS 5. P Chapter 1: Introduction Microprocessor Architecture Microprocessor Technology Telephone Traffic Types of Traffic The Importance of Traffic Recorders 16 Chapter 2: The Design of a. Microprocessor 'Introduction The Choice of the Microprocessor Intel 8080 Microprocessor CPU Signals and their Use Ina - rrupt Structure of the Hardware Design Interface to the Operator 30 (1) The front panel as seen by the operator 31 (ii) The front panel as seen by the microprocessor The SPU Support Units The Memory Units Interface to the External World Software Design The-Main Features of the Operating Program Conclusion 41 Chapter 3: Telephone System Overview Introduction Subscriber s Telephone Instrument Pay on Answer Coin Box Telephones Common British Post Office Exchanges Strowger System TXhl Crossbar System Siemens No. 17 Exchange Line Finder Circuit 59 3,4.2 First Selector 60 (i) One ]igit Selection 61 ii) Two Digit Selection 61 (iii) Final Selector Conclusion 66

6 Chapter 4: Chapter 5: Telephone Traffic Measurement 6. Page 4.1 Introduction Measurement of Traffic Flow Time consistent Busy Hour Traffic 81 recording 4.3 Measurement of Grade of Service 82 (i) Overflow meters 82 (ii) Late Choice Call Meters (LOCM) and Late 83 Choice Traffic Unit Meters (LCUM) (iii Group Occupancy Time Meters 83 (iv) Call Counting Meters Types of Conventional Traffic Recorders Trunk Traffic Analysis Equipment Traffic Measurement by Computer 87 (i) Operation 87 (ii) Analysis of Traffic Records 88 (iii) Cost Effectiveness of the System Call Information Logging Equipment (CILE) Technical Description Analysis of Recorded Data Usefulness of the Equipment Traffic.Engineering by Simulation Methods Microprocessor controlled Telephone Traffic 95 Recorders A Portable Electronic Traffic Recorder A Call Detail Analyser Conclusions 98 The Design of an Interface Circuit 5.1 Introduction Basic Requirements Effect of Line Conditions on,dial Pulsing The Effect of a Resistive Load across 105 the Lines The effect of a Series RC Load across 106 the Line 5.4 Effect-of Contact Bounce Line Characteristics dūring a Call Setup Description of the Designed Interface Performance of the Circuit Multiplexing Arrangements The Overall Interfacing Arrangement 117

7 Chapter 6: A Program for Teletraffic Data Collection Page 6.1 Introduction The Program Structure Definition of Events Method of Data Acquisition The Scan Rate Time Information Work Scheduling Definition of Terms Data Storage Structure Tables Details of the Teletraffic Monitoring Program On Line Data Analysis 139 (i) Pre dialling states 141 (ii) Data validity check 142 (iii)- A method of merging data and time 142 information (iv) Break pulses on the line 143 (v) A called line 144 (vi) Tone on the line 144 (vii) Answer 148 (viii) Clear Search for non registered Active Lines Particulars of the Program An Example of the Operation of the Program Off Line Translation of Call Details Experimental Results An Estimation of the Run Time of the Teletraffic 161 Monitoring Program Minimum Analysis Time Typical Analysis Time Overall Program Execution Time Chapter 7: Conclusion and Suggestions for Further Work 7.1 Conclusions Suggestions for Further Work 185' A Permanent Storage Medium Further Work on the Results 188

8 Page Appendix 1: Flow Charts for Microprocessor Operating 189 Program 8. Appendix 2: Flow Charts for Modified MCS-80 Kit 197 Monitoring Program Appendix 3: Strowger and TXKl Exchanges A3.1 Strowger System 213 A3.2 Crossbar System 218 Appendix 4: Supervisory Tones 232 Appendix 5: Flow Charts of Teletraffic Monitoring Program 236 Appendix 6: Details of the Main Frame Computer Program 266 for further Processing of the Final Results Appendix 7: Digidek P.70 Cassette 'Tape Recorder 273 References 275

9 AClNOWLEDGEMt NTS 9. The work presented in this thesis was carried out under the supervision of Dr. G.J. Hawkins of the Electrical Engineering Department, Imperial College. I am grateful to Dr. Hawkins for his conscientious supervision, encouragement and advice during the course of this work. I would like to thank him also for the care and concern he always shows for the general well being of his students. I wish I could express my gratitude for the support and encouragement I have received from my parents throughout my studies, The help and technical assistance offered and provided by the members of staff and my colleagues in the Communication Laboratories of the Department is very much appreciated. Finally, my thanks are due to Mrs Shelagh Murdock who typed the text conscientiously and accurately.

10 CFT/U.PTIR INt?OMJCTTON The number of transistors which can be made on a given area of silicon has undergone a rapid increase in the last fifteen years. Integrated circuit technology now makes it possible to pack hundreds of logic elements onto a small silicon wafer. Large Scale Integration (LSI), as it is called, can compete with those based upon the logic module families, provided the production quantities are sufficient to offset the high cost of LSI chip development. In 1970 Intel Corporation started work on a standard universal programmable logic element which resulted in the intrōduction of the first commercial microprocessor Intel 4004 in 1970 (Ref. 10). Microprocessors provided the means to replace dedicated logic circuits with a sequence of software instructions known as a program. The universal nature of the microprocessors leads to huge production volumes, which is generally required for an economical LSI production line. The rapid acceptance of the microprocessors by manufacturers and designers has been brought about by their versatility and low cost, which leads to higher production reliability, improved performance with a lower production time and cost in various applications. Through LSI utilization it is now possible to embark on systems where development cost or production time would have previously made it unfeasible. One area in which the application of microprocessors is going to have an impact is telephony. The move towards a complete

11 11. software controlled telephone system has encountered various problems including the need for a cheap and flexible processing unit which can be used in order to decentralise the required control system and, hence, overcome the reliability and security problems. Active research has been going on in order to explore the potentials of microprocessors for applications in all areas of telephony including teletraffic engineering. While most of the available teletraffic recorders do not meet the expectations of Post Office teletraffic engineers, the cost of sophisticated electronic equipment has not justified their wider contemplation. The work presented in.this thesis is an attempt at developing a microcomputer system and exploring its application in ' the field of teletraffic engineering. A brief summary of the material in each chapter of the thesis is given below: The remainder of this chapter gives a brief introduction to microprocessor architecture and technology. It also introduces the nature of telephone traffic and the importance of teletraffic measurement. In Chapter 2 the development of a microcomputer based around Intel 8080 microprocessor is described. Chapter 3 briefly reviews the telephone system in the U.K. and details the operation of a Siemens No. 17 exchange which was used as the model exchange for the experimental tests. Chapter 4 is devoted to a survey of various traffic recorders and call analysers. The problems involved in traffic data collection are also discussed.

12 12. Chapter 5 is concerned with design considerations involved in tapping a telephone line for the purpose of teletraffic data collection. It then continues to describe an interface circuit developed for the purpose of the experimental work carried out on the model exchange. Some problems involved in multiplexing of telephone lines are also considered. Chapter 6 studies the test results obtained from the model exchange and describes a program which was developed to collect call details from the College exchange. It continues with the analysis of the results and, hence, the performance of the developed microprocessor controlled call detail analyser. Chapter 7 expresses the final conclusions drawn from the thesis and a few suggestions for possible further work. Each chapter is supported with diagrams or flow charts which are accumulated at the end of the chapter. The thesis also contains several appendices for further support of the material. 1.1 MICROPROCESSOR ARCHITECTURE A microprocessor is basically a miniaturised one chip LSI processing unit typically consisting of an Arithmetic and Logic Unit (ALU), a set of registers, an instruction decoder, hnd a timing and control unit (lief. 1). The internal sub components are linked together with an internal bus which is usually extended, through buffers, to the external peripherals. Fig. 1.1 shows the basic elements of a microprocessor.supported with external memory and input/output devices.

13 13. The ALU consists of a parallel adder and logic circuits for arithmetic and logic operations to be carried out under the supervision of control unit. The registers include an instruction register which stores the next instruction to be executed, also the program counter which holds the address of the next instruction. The timing and control unit maintains the proper sequence of operation throughout the system by providing synchronised signal pulses driven from a standard clock. It also responds to external signals such as an interrupt. The instruction decoder translates the machine instruction codes into micro-instructions which are executed by the processor. A sequence of instructions (a Program) is stored external to the microprocessor in the memory unit. The microprocessors often use time multiplexing methods to transfer information on their bus system at different times. This reduces the number of pins used in a package, by making a more efficient use of the available bus; however, the consequence of resource sharing is the frequent need for auxiliary hardware to capture the required information. Microprocessors can appear.on multichip implementation usually providing richer functions and more flexibility at an increased cost. The instruction decoder of these systems can be in the form of an external read only memory chip containing user-defined micro-instructions resulting in a faster execution time in specialised applications.-

14 MICROPROCESSOR TECNTOLOGY The first generation of microprocessors, typified by the Intel 4004 or 8008, used the p-channel MOS technology because of its availability (Ref. 1). The n-channel MOS technology was used in the second generation of microprocessors (e.g. Intel 8080, Motorola M6800) which were also characterised by their large instructions sets (up to 80 instructions). The new technology also improved the speed of operation. The third generation of microprocessors (e.g. Intel 3002) use sophisticated architecture and bipolar technology which achieve higher performance at the cost of higher power dissipation and lower packaging density. The gate propagation delay of many emitter-coupled logic products is lower than 1 ns compared with ns for MOS products. The best of MOS and bipolar technologies have been combined in integrated injection logic (I-L) technology used for the production of highly sophisticated microprocessors of the fourth generation (e.g. Ti. SBP 0400). This technology demonstrates speeds comparable to bipolar TTL with low power dissipation in the region of that of CMOS (Ref. 11). 1.3 TELEPHONE TRAFFIC Telephone traffic is primarily composed of the calls originated by subscribers and is defined as the aggregate of calls passing over a group of circuits or trunks.

15 15. The average nunfroer of simultaneous calls in progress during a period is known as the traffic flow, or intensity, and is measured in the unit known as the "Erlang". The unit provides information on the portion of the specified period "T" for which a circuit is occupied and the number of calls which originate during a period "t" where "t" is the average holding time of the calls occurring during the period T. Traffic flow = A = C t/t. C = No. of calls during period T Types of Traffic The actual number of calls in progress depends on the time of origin and the duration of each call. The traffic in which a call can be originated at any instant of time with an "equally likely"_. probability, is defined as the "pure chance" traffic. In practice the number of sources from which a call is originated is finite and therefore the telephone traffic, strictly speaking, cannot be called a pure chance traffic. However, the proportion of the number of calls in progress to the number of sources is very small and consequently the assumption of pure chance traffic for the telephone system is acceptable in practice. Such assumption allows probability theory to be applied to the problems of telephone traffic engineering, yielding a definition for the "grade of service" for a given group of circuits as the ratio of the traffic lost to the traffic offered (Ref. 16). If the traffic on a group of circuits does not, at any time, differ greatly from the average traffic, then it is said to be "smooth". This condition applies to high traffic levels from a small number of subscribers, or at a particular stage where the peaks.of

16 16. the traffic have been spread over a number of circuits, The smoother the traffic the fewer the number of circuits required to deal with a given volume of traffic at the same grade of service The Importance of Traffic Recorders There are about 20 million telephones in Britain making about 16,000 million calls per annum. This means that, on average, a telephone call is made every 2 ms and, in the busiest period of the day, calls are made at an average rate of one every 0.3 ms, with up to 1,500,000 conversations taking place at once (Ref. 5). About 300 million Pounds per annum are spent on trunk, junction and internal equipment provision. When the investment ofsuch large sums is being decided, small errors in equipment provision can be very costly. Although some of the assumptions used in predicting the future needs may not turn out to be perfectly true, errors must be minimised wherever possible. In the field of planning, traffic recorders are used extensively by service and planning staff to ensure that existing plant is deployed to the best advantage, and that yearly increments of plant are provided in time and in the right place. This is also of particular interest to the manufacturers of the equipment, as such equipment can rarely become available at short notice. Data about the trunk network traffic is required for planning future routes, tariffs and plant growth. Forecasting future requirements is not easy because it involves assessing growth potential, the effects of changes in tariff policy, and changes in

17 17. social structure and so on. A balance between conflicting customer expectation of good service on the one hand and cheap service on the other is continuously being sought. Under-provision of equipment causes congestion, and could lead to the complete collapse of the telephone system, over-provision of equipment leads to inefficient use of resources and requires high tariff rates, which mean that many people do not avail themselves of the facilities and can lead to even higher tariffs. Congestion at present is not a critical determinant of telephone usefulness; however, the congestion component of the quality of service influences the equipment provisioning policies. Statistics show that about 3 per cent of call failures are caused by congestion, giving a loss of about 6 million/annum in revenue, the bulk of which is in trunk calls. Zero congestion is never economical and the annual cost of removing congestion from local or trunk calls does not justify its contemplation. On the other hand, surveys of customer dissatisfaction with the service suggest that the system has more congestion than is shown by statistical surveys. Although there can be many psychological reasons for that, the issue can be settled by surveying the actual congestion experienced by the customer. With modern telephone systems which incorporate such facilities as "second attempt", other measures of quality are becoming more salient. Post-Dialling-Delay, for example, is becoming an important factor during the transition to new generations of exchanges. The response of individual users to such relatively new experiences needs to be analysed.

18 18. While the conventional traffic measurements are essential, their scope needs to be widened to cover new areas of traffic studies required for modern telephony.

19 19. 6:^a 6157 C4:D e resz, R' - Osa OW! IMO 6340 it",, arm, WM 1219 tle External Clock or 0 Control Signal MICROPROCESSOR MEMORY Fig 1.1 Microprocessor Architecture Plus External Support Circuit

20 20. CHAPTER 2 THE DESIGN OF A MICRO-CO 4PUTEEZ 2.1 INTRODUCTION A digital micro-computer is a machine which manipulates numerical data using a microprocessor as its Central Processing Unit (CPU), a set of memory devices, Input/Output (I/0) devices, and interface components (Ref. 1). The prefix micro- to the words computer and processor should be interpreted in terms of size and cost and not capabilities. The microcomputer is called upon to process three tykes of information - data, status and control. The nature of the data strongly influences the microcomputers optimum word length. The status information describes the states of the peripherals and other input/ output devices and can be transferred in either decoded or encoded form (Ref. 12). Control information flows in the opposite direction to status words, from the microcomputer to the peripherals and other I/O devices. Every microcomputer instruction to I/O devices includes selection, or routing, of information in the form of an address. The form of presentation of the information depends upon the type of the CPU and has a marked effect on the design and the overall efficiency of the system. To design a commercial microcomputer system several points such as cost, size, reliability, flexibility, compatability with the. other existing systems, the life cycle of the system (before obsolescence), and the development time (hardware and

21 21. software) should be carefully considered. The overall design is a balance between the customerls requirements and the feasibility of meeting these requirements. This chapter describes the steps involved in the development of a non-commercial general purpose microcomputer system for university studies and applications. The particular environment in which the microcomputer was to be used, mainly the university, relaxed some of the design considerations. For example, the requirements for the number of power supplies and power dissipation were not stringent and also certain familiarity of the potential users with a typical computer hardware and software could be taken for, granted. On the other hand, costly support hardware and software to reduce design and development time were not readily available and the time factor was often influenced by the cost factor. 9 9 THE CHOICE OF THE MICROPROCESSOR The choice of the microprocessor is often the most crucial step in the microprocessor system design procedure. The available microprocessors should be surveyed and their capabilities should be weighed against the system requirements. Although the choice of a particular category of the processors is a relatively straightforward decision based on the basic requirements, the selection of a particular microprocessor is often influenced by the previous experience as well as other considerations (Ref. 13). A simple program or routine (Benchmark Program) can be used to compare the performance of different processors in execution time and memory requirements. But the benchmark program should not be

22 22. taken as the absolute proof as a user cannot predict the most executable codes and whether he will be able to use the instruction set efficiently. Hardware benchmarks can also be of considerable use. The number of I/O ports, the interrupt structure and other special functions (such as Direct Memory Access) should receive careful attention. The availability of the family parts and their computability with other existing logic circuits (such as TTL) is also important. One other important item to be considered before the hardware selection is the software support available to the microprocessor. Among these are assemblers or cross-assemblers or simulators (see footnote) which can considerably reduce the software development time and effort. The manufacturers have, unfortunately, been relatively slow in backing their products with widespread software support. The development of the college microcomputer did not benefit from the present (May 1978) available hardware and software kits on offer by most leading manufacturers. The choice to be made for the microcomputer design was narrowed down to the two then most popular microprocessors, i.e. Motorola M6800 and Intel The latter was considered to have some slight execution speed advantages (Ref. 14) over its very competitive rival. The 8080 was selected so that the previous experience gained from the already available Intel 8008 could be The assembler is a program that converts the mnemonics into binary codes ready for execution. The cross-assembler is an assembler program run on another machine. The simulator is a program which runs on a host machine program to simulate the action of the target microprocessor.

23 23. called upon. The existing 8008 was considered already out of date and slow in operation. The complexity involved in using its timemultiplexed 8-bit bus for data and address transfers and its relatively few input/output ports and its limited stack depth, as well as other design shortcomings (Refs. 1, 2) wade 8008 highly inferior to its successor, INTEL 8080 MICROPROCESSOR The Intel 8080 is an 8-bit n-channel MOS single-chip microprocessor organised around an internal 8-bit data bus. Advances in packaging technology following the introduction of the first microprocessors resulted in a 40-pin package as the standard for second generation microprocessors (including the 8080). The large number of pins offered the possibility of using separate unidirectional address and bi-directional data busses. However, the economy associated with time-multiplexing (as in 8008 address presentation) forced the retention of some aspects of this feature in other generations of microprocessors. Since no data flow can occur until the target address had been set up, the data bus is available for the flow of other information (such as status information) prior to the presentation of the data (Ref. 2). Fig. 2.1 shows the basic blc-2k design of the architecture of the Data transfer between the internal registers and, the memory (RAM) needs 16 bits of address, 2 bits of op-code and 3 bits for internal register address. The overall 21 bits of information would have occupied three bytes of instruction storage, requiring three memory fetch cycles. This was avoided by using two of the six

24 24. accessible internal registers as memory address holders. Therefore a single instruction can repeatedly refer to a location in the memory whose address had been pre-loaded into the H-L register pair (Register-Indirect addressing mode). The fastest way of changing the pre-loaded address would then be by incrementing the content of H-L implying the need for sequential storage of the required data. This has been one of the weak points of 8008 and 8080 microprocessors (Ref. 2). The Arithmetic Logic Unit allows logical and arithmetic transformation of data. A one-byte instruction is not enough to specify the source register, the operation, and the destination register. Since these operations are common, a two byte instruction would have been costly in terms of memory. Therefore, the generality of the instruction was sacrificed to allow a one byte instruction to operate only on one register and accumulate the result in the same register called the "Accumulator". Condition flags, or status flip-flops, are generally set as a result of an operation performed on the content of the accumulator. These flags can be tested by the following instructions to alter the program flow using "transfer of control" instructions (e.g. JUMP or CALL instructions). The processor should be able to record where the transfer occurred so that a return to the main instruction sequence may be effected. If the return address was stored in the RAM, the return instruction would require at least two address bytes as well as the op-code information. To avoid this sequential order mechanism in space, the equivalent sequential order in time (known as the order

25 25. of occurence) is used in a Last-Tn-First Out stack mechanism (Refs. 2, 3). The number of stored addresses is, then, meaningless until the stack capacity is exceeded and only the order of occurence has meaning. The use of a 16-bit stack pointer in the CPU, to refer to a user-appointed stack region in the RAM, ensures a virtually unlimited stack capacity. The flow of the program into the processor can also be altered using an external interrupt signal. An interrupt instruction can be jammed into the CPU only during the times when the CPU is requesting the first byte of a new instruction. Therefore, the last instruction is always finished before any action is taken to service an interrupt request CPU Signals and their use The processor does its job by executing a series of instructions forming a program. An instruction cycle is defined as the time required to fetch and execute an instruction (Ref. 3). Every instruction cycle consists of up to five machine cycles which, in turn, includes between three to five states (T1 to T5). In order to synchronize the operation of the CPU, a master clock provides two-phase non-overlapping clock pulses, known as 01 and 02. A complete cycle of the 01 clock is known as a state of a machine cycle. The mechanism by which the CPU knows how many states are needed for each instruction is the feedback shift register, where

26 26. the output of each stage is a function of the previous stage and other following stages. The 8-bit status information appears on the data bus at the beginning of each machine cycle where status strobe (SYNC) signal is given to enable the external latching of the system select bits. The internally decoded bits divide the total system into five subsystems (input, output, interrupt, memory, and stack) and can be used to prepare the appropriate subsystem to receive or transmit the data during the subsequent states (Fig. 2.2). Following the address presentation to the system, the 8080 generates a timing signal, Data Bus IN (DBIN), that tells the selected subsystem to gate the data onto the data bus. Fig. 2.3 shows a simplified timing waveform during the first machine cycle of an input instruction cycle (Ref. 3). A logical combination of the DBIN signal and the appropriate status bit (or bits) provides a READ signal for the memory, I/O, and interrupt; subsystems. A similar combination of status word with the Write Control signal (WR) from the CPU can result in "WRITE" timing signal for the memory and input/output units. Each source of the data must, therefore, have two enable lines, one for the timing pulse and another for the subsystem select line. Subsystem selection can also be performed. by Memory Mapped techniques, where one or more of the address bits are used to select a particular subsystem. This avoids the use of input or output instructions, and hence improves the execution efficiency, but at the Expense of a reduced memory capacity.

27 27. Apart from the normal states in a machine cycle, a "WAIT" state can be forced upon the CPU, following the To state, if the READY signal indicates the need for the prolongation of the processing cycle. During the "WAIT" state both the address and the data on the output lines remain stable and the processing cycle will not proceed Lentil the READY line again goes high. It should be noted that this is different from the HOLD state during which the processor relinquishes the control of the address and data busses to allow for uses such as the Direct Memory Access (DMA). The functions carried out during a machine cycle is therefore as follows (Ref. 3): State T1: Address is placed on the address bus and status word is put on the data bus. State T2: READY and HOLD inputs are sampled and the halt instruction is checked. The Program Counter is incremented if it was used during the T1 state. State T: The processor enter=s wait state if it is required either due to RPY signal or a HALT instruction. State T3: DBIN or t i3' timing signals are issued for data flow to/from. the CPU. States T 4 and T5: Internal Processing is carried out ifneeded.

28 Interrupt Structure of the 8080 In order to enable the microcomputers to communicate with the I/O devices, typical systems use pulled I/O, interrupts, direct memory access, or any combination of these techniques. When the interrupt technique is used, the I/O device attracts the microcomputer's attention by activating a control line (INTERRUPT). In the polled I/O sequence, the microcomputer initiates the transfer of information in synchronisation with the program. A high priority I/O, then, cannot override a lower priority port. In the interrupt system the I/O port, has the initiative and priority interrupt can be used at all times whenever "nesting" is permitted Ref. 12). The interrupt system can be of the "polled" or "vector" type. The former transfers the Program Counter to a common location where a routine polls status bits of the I/O devices which could have been arranged in a priority chain formation. The "vector" interrupt, however, transfers the PC to one of the several possible locations (eight in the case of 8080) where a specific routine associated to that particular interrupt can be executed. This is a more efficient means of using the interrupt facility where a large number of devices is likely to request the CPU's attention. The 8080 uses a "vector" type of interrupt request which is re-clocked by the internal logic of the CPU so.that the last state of the progressing instruction cycle can be completed. This logic disables the interrupt system, sets the interrupt acknowledge bit (INTA) in the status word while resetting the Memory Read bit, and inhibits the store of the incremented PC so that the address of the next selected, but not accessed, instruction can be stacked.

29 29. The interrupt cycle is otherwise indistinguishable from an ordinary FETCH cycle that brings in the next instruction. It is the responsibility of the system designer to use the INTA bit and DBIN signal. (during the state T3) to generate a signal which removes the interrupt request and disables MEMORY READ signal so that the user9 s own interrupt instruction (generally a special one-byte CALL instruction) can be "jammed" on the data bus (Refs. 3, 2). The content of the PC is then automatically saved in the stack region of the RAM (see footnote) and can be used for a return to the interrupted program. The priority encoding of the interrupt levels must be performed externally to the CPU and is discussed later. HARDWARE DESIGN The choice of the microprocessor sets the basic requirements of the hardware. Among these requirements are the specified maximum loading of the CPU lines so that the timing constraints can be met, thus ensuring the correct data transfer in and out of the CPU. To avoid any compatibility problem between the external TTL chips and the n-mos CPU, and ensure adequate design margins, the manufacturers suggestions on the layout and the useable family parts were observed wherever applicable. This saved design and testing time by reducing the possible sources of error. This region can be separated from the memory region by using the stack subsystem select bit which appears during.the Ti state of every stack operation.

30 Interface to the Operator An interface had to be developed to enable man-machine communication. The foremost consideration was the type of the language to be used. The choice (see Section 2.5) was between different formats of machine language programming, mainly binary,- Octal or hexa-decimal. The Octal format was selected as it avoided the cumbersome and time-wasting handling of the binary language while preserving the basic coding format of instructions (two bits of op-code, three bits of destination register, and three bits of source register). Therefore eight push-button keys (0 to 7) and a data/address select key are provided to enable Octal inputting of the instructions, Each key entry is translated into a 3-bit binary code, by hardware logic which is shifted into a predefined RAM location whose address and content can be displayed on the front panel, again in Octal format (six Octal digits for higher and lower address bytes with a further three Octal digits showing the data content of the memory). A latch mechanism for a continuous display is used for simplicity of the design. This has the disadvantage ofincreasing the power consumption and the current requirements of the system (Maximum of 2 Amps on +5 volt supply). In order to facilitate program debugging and the control of the microcomputer, eight functions are provided - to include: RUN : STOP : Runs the program from a predefined location. Stops the program and enables the front panel.

31 31. :EXM.FORW. Allows forward examination of the memory locations and their control. EKM.BACK Allows backward stepping through the memory locations and their content.. Read Internal :Displays the content of the internal registers and. the Registers (RIR) flags. Load Address Is used as an extra bit of information to allow the of Single Step (LAD.SSTP) selection between the user-defined and the software- defined address for single step executions. S.STP Is used to execute one instruction at a time (Single Step). CONTINUE Runs the program from where it was last stopped. A CLEAR key is also included to clear the display and reset address input counter (to be discussed later). (i) The f ront panel as seen the operator Fig. 2.4 shows the logic circuit designed to interface the front panel keys with the microprocessor using two three-state buffers (one for the keyboard and the other for the control keys). Three NAND gates (IA, 1B, 2A) are used to translate each Octal digit into three binary bits representing 3 bits of data or address according to the position of data/address select key. A high to low pulse transition at Al or A2 input of the mono-stable (Chip no. 3 ) initiates a strobe pulse to the three-state 8212 buffer (Chip no. 10) which latches the keyboard information and issues an

32 32. interrupt request to the processor. The mono-stable time constant is set to allow for contact bounces to settle before the information is latched into the buffer. A similar arrangement is used for the control keys where a second buffer (chip no. 11) is strobed by an independent mono-stable (chip no. 4). A flip-flop (chip no. 6) is used to disable the keyboard mono-stable (chip no. 3) and block the path to Al input of chip no. 4 whenever one of the main control keys (RUN, CONTINUE and S.STP) is activated. Therefore the other panel keys are unable to interrupt. a running program unless the STOP key was first used in a willing attempt to terminate the program and enable the path of the strobe pulses to the buffers. The strobe pulses are also suppressed, for a period determined by R2 and C2 of a third mono-stable (chip no. 8), in an attempt to eliminate the effect of contact bounce during the release period of a key (the contact bounce from the CLEAR key is considered unimportant). (ii) The front panel as seen by the microprocessor The outputs of the input buffers (Fig. 2.4) are coupled to the data bus of the microprocessor (Fig. 2.5). The use of three state buffers in the input mode allows for the maximum decoupling of the input device from the bus when the device is not used. The interrupt request signal, issued by the input buffer, enters the priority interrupt control unit (Intel 8214) and its level of priority is compared with any other simultaneous interrupt request

33 33. as well as a software controlled interrupt threshold (which can be disabled if so desired). On receipt of a valid interrupt request, the priority interrupt control unit repeats the request by issuing an active low pulse of the same width as the 2 clock pulse. This pulse is used to latch a RESTART instruction into another buffer which will then proceed to force the CPU into an interrupt cycle and put its single byte CALL instruction on the data bus after the acknowledgement of the interrupt request (Ref. 3). In order to input the latched data, the processor enables the input buffers, under the control of software instructions which presents the correct port address and a READ timing signal (see footnote). A special output instruction is used to re-enable the priority interrupt control unit for further interrupts. To output the content of the data bus, the output buffers (chip nos. 12, 13 and 14) are clocked by a WRITE timing signal and an address select signal (coming from the 8205 one out of eight decoder). The latched data is fed to a series of 7-segment LED displays via their appropriate drivers (Ti ) The CPU support units The requirements for high-level clock drivers, synchronising flip-flops, various timing signals. and bi-directional data bus drivers led to the development of special purpose support chips for the Correct timing signals for I/O READ or WRITE were derived from the status word and WR and DBL signals. The moans to drive these signals is discussed later in this chapter.

34 34. The Intel 8224 clock driver provides a 12 V swing clock pulse and a synchronising latch for the READY and RESET lines. A status strobe for strobing the status latch is also available. The Intel 8228 bus controller provides bi-directional buffering for the 8080 data bus meeting the voltage and current loading requirements of the CPU. It also contains a latch for capturing the status bits at the beginning of each cycle. These bits are then combined with the DBIN, WR and IIOLDA signals from the CPU to provide Memory Read (MEMR), Memory Write (1w7), Input/output Read and Write (TUT, TN), and Interrupt Acknowledge (INTA) signals (Ref. 3). The overall arrangement of the CPU support chips is shown in Fig To improve the fan out capability of the address bus lines, bus drivers were introduced with three-state output capability so that DMA can take place if required at a later stage The Memory Units The microcomputer has the theoretical capacity for up to 64 k bytes of memory. For the basic system two kilo bytes of RAM and one kilo byte of EPROM (Erasable Programmable Read Only Memory) chips were considered. Static RAMs were preferred to the more economical dynamic RAMs since the static MOS memory chips did not require any critical timing circuits to refresh their content. Eight Intel 8102 A-4 chips are used to provide 1 k bytes of memory of 450 access time (Ref. 3). The on-chip address decoders are fed from ten address

35 35. lines (AO to A9) while the chip enable inputs are connected to one of the outputs of an Intel 8205 decoder (Fig. 2.7). The delay from the address set up to chip enable signal is therefore about 18 nsec 'the 8205 output delay). The write cycle specification of the memory requires stable address lines for a minimum of 450 ns with the RAM chip being enabled at least 300 ns before the data is written into the memory (data is stored in the RAM during low to high transition of the R/W signal, as shown in Fig. 2.8). The R/W pulse applied to the chips is derived from the MEMR signal which has the pulse width of WR signal from the CPU (equal to one clock cycle). The 8080 specification ensures a stable address, at least 730 ns prior to the WR signal, with the clock cycle of 500 ns. The data is also guaranteed to be stable at least 200 ns prior to and 140 ns after the WR signal. With the chip enable lagging the stable address by 18 ns, all the timing requirements of the RAM memory for the write cycle are met without any need for external hardware. The compatibility of the memory chips with the timing waveforms of the 8080 during the READ cycle was also satisfactorily che:eked. The EPROM memory chip Intel 8708) also has a maximum. access time of 450 ns and requires a chip select signal to be present 120 ns (worst case) prior to data output. As the byte select occurs during the FETCH period of the instruction cycle the time allowed for. the outputting of memory data is from the address set up Lime (maximum of 200 ns after the first 0 9 pulse in state T1) to the data input time during the T~ state. There is therefore more than 450 ns available to the EPROM in order to output its data.

36 Tnterfface to the external world In addition to the front panel extra interface units are contributed to the microcomputer card racks to allow its operation with the teletype and CRT. Work is also in progress to link a cassette tape unit to the system. 2.5 SOFTWARE DESIGN The software of a computer provides the means for the explicit control of the computer operation through a step-by-step sequence of instructions that form a program. Each microprocessor has been provided with an "instruction set" in the form of a list of binary machine codes of 8-bits long for 8-bit microprocessors. The tedious task of writing a program in this low level language, and the consequent high rate of errors resulting therefrom, asked for a more efficient representation of the instruction set. The assembly language is a basic language in which there is normally a one to one ratio between the statements in the language and machine code instructions (Ref. 4). Host computers can be used as cross-assemblers to eliminate the need, and its associated cost e.g. in memory requirement), for an independent assembler running on a microprocessor system. To facilitate programming and debugging, high-level languages have been developed. These are instructions which more nearly approximate ordinary English where each instruction corresponds to many machine language statements. High-level

37 37. languages are effectively waebine-independent and allow for major changes in the system hardware (including the change of the microprocessor used) to have a minimal effect on the software. But generally high-level languages produce a more inefficient program, in terms of the occupied memory space and the execution time, than assembly languages. It has been estimated that (Ref. 20) the code produced by a high-level language occupies about 1.6 times as much memory and takes 3.5 times as long to execute as an equivalent assembly code program. The ratios should be considered as an approximate indication of the merits of assembly code since much depends on the efficiency of the compiler which translates the highlevel statements into machine codes. It should also be argued that program development and debugging in assembly code takes about three times as long as high-level language programs (a very strong point in favour of the use of high-level languages). The question of the language to be used for the development of microprocessor software has been a.difficult one to answer. The hardware cost of producing microcomputers dropped rapidly during the first few years of microprocessor availability, increasing the gap between the hardware and software support systems available to the users. The problems in obtaining developed software packages and software support systems and the unavailability of a direct physical link between the microcomputer and its potential cross-assembler (a computer) forced the choice of machine language to be used for software development. To avoid dealing with the binary representation of the instructions while preserving the structure of the instruction

38 38. codes (for easier recall of the instruction codes by the user) it was decided to have a simple hardware translator to translate Octal digits into three binary bits. A series of these bits was then manipulated by suitable programs to produce and store the appropriate instructions in the appropriate locations The Main Features of the Operating Program One kilo bytes of program instructions were stored in EPROM to provide software means for program manipulation through the front panel keys of the microcomputer. Basic sections of the operating program are detailed in the flowcharts of Appendix (1). The overall program uses ten RAM locations as the working space for temporary storage of updated information. These locations are explained below: Four' locations (called X through X+3) are used to store up to four instructions which are generated by the operating program in the ROM. By altering the content of these locations and transfer of the Program Counter to location X, the operating program can change its next executable instruction(s) to suit a particular requirement. To facilitate program debugging i.e. correcting program errors) means had to be provided whereby the operator could check the content of each of the six registers and the flag flip-flops. This is achieved through the Read Internal Register (RTR) program which is initiated by its corresponding front-panel key. A threebit counter (G) is set in the RAM, during the processor RESET period, to be incremented during the execution of the RIR program, hence pointing to a different register each time.

39 39. A pair of locations (referred to as Memory Pair Y, or MPy) is also included in the RAM to store the addresses of particular importance e.g. the address of the next instruction to be executed if single step key was pressed by the user). The representation of a byte in the form of three Octal digits (i.e. 377 as the highest possible number) did not introduce any problem as the nineth bit was effectively unimportant and was therefore automatically shifted out of data. However, this method could not be used in a six Octal digit representation of a 16-bit address, since it was desired to represent the address by two bytes of high and low addresses in Octal format. Therefore the processor had to be provided with the information indicating the intended byte (this problem would not exist if hexa-decimal format was used). In order to avoid using a separate key for the byte selection, the address input program was arranged to interpret the alternating 8 bits (represented by three Octal digits) as higher and lower bytes. A counter (F) was provided for this purpose which could be reset by the CLEAR key enabling uninterrupted loading of the address starting with the most significant two bits of the higher byte. The two remaining working spaces (called Z and Z+1) are used as temporary storage of the registers whenever their stacking is not desired. The initiation of the RESET routine enables the interrupt line, sets the stack pointer, and outputs an arbitrary code on the panel display to inform the user that the machine is ready to receive instructions. The starting address can then be defined (using the Address/Data Select key and the 0-7 keyboard) before data

40 40. is input. The input address is loaded directly into Ii and L registers which can be incremented or decremented for consecutive data input or examination. To terminate a running program the "STOP" routine is initiated which displays the content of the PC at the time of stopping the program. A continuation of the program can then be initiated immediately after the stoppage or following the examination of the internal registers (using R7Rt key). The "STOP" routine can also be called in the program to enable single step execution (S.STP key) of the whole or part of the remaining instructions before the CONTINUE key is used to carry on the program execution. In order to allow the processor to choose between the single step execution of the instruction shown by the PC or the instruction selected by the user (through the setting of II and L registers), an extra routine (LAD.S.STP) has to be initiated by the user prior to the input of the starting address for single step execution. Some basic programs have also been included in the E1'ROM to allow for the use of paper tape for program loading or unloading a 66iye. The capabilities of the system have been enhanced by the addition of a 1 k byte PROM which contains the modified version of a standard software monitor program to be used via a teletype. The original version of the program was developed by Intel Corporation for use in MCS-80 KIT system. This program, however, used hexadecimal numbers and had to be modified to enable the use of Octal numbers in one- or two-byte representation of input/output data. Details of the facilities provided by the modified program and the appropriate flowcharts can be found in Appendix (2).

41 2.6 CONCLUSIONS The individual hardware and software functions were defined before the development stage of the microcomputer system. This was essential since a trade off between the hardware and software, although possible, is not always practicable in a developed system. The design took notice of the possible future expansion of the system in memory size, and increased I/O and interrupt units. The processor bus lines were extended to several card racks to facilitate the addition. of extra modules. The introduction of various hardware support chips (such as timers, controllers, etc.) made the hardware design of some microcomputer boards a fairly standard work using manufacturer 2 s recommendations. This is one of the reasons which has encouraged some companies to produce ready made microcomputer modules eliminating the need for the design of virtually identical items from scratch Ref. 21). The choice of hardware components was, however, not optimum but based on the desire for the simplicity of the design and computability of the IC chips. As a result of this the hardware debugging was facilitated but the power consumption and the chip count of the final system were increased. Useful all pirpose monitoring subroutines were included in the main operating program which provided useful program debugging means. The initial software development, however, was considerably prolonged due to the inadequacy of software support systems. Errors were found long after the program was considered fully debugged. One particular weak point of the monitoring routines has been the

42 ti 2. inability to modify the content of the registers during their examinations. The selected programming language Octal representation of the machine codes) did not introduce unforeseen problems. It is, however, felt that hexa-decimal representation of the codes would have made the system more compatible with the increasing software packages now on offer. The choice of'the microprocessor was based on the factors present at the time of the design. By the time that the machine was ready for operation, its CPU was already superseded by more efficient processors of the same family. The Zilog Z-80, for example, sounded a better proposition. The, life cycle of the microprocessors is in fact one of the problems that many microprocessor users have had to face. This is expected to improve as the advances in the hardware technology approaches a saturation point.

43 Bi -directional data but Data ous buffer latch r Accumulator (8), _ Accumulator latch (8) (8 bit) internal data but Temp. reg. (81 Flag flip flops Instruction register (8)1 Instruction decoder and machine cycle encoding (8 bit) internal data but w (81 Temp reg. S Reg. Multiplexer D (8) Reg. H (81 Reg. Stack pointer Z (El Temp. reg. C Reg. E (8) Reg. L (8) Reg. (16) Register array Program counter (16) Incrementer/decrementer (16) address latch. Power supplies V ~ +5 V r 5 V - -GND Timing and control Data bus Interrupt Hold Wait Write control control control control Sync Clocks Address buffer (16) WR DBIN INTE INT Hold Hold Wait Sync pt p= Reset ACK Ready (HLDAI At5A0 Address bus Fig. 2.1 Intel 8080 Block Diagram

44 ADDR C PU STACK I/P 0/P INT. DATA STATUS LATCH 1 Clock J Strobe Fig. 2.2 Selection of Subsystems

45 2 5 J1-STATE,.4 T ADDR. VALID DATA BUS STATUS ; WORD DATA VALID status word latch SYNC. DBIN Fig. 203 Timing Waveform of 8080 (First Machine Cycle of an Input Instruction)

46 46 3 _3k CO DTD.Da RuN 3.3K D, STB S. STP - 1K ch LAD. S.s TP chip r F_xAl At 221./ P 1 4' Fig. 2.4 Front Panel Logic Circuit

47 Control Pannel I Control Keys Digit Switches /777 1g +c Rzt2 L E2 1 VT t It 7.I 2 0 ' 1 1 HUJ1 I 1 i R! s b +5Y +5'l Fig 2.5 Front Pannel I/0. Circuit 3 4 G7 4 e ,6 w d R s +5'1' rgr e t~ c IcK 4 5V

48 r A7 CPU!T3 D ~r ca i v N 4 5 Co 3; - C7 4c CO 37 :3E 3j 36 ICF I ~s! 5 0. I 3 '5, r ' N 7 CO 23 [N-,? :. cr MCN/1.t h'c Li s X /. i?,7 77Z /77 4 Ictr n il//7 Fig 206 CPU and its Support Chips

49 ,- r=i cz) CO C f-r, A15 IL. 1 ' I' -. -t- v t TY -...,... 4, -" -t t r. - V. ' ' ; -.. i _ '..t, 4, i - 4 ' , ". t t ITI I it I 8102-A4 ò I EFRO RAM 1 X 1024 RAM RAM RAM RAM RAM RAM RAM cv.,; VI IL I t3 I0 6 3 C=I I ' BUFFER lj BUFFER Mai-DECODER ( 824J 5 a ii I 1.51t A 4 Fig. 2.7 Memory Unit

50 50. write cycle time 450 ns. Min. ADDR. CE to write time CHIP ENABLE 300 ns. Min. 300 ns. Min. 2Ons min, DATA IN 300 ns. Min. data stable data input into RAM 0 ns. Min. y data can change Fig. 2.8 Timing Waveform of memory Write

51 'CHAFFER TELEPHONE SYSTEM O VIT IEQ^T 3.1 INTRODUCTION The public telephone system consists essentially of a large number of single telephones unevenly distributed throughout the country, each being connected to a switching centre termed a telephone exchange (Ref. 17). The process of a call setup, for a local call, is best illustrated by Fig. 3.1, as is explained in Ref. 5. The caller initiates the call and signals the required number to the exchange which then sets up a path to the called number and informs the caller of the progress in each stage of the call. The path is broken when either side clears. There are four basic signalling systems in use in the U.K., depending upon the type of exchange to which the line or trunk is connected (Ref. 5). D.C. loop disconnect pulsing is used to give a series of breaks in the loop where the number of breaks, their duration, and the separation between the trains of pulses convey the necessary information. For audio links over 25 Km long, DC2 signals are used; this system completely reverses the current feed to signal digit pulses. The other two systems are in-band a.c. 'system AC9, which uses single tone frequency, and signalling system AC11 which employs multi-frequency tones for dialled digits and single tone signals for the transmission of other information.

52 52. This chapter lo--.ks at the equipment used in setting up a telephone call and discusses one particular exchange (Siemens No. 17 system) in more detail. 3.2 SUBSCRIBER TELEPHONE INSTRUMENTS The elementary circuit of connection between two Central Battery (CB) telephones is shown in Fig The coil and the battery are situated at the telephone exchange, and while the coil is particular to the connecting circuit the battery is shared by all the circuits on the exchange. As the coil has a high impedance to audio frequency signals, the greater portion of the speech current, generated at one end will flow through the receiver of the other end. The subscriber's set in an automatic telephone area should have provision for dialling, ringing,as well as a more sophisticated transmitterreceiver circuit. Fig. 3.3 shows.the circuit of a typical subscriber instrument known as Telephone 332 which was largely in use up to 1955 Ref. 8). The figure shows the 0.1 /IF capacitor across the transmitter to by-pass.radio-frequency currents. The dial off-normal springs are arranged to short circuit the transmitter and receiver circuits to prevent acoustic shocks in the receiver while dialling continues. The bell tinkling with dial pulses is also similarly suppressed. The 2,LLF capacitor provides a spark quench circuit in series with the 30 Qresistance. In 1955 the B.P.O. introduced a new telephone, the 700 type, with a superior performance in transmission and the suppression of side tones generated in the instrument. A simplified circuit of telephone 71 6, without a regulator for line resistance compensation, is given in Fig. 3.4.

53 53 The ringing signal ci-rcui-t is formed by the 1000 ohm magneto bell connected in series with the 1.8 1,1F capacitor (Ref. 7). The loop calling signal is completed by the micro-switch contacts and is formed by the contact GS2, the 23 Q winding of the induction coil, the transmitter and dial pulse springs. The two diodes suppress any surge voltage when contact D1 closes as dialling starts. The increased sensitivity of the 700 type telephone allows it to be used on longer lines than the earlier types. It is, however, so sensitive on short lines that without modification the loud reception would cause discomfort to the customer. This point made it necessary to provide all telephones with a regulator which reduced the sensitivity by an amount governed by the value of the line current. For D.C. current the regulator has the effect of an additional current dependent resistance, in series with the transmitter, and typically of about 36 ohms for a line current of 76 ma or 10 ohms for 30 ma. Other types of telephones exist, such as "Trimphone", "Kcyphone", and modified 700 type phones suitable for shared service working. The D.C. signalling path of these telephones is basically the same as the general 700 type; however, their ringing circuitry may differ slightly Pay-On-Answer Coin-Box Telephones The basic difference between an ordinary telephone and a coin-box telephone is that the latter is required to provide two signals. The first signal consists of the normal dial pulses and the second is a signal from the coin-box to the exchange to indicate.

54 54. the value of coins inserted. In addition to the above two, a further signal is sent from the exchange to the coin box to unlock the coin slots. The circuit of the coin-box is, therefore, more complex, as can be seen in Fig. 3.5, where the regulator has been omitted for the purpose of simplification Ref. 22). The relay SU is made sensitive to the line voltage reversal which occurs when the called subscriber answers the call. The operation of 'SU opens the coin slot while the exchange equipment disconnects the speech path and returns pay tone to both sides of the call, allowing 12 seconds for coin insertion. The fully inserted coin is then checked before the Mask Contact opens in preparation for coin pulse signalling. These signals consist of the reduction in line current, at the rate of 4 pulses per second and are caused by the insertion of the 5 kq resistance in the line loop. CP-ON contacts guard the caller from acoustic shocks during the coin pulsing and prevent any interference with these pulses by other components of the circuit. The Coin and Fee Checking C.F.C.) equipment in the exchange detects the signals generated by insertion of coins, and compares, throughout the duration of the call, the total number of coin pulses received with the total number of meter pulses proper to the call at that time. Coin-box lines terminate to a transformer-type transmission bridge in the exchange. This bridge permits the use of a high speed signalling relay and facilitates the sending of tones to either or both sides of the connection, with or without continuity of the transmission path. This is illustrated in Fig. 3.6 by the contact TN which can isolate one side of the connection from the other when

55 55 required. It is apparent that the D.C. condition on a coin-box line during the call setup is different from the conditions which could exist for an ordinary line. A coin-box line is A.C. coupled to the exchange selectors, whereas an ordinary telephone line finds its way directly into the selectors. Therefore it should be noted that some of the arguments that will be given in later chapters will not be directly applicable to the coin-box lines. 3.3 TYPES OF COMMON BRITISII POST OFFICE EXCIIANGES Most of the about 6200 local exchanges of the B.P.O. are of the non-director type (see footnote) Strowger exchanges. The rest are of the director type Strowger, cross-bar systems, or reed relay (TXE2) exchanges (Ref. 19). The next level in the exchange hierarchy consists of about 370 primary trunk exchanges.(group Switching Centres) of mainly Strowger and about 40 cross-bar TXK1 exchanges. All 27 secondary trunk exchanges as well as 9 tertiary trunk exchanges are of cross-bar type, known as TXK42 s. In 1976 the public service of a large reed-relay exchange, called the TXE4 exchange, commenced (Ref. 23). This exchange can act as a combined group switching centre and local exchange for up to 40,000 lines and forms one of the bases of the modernisation plan for the British telephone system. Detailed description of the exchanges is out of the scope of this thesis. Therefore only two commonly used B.P.O. exchanges are A director exchange translates a standard exchange code to the actual code required for a particular route. In a non-director exchange the actual exchange code has to be dialled as there is no register-translator facility.

56 56. mentioned in order to compare their operation with that of Siemens No. 17 exchanges, which will be discussed in detail later in this chapter Strowger System The Strowger system is one of the more straightforward systems to understand, and illustrates most of the essential principles of automatic switching systems in general. About 36 per cent of all local director exchanges, 46 per cent of local nondirector exchanges operate on Strowger principles. In the Strowger step-by-step system of automatic switching the required line is selected by a process of decimal selection. Dialling signals in the calling subscriberls line actuate a relay circuit in the selector which in turn controls the movement of the vipers (Ref. 9). Fig. 3.7 shows the main parts of the system in the form of a block diagram and Appendix (3) goes into more detail describing the operation of each block. A calling subscriber signals his line circuit to seize a first selector which would then return dial tone to the caller. If the attempt fails, due to the unavailability of. first selectors;" equipment engaged tone is returned. The pulses generated by dial then extend the calling line through the group selector switches to the final selector, which has access to the line circuit of the called party. The final selector then informs the called subscriber of the incoming call, and the

57 57..link between the two subscribers becomes complete when the call is answered. On the other hand, busy tone may be returned to the caller if the called line is engaged. The distributive control of the step-by-step exchanges, although simple, is undesirable since the switching equipment is busied throughout the progress of a call which may take a considerable time while the caller decides on the next digit to be dialled. Further, as busy tone is returned to the caller through the final selector, the intermediate equipment is only released when the caller clears the call TXK1 Crossbar System The crossbar systems, like Strowger, are space division systems as different lines are physically separated. The main advantage of crossbar systems is the use of common control in the call setup progress. Other advantages are the faster operating speed of the crossbar switches, their size, and their precious metal contacts which eliminate microphonic noise often present in Strowger contacts. A greater reliability also arises, in crossbar systems, from relay operation replacing mechanisms. Fig. 3.8 shows the basic operation of the TXK1 crossbar exchange, which is discussed in more detail in Appendix (3). Lifting of handset operates relays in the subscriber's line circuit which signals the corresponding line marker to hold the selected path through Distributor Switches (DS) into the Line Transmission Relay Group (LTRG). The seized register then stored the dialled number and when adequate information on the called

58 58. subscriber is stored; the controller finds the line marker associated with the DS in which the called line is located. Meanwhile the path between the caller and the register is held through LTRG and hence the first line marker is free to serve any other line (Ref. 15). The LTRG returns all the required signals to both parties. If the called line is free, the DS in the called end of the line "hunts" for a free path, through Router Switches (RS), into the appropriate LTRG and the register and the controller are then freed. The speech path is completed when the called end answers the call. Therefore, the essential part of the equipment (i.e. line markers, 44.40k4olita, and controllers) are busied for a fraction of a second and the equipment is used efficiently. 3.'4 SIEMENS NO. 17 EXCHANGE The Siemens No. 17 system was taken as the model exchange for the experiments and tests needed to be carried out. The choice was obligatory due to the legalities attached to tapping a public telephone line. The, exchange is being used in the internal telephone network of Imperial College and therefore is not covered by legislation concerning the B.P.O. The Siemens No. 17 system was originally designed in 1933 and modified some years later (Ref. 9). The system is essentially a marker-controlled uniselector scheme with common control circuits. The selectors are positioned stage-by-stage under the control of the calling subscriber's dial. The distinguishing feature of the S.17 system is the use of a mechanism of large capacity and with an

59 59... exceptionally high speed of search, This allows the adoption of a: straightforward stage-by-stage selection scheme without the need for complicated devices to keep the time of search within the minimum pause period between digits (normally regarded as 400 ms). The system has been designed to operate at the standard voltage of 50 V, with the usual limits (46-52 V). The tones provided in the College exchange were similar to standard Post Office tones (Appendix 4), with the exception of the Equipment Engaged Tone which was no different from the "Busy" tone. The main arrangement of the system is shown in Fig Line Finder Circuit The line finder No. 17 is a 200 outlet high speed Motor- Uniselector. The Motor-Uniselector, unlike normal uni-selectors, cannot be stepped directly from dial impulses. It operates when the start relay associated with its latch magnet is energized and it stops and mechanically locks itself when its wipers get to the marked outlet. These wipers move on banks of contacts at a rate of 200 contacts per second. The 200 lines connected to a line finder are divided into four banks, each of which is associated with a separate Start Relay. The operation of the line finder circuit is preceded by the operation of. LIQ, relay in the subscriber line circuit (Fig. 3.10) after the initiation of a call (Ref. 24). This engages the final selector multiple (through P-wire) and marks the line finder multiple. The Allotter, started by the start relay, searches for a free line finder together with a free first selector associated with it. The

60 6o. allotted line finder. than "hints" for the calling line in the bank and is stopped by the battery potential through the 550 Q shunt across the K-relay in Fig. 3.10, which then operates, releasing the LR relay. The operation of K-relay initiates the release of the associated control circuit while extending the first selector to the calling line. Meanwhile, earth is connected to a traffic meter (if fitted) to register the call. If a call is originated while all line finders are engaged, the Allotter is halted and the start circuit is closed down until a line finder becomes available or a time pulse arrives, force-releasing the Allotter. It should be noted that under this condition no Equipment Engaged tone is returned to the caller and he just queues for a free line finder. Fig simplifies the closed loop d.c. condition of the line after the initiation of the call and before the caller is extended to a first selector First Selector The first selector in this system combines the operation of an ordinary-type first and second selector. Six first selectors are served by a single control circuit which is coupled to any of the selectors, via relay contacts, for the period of time required for completion of the selector operation. The selector gives access to 250 outlets, divided into five banks. One bank is available for first digit selection, two for second digit and the remaining banks for first and/or second digit selection. Access to each bank is given by prepositioning the wipers after the receipt of the relevant first or second digit (Ref. 25).

61 61. Subject to selector and control being free, the allotter of the associated line finder tests in via the selector P-wire connection to the battery. Relay A Fig. 3.12) then operates to the incoming loop causing relays B and C to operate while holding earth is returned on the P-wire. The caller receives dial tone which remains on the line until either C or relay PA operates. There can be two modes of operation for the first selector (Ref. 25): (i) One digit selection: Relay A responds to the dialling impulses stepping the wipers of DA switch accordingly. Relay C holds during the impulses only to be released after the end of each digit. Therefore dial tone is not removed until the'end of the first dialled digit is reached. Then other wipers of. the DA switch start a search for a free outlet in the group marked by the dialled digit. (ii) Two digit selection: In this mode, the search for a free outlet at the end of the first dialled digit is inhibited due to special wiring arrangement between DA and DB switches which operate relay PA, transferring the control to DB switch. The wipers of this switch step round to mark a group of outlets at the end of the second digit when a search to locate a free outlet in that group begins. A successful marking of a free outlet stops the wipers and hence terminates the search. H-relay then operates to extend the line further to the group selector. Fig simplifies the D.C. condition of the line when Dial, Busy or. Number Unobtainable tones are superimposed on it.. The latter two tones can be connected Lo the line at any time after

62 the receipt of the :first digit but not betty eh the final two digits, as will be seen later. The appropriate circuit to be discussed, at this point, is the group selector. However, as its control circuit operation is very similar to the first selector and its D.C. line condition is no different from the final selector, only the latter circuit is examined here. (iii) Final Selector: The final selector includes the transmission bridge and gives access to 200 lines which may consist of individual or P.B.X. lines if required. Normally, one control circuit serves six such selectors and the circuit is arranged to control the application of ringing current to the called; ringing tone, busy tone and N.U. tone to the caller. The circuit is also capable of force-releasing the called party within 30 seconds after the caller had cleared. The called is then treated as a new caller and dial tone is returned. The 200 lines are divided into four banks of 50 lines, called W, X, Y and Z as shown in simplified diagram of Fig The hundreds digit dialled by the caller decides on two of the four banks, one of which will, eventually, be selected by appropriately pre-positioned wipers. This use of single-ended wipers to provide two groups each of 100 is one of the features of the No. 17 system and is used o concentrate of traffic into a smaller number of individual. groups. The principle is known as "pairing" and its objective is achieved by. arranging the selector involved to receive a momentary discriminatory signal for even or odd hundreds

63 63. selection. This arrangement should not be confused with the Post Office standard pairing system. The latter uses two separate groups of 100-line penultimate selectors to access a 200-line final selector, while here only one group is employed (Ref. 9). The pairing arrangement as well as the control and line circuit condition for the final stage of a call is shown in Fig The operation of relay P is conditional upon the battery potential on the "+" line. P operates for odd hundreds digit changing the condition of WS switch (Fig. 3.14). Selection of the particular line required in either 100 is determined by the tens and units digits dialled. The impulse trains, being recorded by DA and DB switches, select one of the 50 marking connections. There are four sets of markers, each capable of marking 50 lines, each pair being associated with odd or even hundreds digit. DA1 selects one of the two groups of digits while under control of tens digits. DA2 points to two digits out of ten possible ones before the units digit move DB switches to select one out of ten possible choices. Marking of the required line is then completed. The control relays (not shown) then operate to close a path for the selector magnet latch which steps the selector wipers forward until the marked line (called line) is reached. The 550Q battery potential on the P-wire of the non-busy called line operates the T-relay which in turn stops the wipers by cutting the latch magnet path. This relay does not operate if the P-wire of the called line is earthed, indicating a busy line.. Initially the. line loop resistance consists of the 400Q winding resistance of the P-relay and the 55 Q resistance of the coil,

64 64. the line resistance itself, and the two 200 Q resistances of the A-relay in series with the 35 Q resistance. However, this momentary situation, shown in Fig. 3.16, changes when.bb-relay operates within a fraction of a second afw. the A--relay is seized. The 400Q winding of P-relay is thus short circuited, but the relay can hold if it has been operated by the pairing signal. The new D.C. condition of the line (Fig. 3.17) persists while the A-relay receives the dialling impulse train and transfers them to DA and DB wipers. No tone can be connected to the caller line until the outcome of called line marking becomes clear. For caller-not-engaged condition, relay G (not shown transfers the line from the control circuit A-relay to the selector A-relay where ringing tone is returned to caller. On the other occasions where the called party is busy or number is unobtainable, relays LC and PA operate appropriately to return N.U. or Busy tones from the control to the caller. It should be mentioned that under any of the above conditions, the tone is returned on a balanced line with total resistance as shown in Fig Concurrent with the ringing tone to the caller, ringing current is supplied to the free called line which closes its D.C. loop on answer. This operates the F and D relays which, with J relay, previously operated, completesthe speech path via the transmission bridge. The control circuit is then released, leaving the called circuit under the control of the D-relay while the A-relay holds the calling line.,fibres 3.19 and 3.20 show the D.C. condition on the final stages of the call. setup. The marking earth potential of the P wire.

65 65. operates the K-relay in the called subscriber's line circuit and K relay contacts remove the line potential. Ringing current is then supplied to the called line and the polarity of the line is reversed. It is worth noting that the called line potential, rather than the caller line potential, reverses its polarity when a call is answered. (The opposite of this condition happens under the P.O. Strowger exchanges.) Therefore the D.C. condition of the caller line remains unaffected from the time ringing tone is supplied up to the end of the call. Finally, to complete the description of the exchange operation the "Right-of :Way" function has to be mentioned. An executive calling an engaged line can obtain "Right-of-Way" by a brief operation of the special push button on his telephone instrument upon receipt of Busy Tone. This results in the completion of a connection to the engaged line, but to allow his presence to be known to the other parties, Warn Tone is connected to the lines at low level. The exclusive access to the called extension can then be arranged when both parties of the existing connection clear; upon so doing, the wanted extension is rung and the connection is completed as for a norma]. call. The executive signal to the control circuit is by putting an earth on the negative line, whereby relay RSA Fig. 3.15) operates via the 200 resistance of the control A-relay. A series of relays then operate to form a three-way speech path. As this feature of the system has a rare use, it was not explored any further, neither was any attempt made to make provision to study its occurrence in the exchange.

66 CONCLUSION The overall telephone system consists of subscriber sets, links to the exchange, interface between the subscriber and the exchange, and the switching network of the exchange with the appropriate control arrangement. The need to interwork with the other public telephone systems has kept, in general, the principles of signalling and the basic design of the elements in the subscriberls loop unchanged. The crossbar exchange took advantage of the fast operating speed of crossbar switches and introduced an efficient register control. system. The Siemens No. 17 system has a switching mechanism similar to the Strowger type of exchange while it uses the common control feature of more contemporary crossbar systems. Despite their different control concepts, the Strowger and the Siemens No. 17 exchanges make use of similar elements in their subscribers? line loops. in Table 3.1. The operation of College internal exchange is summarized

67 TABLE 3.1 POSSIBLE rrnal\jsrrions PHON ONE STATE filo ANO'nTF.B DUlinrG A CALL SE'r UP Dra,m for College 'phone, lith some possible events in case of normal Public Exchange <l> ~ ~ bd r-! H ~ 0 N 0 E-i 'r-l Ul CH~ -i-j tt: \I: +'r-! <l> 0 ~ r-! ~r-! r-! rn r-! +> Q)' Q)O CH.;tl ro ro cor-! r-cl ro ~: r-l ~o CH 'M +> 'M 'r-i~ <l> <l> 0..:::1' 0 A U)A A I ~A Z':.fJ. E-i '-" Ul <l> rf} H CI) "-... Ul ~. ~ H ro CI) ~... ',--l 0 OA % -*-1 Off Hook ~ J V Dial Tone ~ J *2 start Dialling -1<-3 ~ J I I I Dial Pulses ~ V End of Dial Pulses *4- *5 Next Selector ~ *2 I ~ J J Tone (1100 Hz). ~ Answer - J *'6 ~- Clear Down J. (On Hook) *''7 *" 1 Equipment engaged tone for no available uniselector. 2 Possible to get NU tone if dialling does not follow after certain time(not in the college exchange) 3 If dial is not fully rotated to produce any dial pulse, dial tone is returned. 4 Can be after the first digit or after the second digit. I ~ 5 Busy,EQ.ENG.,Ringing,or NU tones are possible. 6!msltler: is followed by pay-tone in case of t Pay-on-Answer 'phones. 7 Off-Hook condition can imply that Ringing current is to follo\'l. V I I / I ~

68 68. Start of cat Ca11- u0 Proc 3-to-5end First 5~ di it Third digit fou~ d,,d to set'd, First do digit Third di if Fourth diyr lcrmirtim-free start of ring ng tq11e) Called' Call -answered (cessation r of rirx).ng tone) Ca ll-answe red Alort- tonnirtal Cat- answered _~-- Call ended Calling terminal Local exchange Local exchange Called terminal Fig. 3.1 Signal Diagram for a Call Between Two Exchanges (1 ef:5)

69 69. Fig..2 Basic Principles of Central Battery Telephones Fig. 3.3 Subscriber Set Model No.332 ' Fig, 3. Subscriber Set(700 Series)

70 70.?i'F,VO su VT --'Y Sr..n:ji Cs 2. 4, Short Circuit for 999 services Fig. 3.5 Pay-on-Answer Telephone Set tl U Too Fig. 3.6 Exchange Equipment Loy Coin-Box Telephone Line

71 magags dazs-rq-dal.s ;o rm.z2t j haots STJ L Fl S 0 f 13) DS (/ I'QI *J f v ~ /T"1 K`~l ' / 0 Waa

72 ROUTER SWITCH t t LIRE MARKER DS 1 LM Fig.3.8 TX10 Crossbar Systen

73 ma;sgs L ~ oi1 suemei s Jo quaaasuu.z.iu ozsug 6 C h:: J7 rtn

74 SUBSCRIBER l'^' R I TO - LINE FINDER MULTIPLE TO N:F.TER TERM,WAL: SLOCK TO FINAL SE LECTOR MULTIPLE p TO START RELAY <3 LR 1 Fig Line Circuit of Seimens No.17 Exchange _ R L R s ON 7 7O0 -of 50 V Fig Line Condition at Off-Hook and Before 1st Selector is Seized : Total Resistance of the Subscriber Telephone Set RL : Line Resistance DoN ; Dial-Off-iiormal Contacts

75 J 4- P To Mark QaiL is DA ~B P?3 DB C2 fc 500 j Q A 11 LC, Fig, 3.12 First Selector (Seimens No.17) C. L3usiTone NU Tone plat Tone '72, Di? r. D3

76 76. 20o, 501" ZOO Fig Line Condition When Dial,Busy,and NU tones are Received. VIS sub.line or trunk Fig, 3."1k Simplified Diagram of the Four Banks of a 200 Outlet Final Selector in Seiniens No.17 System

77 F -T, 4 ticy 2 Uri A D '6c. I J. (sccze..-ryi \ow.. 114/..4. i 2 G4' F vii,,,.), f- t -., 4ne, I:- BB -1,. c...= LC P 1 P- kid 3 - (40,47,1) I.4 - Qij NU-7Zne Fig Final Selector (Seiniens No.17)

78 78. RL PkN 35 a'~ v Fig Initial Line Loop Resistance When a Group or a Final Selector is Seized o;T 3 \ ~ :1`$ 1 Fig Line Loop Resistance (Steady Condition) 35 N L v RL 250 Soy",n 1 I RL 250 Fig Balanced Line Loop Resistance t\a) Rs; Resistance of the Telephone Set RL: Line Resistance

79 :, y ~,.. OPerfft!tt til 1K "tes _ Cferated K i 2co f) RL Fig A Called Line when Receiving Ringing Current i ( I G' 25o I 250 r1 5o ~. Fig Line Cordition(d.c)When a Call is Answered

80 CHAPTER TELEPHONE TItAFFIC IEA.SUR.EMENT 4.1 INTRODUCTION It is now generally realized that an accurate knowledge of the traffic flowing in the network is vital for the proper administration and economic control of any telephone system. In this chapter, the means of recording the traffic as commonly used by the British Post Office is discussed. 4.2 MEASUREMENT OF TRAFFIC FLOW With the aid of traffic recorders, extensive traffic measurement can be made to obtain estimates of the traffic carried by each group of circuits in an exchange. The flow of the telephone traffic changes by the hour of the day. There is usually a period of at least an hour during which the fluctuations of traffic flow are minimum around a value. The traffic is then said to be in statistical equilibrium (Ref. 34), which means that the probability of finding any number of simultaneous calls is independent of the time when the system is examined, provided the time is within the equilibrium period. The period of one hour during which the statistical equilibrium exists for.the maximum traffic flow is known as the busy hour and is used as a measure of the traffic flow. The individual circuit groups may have different busy hours which do not necessarily correspond with the observed busy period for the exchange as a whole. Therefore, several busy hour measurements on different days of the week and even for different months, may be required before the

81 81. maximum traffic is recognized. In practice, information about the traffic flow is obtained either in terms of the total number of calls during the busy hour and their average duration, or of the average number of simultaneous calls in progress during the hour. This can be done by visual observation of the number of engaged switches or circuits in a group, by manual testing of each circuit in the group, or by automatic recording on the meters (Ref. 44). The procedure adopted by the B.P.O. for automatic traffic recording was, for many years, the Post-Selected Busy-Ilour Traffic Recording. Tests were normally made once every 30 seconds over one and a half hour period with the meter readings taken at half hour intervals. The busy hour was then taken as the two consecutive half hour periods during which the number of engaged conditions recorded was the greatest (Ref. 44). While this method had the advantage of encompassing the true busy hour, even if this varied from day to day, it tended to over-estimate the traffic level. It also required a large amount of meter-reading, which was undesirable (Ref. 31) Time-Consistent Busy-IIour Traffic Recording- This method superseded the Post--Selected Busy-flour Traffic Recording method, and it has been employed by the B.P.O. since 1969 (Ref. 44) Briefly, recording is normally done over a selected one hour period each day from Monday to Friday, under control of a time switch and a cycle counter. The equipment is switched on automatically at a

82 82. -predetermined time each day and recording is terminated after 20 scans of 3 minute cycles, on long holding time equipment,. or 200 scans;of 18 second cycles on short holding time equipment. The average time consistent busy hour traffic can then be obtained, at the end of the week, by subtraction of the initial and final meter readings and division by 100 or 1000 for 20 scans and 200 scans respectively. This method allows more frequent traffic records to be made from simultaneous recording of both short and long holding equipment, and avoids the labour in connecting and reconnecting the equipment )ge meters. As a result of this system,a.recording time is also substantially reduced and the elaborate processing of the meter readings is avoided. 4.3 MEASUREMENT OF GRADE OF SERVICE In automatic exchanges meters, in addition to the automatic traffic recorders, are provided in order to keep a continuous check on the grade of service given on the various groups of circuits. The main types of these meters (Refs. 44, 9) are: (i) Overflow meters: An overflow meter. is connected so that it records the number of times that calls occur when all the circuits in the group are engaged. The meter is operated when the wipers of a selector, unable to find a free outlet, pass to the 11th outlet. and reniain there until the selector is released after a maximum of 15 seconds. A second selector cannot operate the meter while it remains operated by the first selector, therefore further events remain unnoticed. However, if the total number of overflow calls is small, the resultant error can be neglected.

83 83. (ii) Late Choice Call Meters (LCC,) and Late Choice Traffic Unit Meters (LCUM): These meters. are used in conditions where the overflow traffic cannot be measured due to the continuous hunting action of the switches. The LCCM is connected usually to the last circuit and records the number of times this circuit is seized. A contact of the LCCA completes a circuit for the LCUM which records the cumulative time that the circuit is in use, by being stepped once every 30 seconds. Therefore: LCUM reading The amount of time the unit was fully occupied during 120 one hour i.e. the traffic in Erlangs) (iii) Group Occupancy Time Meters: These meters are used to record the cumulative time, usually in 1 sec. or 2 sec. intervals, during which all circuits in a group are busy. This time, when converted to hours, is numerically equal to the grade of service. (iv) Call Counting Meters: These meters are connected to certain types of equipment, such as senders, which have a fixed performance time. The meter operates once for each complete call, hence the product of the meter reading in one hour and the operation time of the equipment gives the traffic carried. 4.4 TYPES OF CONVENTIONAL TIh&i+'1"IC RECORDERS In Stroti er exchanges access to traffic recording points is via uniselectors. These points are usually the private wires, although separate traffic recording leads are provided in some cases. The busy condition is indicated by the presence of an earth and each uniselector, using 49 of its 50 outlets, can scan 147 access points with three sets of wipers.

84 84. Tn TYK1 crossbar system, access to the traffic recording leads is via the crossbar switches which cater for a maximum of 1200 leads to long-holding-time (1.h.t.) equipment and a maximum of 40 usable leads to short-holding-time (s.h.t.) equipment and 10 leads to very-short-holding-time (v.s.h.t.) equipment, such as markers and router controls. The above groups of equipment are scanned at 20 sec., 2 sec. and 200 ms intervals. A feature of the TAIK1 recorder, not previously included in traffic recorders used by the B.P.O., is the ability to measure delay in receiving dialling tone. This facility is used in some countries where exchanges are deliberately designed to handle a given quantity of traffic with a specified delay. This delay is then used to assess the need for equipment extension (Ref. 31) Trunk Traffic Analysis Equipment This equipment was developed in the mid s for the random sampling of trunk traffic in a.group Switching Centre (G.S.C.). The equipment is connected toaregister-access_relay set, as shown in Fig. 4.1, and records such information as the dialled digits and meter pulses which are punched onto a paper tape for subsequent computer processing.' A maximum of 3000register-access-relay sets can be connected to the analysis equipment which can only monitor one out of every n incoming calls. Each register-access-relay set has a count wire on which a 50 ms earth pulse is sent to a "pulse separator" unit shared by 100 other count wires. The pulse separator produces a 24s pulse to a counter which is set to operate the NN relay when a count of n is reached. The contact of the NN relay then prepares the

85 85. circuit for the operation of the next A relay which receives a 50 ms earth pulse. The operation of this A-relay initiates the hunting action of a motor uniselector to find its marked output. The signals on the P and M wires are detected by high impedance relays before being stored and switched by orthodox electromechanical circuits, into the perforator control to operate the perforator magnets. The dial pulses are stored on a uniselector until an inter-digital pause indicates that a complete digit has arrived. This digit is punched on the tape, and the uniselector homes (Ref. 30). The paper tape contains information on the date and the time of the day and details of the observed call, such as off-hook, dialled digits, answer, meter units, and on-hook events; also, the value of n when the record was made. A time character is punched on the tape every 5 minutes throughout each 24 hours. During the monitoring the call--timer suppliestime pulses so that the time, in seconds, from the beginning of the call to each event can be. pinched on the tape. The design of the equipment had to take into account some practical aspects of taking the samples. As the holding times of calls vary considerably, it is possible that during the observation of the IC.nth call, the (K+1).nth call arrives, so causing the termination of the previous observation before the completion of the call. The value of n can be chosen in order to reduce the above possibil isy. The probability of a call lasting longer than time t is e-t/z, according to negative exponential d:i.stri',~ution of random

86 86. arrivals (lief. 36), where T. is the average holding time of calls. This probability is less than 0.01 for a t/i ratio of 5. Therefore, if n was chosen so that the time taken to count from zero to n is five times the average holding time for all calls, then less than 1 per cent of the observations will be forcibly terminated. Assuming that C calls arrive per hour, then the time taken for n calls to arrive is n/c, which should be equal to 5T. It follows that the value for n should be equal to 5A, where A = CZ is the total traffic flow. The data on the paper tape is fed to an off-line computer which is programmed to calculate particulars of the sampled calls such as the average holding time, the number of calls that failed, and the meter pulse rate for the particular code dialled. The trunk traffic analysis equipment provides valuable information on the traffic 'flow in the network. Its operation is not restricted to the busy hour and, therefore, any shift in the busy period can be detected. It reduces the labour involved in processing and scrutinizing the records and collects useful details on the particulars of the calls. However, it is expensive in hardware and Slow in operation. Its cost-effectiveness could be greatly improved if more than one call at a time could be monitored, employing a scanning process. Even then, the prospect-of a large number of traffic recorders producing an unmanageable quantity of paper tapes could limit the utilization of the equipment. The inclusion of a processor to give a traffic recorder that provided its own analysis printout was considered unfeasible at the time the Trunk Traffic Analyser Equipment was introduced.

87 Traffic Measurement by Computer In 1969 the B.P.O. decided to investigate the possibility of the control of traffic recorders. over a data link by a dedicated computer with one computer controlling all the recorders in an area (Ref. 35). This was made necessary by the high cost of manually recording and calculating telephone traffic. The most promising system was considered to be the one which aims for a minimum of equipment to be located at each exchange and for a suitable group of exchanges to be connected by data links to a centralised computer which would control the local equipment and receive and process the traffic, data. All traffic recorders working on a scanning principle consist basically of two parts: the control section and the access equipment. Much of the cost of a traffic recorder is in access equipment, therefore the access uniselectors of the Strowger traffic recorders are retained and used, after being slightly modified, to interface the control system with the subscriber's P wire (Ref. 32). (i) Operation: Fig. 4.2 shows the general configuration of the computer and a traffic recorder. The access uniselectors are grouped into blocks of three, with the capacity of 441 access points. Each block is identified by a 9 bit code which is wired to the home contacts of the nine uniselectors forming one of the thirty possible blocks. The operation of each traffic recorder in each exchange is independently controlled by the computer. Start up is initiated for

88 88. a particular traffic recorder 30 minutes before commencement of the busy hour when the wipers of the uniselectors are automatically set to home-positions. At the commencement of the busy hour a block identifier code, received from the computer, is decoded in order to select the required block. The scanner-sender reads simultaneously the conditions on the nine access leads into its store and assembles a character consisting of the nine bit conditions on the wipers and a parity bit. This character is then sent at a rate of 200 bits/sec. to the computer which expects the first and the last characters to be the block identifier code. The complete scan cycle is repeated 20 times during a recording hour. Any access block can be scanned with a periodicity ranging from 3 minutes to 6 seconds by repetition of its code within the block list in the computer.. At the end zif the recording time, information on faulty lines is transmitted by the computer to the exchange maintenance staff who then send confirmation of the fault to the computer so that false results CQK be deducted from the data. (ii) Analysis of traffic records: The computer has in its store several programs to meet the needs of traffic recording and analysis. Data received from the traffic recorders are stored on the compnter2 s disc and magnetic tape storage to produce a single :lays record, a weeks record, or a 4 week7 s record of the measured traffic. Some of the features (Ref. 35) of the analysis program are:

89 89... (a) Inspection of the records of all access points and a comparison with the access point look-up file to check that no access circuit has been engaged all the week and that no unallocated point has carried traffic. (b) The measured traffic is compared with the critical traffic for each circuit group and overload indication is.given when appropriate. (c) Special records are kept in the master file for later reference. (d) The traffic of all groups entering and leaving particular switching stages are summed and percentage differences in the lost or gained traffic are given for the relevant switching stage. (e) Call destination analysis is performed using the data collected by Call Failure Detection Equipment (C1DE) which continuously samples a maximum of 120 calls arriving at the first switching stage within an hour. Details of digits dialled are recorded and a tone detector records the receipt of any tone after the last digit has been sent. Only the calls which received a tone, i.e. "good" calls, are actually analysed for routing. A one hour observation for one exchange needs enough storage for 1800 words of 4 characters. (f) Printout details of the collected information are given.

90 90. (iii) Cost Effectiveness of the System: Frequent and reliable traffic records have been obtained with recourse to computer assistance which has also proved to be a valuable maintenance aid. The above system proved an attractive proposition for large exchanges or a number of exchanges situated in close proximity. However, the cost of data links for the system is a large part of the total cost and this rises sharply where exchanges are spaced further apart. Therefore, in more scattered districts some form of fast automatic recorder at each exchange with batch processing of records may be a better answer. One advantage of the system is its capability to detect tones on the telephone lines. This facility has more potential use than the detection of "good" calls only. It will be seen later that the detection of supervisory tones can be used: on the subscriber lines, to collect information about the subscriber's response time and behaviour. 4.5 CALL INFOR1\11\TION LOGGING 7 i;ipif T (CILE~ In 1976 Call Information Logging Equipment was introduced in the U.K. by independent manufacturers for telephone traffic.data analysis, particularly for different types of Private Branch Exchanges (P.B.X.'s). This equipment is mainly intended for use by commercial bodies as a means of telephone usage monitoring (Refs. 39, 40, 41). It is most applicable to big offices and companies where a considerable saving can result from optimization of privatewire and exchange line utilizations. However, its potential in traffic data collection is considerable.

91 91. CILE, as its name implies, collects inforiiation upon a number of events associated with the making and receiving of telephone calls. The gathered information is stored in digital form, typically on a magnetic tape, for a subsequent process on a computer where a comprehensive set of analysis reports can be presented to cover such aspects as: (a) Details of all calls made, giving the date, times originating extension number, the dialled nuinber,and the duration of the call. Details of incoming calls. carried in Erlangs. Exchange line utilization in terms of the traffic Details of operator response time where appropriate. Time of busy traffic within each day of the week. Technical Description A typical block diagram of the system layout is shown in Fig The lines to be monitored are routed to line input boards, each of which has a typical capacity of 16 line circuits, consisting of high input impedance resistive-capacitive circuits connected in parallel across each of the A and B legs of telephone lines (Refs. 39, 40). The voltage excursion between the A and B legs produced by on-hook and off-hook conditions of the telephone is constantly compared with the reference voltage, set for individual lines to suit variable loop resistance, and a TTL logic level output is produced (Fig. 4.4:a).

92 92. The scanner ensures tl.tat each of the 256 lines is examined once every ms (40 j sec per line). The logic level for each line at the instant of scanning is fed to a memory, which is also contained in the scanner control module. The word formed in the memory from the state of the line circuit logic over several successive scannings can be used to describe a particular event and the sequence of events enables the discrimination between outgoing, or incoming calls. Figs. 4.4b and 4.4c give some idea o-i the manner in which decisions can be made on the basis of the information obtained. Trains of dial pulses are recognized by line logic at 0 and 1. The inter-digit pause which separates two dialled digits terminates the counting for each digit dialled. Similarly, a series of rapid excursions between 0 and 1 or a positive going voltage across the line (relative to a threshold) can be detected as a ringing event. The typical 18-bit word information so collected for each event is then stored in a queue buffer, which has a typical capacity of 26 x 18 bit word storage, before being loaded into the magnetic tape control unit. The capacity of buffer is chosen so that each extension can have a call rate of 10 per hour without causing any loss of events. Other functions of the buffer include producing time marks of 1 sec. increments. The time mark consists of an 18-bit word which precedes an event word on entry into the buffer. The output of the queue buffer is reformated in the magnetic tape control unit and then-stored in a 1024 word RAM. When sufficient

93 93. words are accumulated, a +chole block 3.:; elaborated with parity and redundancy check characters and then it is written onto the magnetic tape Analysis of Recorded Data The data is fed into a suitably programmed computer (Ref. 39) which first condenses the isolated data blocks into a complete record and then produces analysis reports in pre-defined formats. Several software packages are on offer in order to extract statistical, u1an,agerial or other relevant information from the recorded data. These have been outlined in the previous sections Usefulness of the Equipment As an engineering tool, the collected information can be of great value in traffic analysis, exchange optimisation and subscriber behaviour studies. The equipment can be expanded to up to 64 modules of 250 lines each, i.e. up to lines can be monitored. The exact volume of tape required will depend on the number of connections made; typically a 300-line PABX with average loadings would require one magnetic tape e.g ft. reel with the tape density of 1600 b.p.i,) for every 2 to 3 week1 s run (Ref. 39). This enables the system to be left at a remote exchange without the need for daily surveillance. The cost of the equipment, however, is the main factor hindering its wider use. (Its rental charge at present is about 2,500 per week.) Also, it does not provide extensive on-line information to be used for daily maintenance purposes. Indeed, the analysis results are not known until the recorded data is processed.

94 91}. 4.6 TRAFFIC ENGINEERING BY ST1\1111 T1 MI" METHOD The purpose of the continuous attempts to improve the means of teletraffic recording has been, among others, to calculate the quantities of equipment to be provided in telephone exchanges. It is therefore appropriate to mention other techniques of obtaining the required estimates. A particular part of interest in a switching system can be examined by setting out a mathematical model to represent the system. This model can then be analysed for deducing facts about the behaviour o:c the model which may be applied to the actual system itself (Ref. 29). A mathematical model, composed of a logical description of the relevant and significant parts of the telephone switching system, together with a set of idealised assumptions about, the traffic offered, can be specified. This model must be simple enough to lend itself to analysis, but not too simple that results of no practical value ensue. Analytical studies of switching systems soon become exceedingly difficult when the model grows more complex for a better representation of the actual system. As a result of this, computer simulation of..a complex switching system becomes a valuable method of analysing the behaviour of the system. In such simulation the operation of the network can be logically described in the computer which would then generate thousands of simulated calls and feed them into the model in order to assess the performance of different parts of the system. Simulation techniques have been used in the study of a variety of traffic and trzenking problems (Ref. 29), including the

95 95. performance of electronic s%d tching sirs{,aim and the measurement of the probability of congestion in a given number of trunks with a specific grading arrangement. The results have demonstrated that statistically reliable information can be obtained when a large number of cells are processed. 4.7 MICROPROCESSOR-CONTROLLED TELEPHONE TRAPIPTC RECORDERS The previous discussions pointed out the need for a low cost and flexible processing power to be included in modern traffic records. Electronic traffic recorders are emerging to meet this need using microprocessor technology (see footnote) A Portable Electronic Traffic Recorder In January 1978 a microprocessor-controlled traffic recorder Down as "the software-controlled electronic processing trafficrecording equipment" (SCEPTRE) was announced (Ref. 42). This device -which is currently (May 1978) undergoing field trials, comprises two units. The main unit houses the display and programming arrangements, including the processor, memory and interface units. The power supply for the main unit is provided by the second unit which uses the exchange battery potential. _ A scan period of 18 seconds is used to monitor up to 256 P-wires and determine the number of calls in progress and register the call-count for each line in a data-store acting as a meter. At the start of the investigations into the work concerning this thesis no such devices-were available. Towards the end of'the. project two microprocessor-=based systems were announced. The project did not benefit from the announced systems.

96 96. Other facilities are included to enable the detection of permanently engaged circuits during the recording. Traffic recording is possible for. 2 busy hours per day for up to eight days. The equipment has several advantages over the conventional traffic recorders. It is portable, flexible and does not require regular meter readings to be taken. Therefore, the equipment can be left unattended for a week or, on the other hand, its other capabilities can be regularly consulted as a maintenance aid. However, this traffic recorder has a limited capacity and improvements are needed to enable its utilization in large exchanges A Call Detail Analyser A more complex traffic recorder unit is also undergoing field trials at present. This is a microprocessor controlled Call Detail Analyser (CDA), developed by the B.P.O. in order to produce a teletraffic logging equipment which exploited the advantages of microprocessor systems (Ref. 45). The equipment is based on the Intel 8080 microprocessor system and uses external hardware to scan a number of telephone lines through appropriate interface circuits. The choice of the external scanner was based upon the decision to relieve the micrporocessor of routine jobs and therefore improve its processing efficiency. The D.C. condition on each leg of each telephone line is passed through an attenuator and a voltage limiter circuit and is then switched sequentially, using CMOS analogue switches, to a set of common threshold detectors. The sequence is governed by the external scanner which samples each input 100 times per second. This

97 97. serial scan data is stored externally to the microprocessor, over 16 complete scans, and is then transferred into the processor memory within a period of 10 mi;. Hence, the processor is left with 150 ms during each complete cycle for uninterrupted processing of the input data. With the system clock running at 1 MHz, 64 inputs can be processed without the possibility of loss of data. A 16-bit word represents the condition of each input during the preceding 16 cycles. Using a series of pattern recognition, the processor can analyse the data and record, onto a magnetic tape cartridge, the following real time information: (a) The identity of the circuit. (b) The start time of the call. (c) The dialled digit pulse-trains which determine the final destination of each call. (d) The duration of each call. To ensure the efficiency of the software in terms of the execution time, assembly language is used to develop a program occupying 2 k-bytes of PROM with a 3 k-bytes of RAM as a working space. Man-Machine communication is possible through an alphanumeric display and a keyboard which gives the operator flexibility to change some of the parameters or to enter the real time clock prior to the use of the equipment. Multiprocessor techniques may be used in the future to improve the performance of the microprocessor-based traffic recorder and increase its capacity, which, for the above model, is undesirably low.

98 CONCLUSIONS The 'common type of electromechanical traffic recorders 'are slow in operation and require considerable manpower. The trend towards computerization of the recorders has been slow due to the relatively high cost of the equipment needed. There is also a problem in interfacing the electronic equipments with the electromechanical elements. A completely fresh design of access circuits would increase the cost of traffic recording while the present access point arrangements cannot take full advantage of the computer facilities. Direct taping of subscriber lines brings the traffic recorder closer to the subscriber and hence enables a more detailed traffic recording to take place. The subscriber behaviour can be better studied if future records include some information on supervisory tones. Microprocessors are providing means for a more advanced traffic recording technique, but the full influence and the capabilities of the new technology are yet to be assessed.

99 to first setector 50rns 2 S Register-Access Relay Set wn 100 count wires commoned pulse separatcrs commoned IHit T T A mark signal pulse monitor dial pulse detector Z perforator control 0 meter pulse monitor ca t timer Figs 401 Trunk _Traffic Analysis Equipment

100 Cord( I C ha r d.0 te,. Rete, rw T ; Bkr (3:t o) M cr -mir ~J r rrr 630,,e14 C N- 1' &c1 0 l Fig. 4.2 Traffic Recording by Computer O

101 PABX PABX Main Devision Frame Connection Boxes Input Scanner Queue Magnetic PCB,s Control Buffer Tape Module I Con_tro. Unit Magnetic Tape Transport Fig. 4 a3 Lay Out of C.I.L.E

102 toz Fig. 4.4 Determination of Line Status OV V ref V on-hook.,_, off-hook (a) ov. va on-hook off-hook dial impulses. end of -....f. - c --- ~{ (b)

103 103. CIIAlI'E'R 5 THE DESIGN OF AN IN'UE12PACE CIRCUIT 5.1 INTRODUCTION A telephone subscriber indicates his requirements by operating the dial associated with his telephone. The pulses from the dial control the exchange selectors which connect the subscriber through to the required number. The supervisory tones inform the subscriber of the current stage of the call setup process; the caller then initiates the next stage and waits for the outcome. In general, the communication between the subscriber and the exchange is in the form of A.C. and D.C. signals passing through a pair of wires which link the two together. Different variations of signalling systems exist, however; D.C. loop disconnect signalling with A.C. supervisory tones form the most common signalling systems practiced by the B.P.O. and is, therefore, assumed here. In order to link an electromechanical telephone exchange with a microprocessor-controlled traffic recorder, a suitable interface unit is required. In this chapter some design considerations are discussed and the circuit arrangement of one such unit and its performance are outlined. Towards the end of the chapter suggestions are made for a method of multiplexing the interface circuit. _ 5.2 BASIC REQUIREMENTS Most of the required data for telephone information can be measured on the subscribervs lines. Therefore the termination points in an exchange were considered suitable access points for teletraffic

104 10 4. data collection (many of the present systems for traffic recording only monitor the P-wire and tell if the line is busy or not). The access equipment, as was mentioned previously, contributes substantially to the cost of any teletraffic recorder; this is due to the large number of lines involved. Hence simplicity in the interface circuit is necessary to keep the cost down while multiplexing of a number of lines can be used to reduce the number of devices required. Fig. 5.1 shows the basic block diagram of the required interface whereby the A.C. and D.C. signals on the line are detected by suitable devices. It is these that provide the input data for the microprocessor. As the D.C. voltage of 50 V is unsuitable for an electronic device, an attenuator was considered with an A.C. amplifier compensating the loss of low voltage tone signals. The first consideration was the required input impedance of the circuit for minimum interference with the normal operation of the telephone system. This was particularly important in the case of loop disconnect pulsing, as these signals are vulnerable to changes' in the subscriber's line and other circuit conditions. 5.3 EFFECT OF L.INF CONDITIONS ON DIAL PULSING The standard dial speed is 10 pulses per second (p.p.s.) with the "break" to "make" ratio of 2:1 (i.e ms break, ms make). Tolerances of dial speed and ratio are set to 7 to 12 p.p.s. with a break percentage of 63 to 72 (Ref. 46). The impulsing relays are designed to have equal operate and release lags, under average line conditions, so that the original

105 105. impulse ratio is retained. Any difference between the operate and release lags introduces some degree of impulse distortion which can have adverse effects on the correct operation of the line and control relays. Fig. 5.2 shows the variation of flux in a typical impulsing relay when connected to a dial of normal impulse ratio (Ref. 9). The exponential rise of the current with the time constant L/R is due to the inductance of the relay and the total resistance (R) of the current path. The rise of the flux lags behind the current due to eddy current effects and the first break period in the relay contacts is shorter because of the higher initial value of the flux built up during the dial rotation period. An increase in the value of R e.g. increase in line resistance) reduces the maximum value of current in the impulsing relay and lowers the rate of current growth. The effect is, thefefore, an increase in the break ratio The Effect of a Resistive Load across the Lines A resistive load provides a path for a residual current in the impulsing relay when the dial springs open. This tends to prolong the release lag while shortening the operation lag due to the presence of a leakage flux before the dial springs close. Fig. 5.3 shows the operate and release lags of a sample relay when connected to a line of zero resistance with different values of leak resistance (Ref. 9). The operate lag reduces only by 1 ms at 20 kq leak resistance, while the release lag rises steadily

106 106. up to 40 Ing point, after which the lag increases sharply as the current through the relay becomes comparable with the line current through a set of closed dial springs. Therefore, the input resistance of any circuit across the lines of zero resistance should not drop below 40 hg for a tolerable impulse ratio distortion. The practical limit has to be higher for considerations such as the possible attenuation of speech signals and the loop resistance of longer lines (the Post Office specification requires not less than 1 Mg) The Effect of a Series R-C Load across the Line Fig. 5.4 shows a simplified representation of a line with a series R-C load and the inductance and the resistance of each coil of the impulse relay. The instantaneous current (i), caused by the opening of the dial contacts, tends to hold the relay and thereby decrease the break period. The expression representing (i) in Fig. 5.4 can be shown to be: d2i R di 1 dt 2 L dt 4- LC -7: 0 (5.1) where L and R represent the total inductance and the total resistance of the circuit respectively. It is, therefore, concluded that if Rib4L! 1/ LC, the corresponding flux in the impulsi.ng relay during the release condition would be of oscillatory nature (Fig. 5.5) and, therefore, capable of producing a short false make period. The frequency of the oscillation

107 107. is given by (Ref. 47): _ R` w = LC 4L2 (5.2) This frequency can be adjusted so as to bring the oscillation to zero before the next pulse is due to arrive. Also, the degree of damping (governed by e l %2L ) can be set to provide a steep initial decline for satisfactory release lag with no risk of false relay operation (Ref. 9). For high values of R (R more than a few tens of K Q), the range of values of C becomes more relaxed, because the nature of the flux decay becomes a non-oscillatory drop. Therefore, the possibility of false operation no longer exists; however, a certain release lag can be expected. As the values of RL and possible toil resistances are fixed, R1 can be increased to reduce the effect of any change in the capacitance. From the above discussion, it can be concluded that if resistance Ra in Fig. 5.6 is at least equal to 40 K (in a short line condition), the distortion of pulse ratio would not gravely affect the operation of the impulse relay. 5.4 " a'ttjct OF CONTNCT BOUNCE During the operation of mechanically-controlled contacts, the moving springs and the system of operating levers possess an appreciable amount of kinetic energy which results in a rebound of the moving system when this is suddenly stopped by a fixed contact. The contact bounce, if sufficient, allows the reopening of the contact and therefore interrupts the flow of current leading to the slower operation of the controlled relay.

108 108. For this reason, several mechanical precautions are nornully taken to minimize contact bounce. In the case of dial springs any possible contact bounce is over within 5 ms after closure or 15 ms after opening. The impulse relay is not normally sensitive enough to be reoperated by the effect of contact bounce, but to an electronic voltage detector the effect would be comparable with the effect of a genuine dial impulse. Hence, the maximum duration time of the contact bounce has to be considered if false recognition of a dial impulse is to be avoided. (This will be discussed later in more detail.) 5.5 LINE CIIARACTERISTICS DURING A CALL SETUP The operation of College exchange was described in Section 3.4 where the pairing arrangement on the S.17 exchange was discussed. It was noted that under this arrangement the plus leg of the telephone lines may be earthed as a means of signalling in the exchange. Furthermore, there is no reversal of the caller line potentials, in this exchange, to signal the called party's answer. Therefore, the potential changes across the negative line, with respect to earth, convey all the information required for teletraffic data collection, implying that one access point per subscriber would suffice in this special case. To study the nature of the actual signal on the subscriber lines, a u.v. recorder was connected across the negative leg and earth in the subscriberos side of the telephone line. The tracing of the recording is shown in Fig. 5.7.

109 109. The handset was lifted at point A, closing the subscriber7 s loop of Fig Dial tone was returned at point C as the line voltage changed to about -28 V allowing a measured current of about 78 ma in a circuit similar to Fig When the dial cam was rotated (point E) DON springs in Fig. 3.3 shorted the 35 Q coil and the microphone('r).consequently the voltage drop on the line increased as more current passed through the line. The next observed event was the effect of dial pulses (points F and G) which showed some oscillatory behaviour due to the spark quench capacitance across the dial springs as well as other line components, but the dial ratio of 2:1 was preserved. As the condition of the line after the first dialled digit (point H) was no different from the condition at D, it was concluded that in this case the first selector was acting as the first and second selector, accepting the first two digits. The second digit was dialled after the rotation of dial at I, and was followed by the extension of the line to the final selector (point K). The unsteady condition of the line at point K was attributed to the effect of relay contacts closing and also the short transition from the state of the line shown in Fig to the steady condition of Fig The increase in the line potential drop (point 0 was expected as the two 200 windings of the impulse-accepting relay appeared in series. The next two dialled digits produced similar conditions to the first two and the busy tone appeared on the line (point R) after the line loop changed to the condition represented by Fig The handset was replaced at point S and the line potential returned to open loop condition.

110 110. Abrupt changes in the state of the line, such as points B and T, were observed at random. The cause was not readily understood; however, these could represent various noises on the line as selectors are connected to or released from the line. Similar tests showed that the line potential was almost at a constant level (vt) while the line was ready to receive a tone (Figs and 3.18), or during the conversation between the caller and the called (Fig. 3:20). The balanced condition of the line, over which any A.C. signal is superimposed, is represented by points D, H and R in Fig. 5.7 where any small change in the line voltage at each of these points was due to the changes in the overall loop resistance and component tolerances. Fig. 5.8 shows the same line when it was called. The polarity of the line potential was reversed (Fig.:5.19) before the ringing current of 180 V peak to peak at a frequency of 25 Hz appeared on the line, and the original polarity was restored (Fig. 3.20) when the call was answered. 5.6 DESCRIPTION OF THE DESIGNED INTERFACE In an attempt to represent:the different states of Fig. 5.7 by a set of binary codes, the following procedure was adopted: A level detector was used to produce a logical output whenever the subscriber loop was closed. A second level detector recognised any line potential just above the D.C. potential (vt) of the line when receiving or expecting a tone or speech. Therefore binary 00 represented an open loop (e.g. point 0 1 binazy 01 indicated a closed loop with the line potential between vt and 50 V

111 (e.g. points D or R), and ti was the code for a closed loop with the negative line potential above vt (e.. points E or N). The supervisory tones of interest were: dial tone, busy tone, equipment engaged tone, and the ringing tone. The particulars of these are listed in Appendix (4), from which it is clear that apart from the dial tone, the other three consist of a 400 Hz tone interrupted at a pre-defined sequence. Therefore, a tone detector was used to give a logical.1 whenever a 400 Hz tone was detected. Hence, a three-bit code was formed to represent the states of the line. A second tone decoder, to establish the presence of dial tone, was considered non-essential because the system does not return equipment engaged tone in the event of no free outlet being available to the callers line circuit. Instead, the caller enters a queue waiting for a free outlet; thus, the first tone returned to the caller is, in most cases, the dial tone. (Busy tone is returned if no group or final selector is available.) Fig. 5.9 shows the circuit diagram of the interface used for experimental purposes. The component values were chosen to satisfy the requirements already discussed. The gain of the A.C. amplifier was adjusted, by RG, to compensate for the 0.08 attenuation factor of the 400 Hz tone and provide a reasonable signal for the tone decoder (Ref. 48). The latter was tuned to the centre frequency of 400 Hz (f0 = 1/CfRf) with a wide detection bandwidth which allowed for frequency tolerances of the 400 Hz tone generator (Appendix 4). The values of Co and Cb could strongly affect the speed of response of the tone detector. The maximum operating speed corresponded to the minimum value of CL

112 112. which if used could moire the tone decoder vulnerable to false triggering and output chatter due to speech and signals picked up by the microphone. The selected values were determined experimentally to give the best acceptable results in the event of the busy and the ringing tones. The level detectors were realized by using 741 operational amplifiers with a slew rate of 0.4 V per microsecond which was considered to be adequate for the experimental studies. The logical outputs were fed to a buffer which was scanned by the microprocessor at regular intervals. The data was not latched into the buffer so that the current condition of the lines, at the time of sampling, could be presented to the microprocessor. The prototype circuit of Fig. 5.9 was intended to provide a simple means of testing the principles involved. A low pass filter, prior to the tone decoder, or level detectors with faster response time could improve the performance of the circuit. Such modifications were left for the time when full performance of the equipment could be assessed under normal operating conditions Performance of the Circuit The designed interface was set up and connected across the negative wire of the subscriber's set in the manner shown by Fig The performance of the circuit, after adjustment of level detectors, can be seen in Figs. 5.10, and Fig shows that in the case of the first two dialled digits the last make period is registered (point A. for the first

113 113. digit and point B for the second). :But this was not the case for the other two dialled digits (points D and E), since the falling edge of the last make pulse in each train did not cross the reference voltage of level detector No. 2. Therefore the correct digit was represented by the number of breaks in a train of pulses, as registered by both level detectors..another point of concern was the sharp transient observed on the line at point C when the caller line was extended to the final selector. This particular signal was not detected by level detector No. 1; however, the detector is not immune from possible false triggering caused by similar spikes. In the event of this happning, the false break period can be distinguished from the normal impulse signal by its short duration (normal break period persists for ms). False triggering was later found to be a source of random error in the final results, and is discussed in Chapter 6, when comments on precautions against its wrong interpretation are made. The ringing current produced a series of pulses of short break periods (Fig. 5.11). The response of the tone decoder to the. busy tone is shown in Fig. 5.12, where it can be seen that the tone-on, tone-off periods are found not to be of equal duration. This was mostly due to the Slow response of the tone decoder caused by its output capacitance (C0). In th^ case of the College exchange the two tones to be detected were the ringing tone and the equipment engaged tone. As these two are quite distinct from each other, the distortion in the tone decoder output was not significant. However, the response of the tone decoder must be improved if equipment engaged tone and busy tone are to be correctly distinguished from each other,

114 M[TLTTPT,TXTNG ARRANGEMENTS The nature of telephone traffic is, as mentioned before, such that not more than a fraction of potential users of the system are likely to initiate simultaneous calls. Savings in the number of detector circuits can be achieved by multiplexing the lines. The actual number of lines which can be multiplexed depends upon factors such as the traffic intensity carried by each line, the scanning rate, and the response time of the multiplexer and the common circuit. Analogue CMOS multiplexers can be used to provide an adequate switching response time (switch on time of 20 Msec is possible). Level detectors with comparable operating speeds are also commercially available. Therefore, assuming the average instructiōn ' time of ti WLsec for current 8080 microprocessors, any software controlled scanning speed is conceivable for D.C. signal recognition. however, the A.C. signal detection circuit limits the speed with which attenuated signals on a group of lines can be sequentially switched through the multiplexer for the subsequent evaluation of the line condition. The tone decoders alone require about 25 ms (equivalent to 10 cycle periods) before positive identification of the 400 Hz signal can be given. Therefore a continuous path should be maintained between the line and the tone decoder for a period longer thn.n 25 ms. As it is not possible to predict the exact time at which a line is to receive a tone, the continuous path should, in practice, be kept for much longer than the minimum required. A tone decoder circuit must, therefore, be available to an active line for the period of almost the total call setup time, so implying that the number of simultaneous active lines on which full information collection is po:,,,ible would be equal to the number of

115 115. tone decoding circuits. A tone decoder can be shared between N telephone lines as long as the probability of having more than one active line in that group is considered low and tolerable. The probability of x active lines in a group of N can be calculated using the Binomial Probability Law P CN Ax (l_a)n_x x,n = x (5.3) and probability of more than x active lines (Ref. 49) is given by: Px,N = 1 n=x n= Pn,N (5.4) where C N the binomial coefficient and A is the traffic intensity (in Erlangs) carried on each line which is equal to the probability' of the line being busy (Ref. 37). The value of A is around 0.05 and 0.15 Erlangs for residential and business areas respectively (Ref. 5). The multiplexing arrangement of Fig can be used with a 28% chance of getting only one active line in a group of eight (N = 8) lines each with the traffic intensity of 0.05 E. The probability of having at least one active line in a group of eight lines is, then, equal to Therefore, the probability of finding the common circuit in use is also To improve the efficiency of using the common circuit, the value of N has to increase which would also give an undesirable increase in the probability of getting more than one call at a time. For example, if N was raised to 16, the probability of finding at least one active line in the group at any instant rises to 56 per cent,

116 116. but the possibility of having more than one simultaneous active line also rises from the value of (for N = 8) to This means that the chances of losing some information on the second active line, due to the continuous connection required for the first one, increase by about 13 per cent. A more efficient use of A.C. signal detection circuit can be made by the arrangement of Fig where two levels of multiplexing make each tone decoding circuit available to M.N lines. Only one set of level detectors is required to be available to the output of each first stage multiplexer via a connection independent of any connection to the tone decoders. This has been considered possible due to the fast response time of the level detectors compared with the possible software-controlled scanning rate. A further possibility of "blocking" has to be introduced to define the probability of an active line not receiving adequate attention due to the non-availability of a free tone decoder (note that this would be the blocking in the interface only; a further blocking may exist if the number of active lines becomes unmanageable due to the monitoring processor). In the arrangement of Fig. 5.11i all of the K tone decoders become busy when at least I{ of the M groups of N lines each require a tone decoder. The probability of a group of N lines having at least one active line can be calculated from equation (5.4) to be equal to: p0,n = 1 - P0,N. (5.5) Therefore, the probability of K tone decoders being busy is given by:

117 QK = M K M-K CK p0 N (1 - pn N i (5.6) 117. Hence, the blocking introduced by the number of tone decoders can be calculated from the following expression: HT = K=K QK K=() Generally in order to access a tone decoder, a line has to be the first active, line in its group and a tone decoder has to be available. Therefore, the overall probability of access to a tone decoder for each line in Fig is less than the same probability for a line in Fig The savings made in the arrangement of Fig. 5.14'to give more efficient use of tone decoders, may well be upset by the increase in the number of multiplexers and the relatively complex software, or hardware, needed to set up the required path. The advantage of having separate routes to D.C. and A.C. signal detection circuits, as in Fig. 5.14, can be mixed with the relative simplicity of the arrangement of Fig to give the circuit outlined in Fig Tn this arrangement the second active line in a group of N lines would be deprived of any A.C. signal detection circuit but its D.C. signals will be continuously scanned. Therefore, traffic details, in terms of the number of active lines, will be kept but some of the call details would be lost The Overall Interfacin Arrangement The methods of multiplexing so far discussed are by no means exhaustive. Other. methods may consider the use ofahardware scanner to relieve the microprocessor from a routine and time-wasting a

118 118. job. For the benefit of ;:hiu project the block diagram of Fig was considered as the final design upon which a teletraffic monitor program was based. Two 8-channel malṯiplexers were considered to provide an independent module of 16 lines. The particular line is addressed as an output port when the least significant Octal digit of the address selects one of the eight lines in the multiplexer whose address latch is enabled by the most significant five bits of the issued address. The 4-bit code (3 bits plus 1 bit permanently 0), representative of the line status, is then input via an input buffer selected by the same address, although a different input address can also be used by having a unique select code for the input buffer. The appropriate 3-bit code. can be extracted from the lower or the higher four bits of the input byte, the choice depending upon the logic 1 or 0 condition of the 4th bit of the input/output address used i.e. if this bit is 0 the lower four bits, and if 1 the higher four bits are selected). An uninterrupted route is maintained by not changing the multiplexer address during the next scan cycles. A possible way of achieving this can be by the use of an inhibit signal to freeze the latched address until the inhibit is removed from the latch. An alternative method is to remember the addresses which should be skipped during each scan in order to avoid disruption of a connected route. The latter method was used and this will be discussed in Chapter 6. A faster scan rate may be possible by feeding the outputs of a group of threshold detectors into one single buffer,'so that the off-hook condition of -a group of Tines can be input in the form

119 119. of a single byte. This could be a useful method of skipping a group of inactive lines, but the required effort in collection and formatting of the binary bits of information has to be weighed against the savings in the scan rate. The circuit of Fig provides for a maximum of 256 lines to be scanned; however., in practice a much lower value has to be considered due to the limitations on the operating speed of the microprocessor. The actual number would depend upon the traffic intensity and the processing time required by any specific monitor program (see Chapters 6 and 7).

120 120. sub's line attenuator+ voltage lirnitter a.c. signal amplifier tone decoder CL voltage threshold detector Fig. 5.1 Block Diagram of the Required Interface MAKE BREAK dial contact MAX FLUX OPERATE FLUX RELEASE FLUX $ ro release lag tri relay - contact I 4._ operate Fig. 5,2 lag Variation of Flux in a Typical īm,ulsing Relay

121 2 " r2 ~11 1 T.sov [ i, r.'rs vt R4 1 il:,, 3000 TYPE RELAY ONC - K. CONTACT VNIT I '121 RELEASE LAG _... OPERATE LAG AO 20 LEAK RESISTANCE (thovs*u0 ONMs) Fig. 5.3 Effect of Line Leakance on The Operate and Release Lags of an Impulsing Relay (FroeTelephony"By Atkinson) Fig. 5.k+. Subscriber's Line With a Series R-C Load 'Fig. 5.5 Change of Flux in a Sub. Line With a Series R-C Load - release flux operate flux (reverse) (reverse) ' I - i false make ( period

122 R,---; H ' Rb f _t_ R'1' T RL Subscriber's Loop With R and C Lad Fig. 5.6 K OV Fig. 5.7 Tracing of a Call Set-Up in College Exchange L~ M hf J IU

123 Fig. 5.8 Ringing Current on a Called Line

124 t r I amplifier i 1 CL I A.,. I/O R STB Cf = C =0.017F CL= 2.0J`F Ca=4.7/4F C1= 0.22/F Rf = 20 K. Pot. R =1K 1 R2=15 K 1 ref- 1 vatta0e I I 1 43K + 43K 4,44 43K + + 5V 741 ~ 5 v~ level detector ( L N_ [V 03 select R3=1K RG= 33K.Pot. RQ= 39K R6= 3.9K 1100K sv level detector 1 i 1 Fig. 5.9 Interface Circuit

125 Fig The Response of the Interface Circuit to the States of a Calling Line A2 ca HZ Tone Output of Tone Decoder 1 J Al A0 Outpu of Level Detector 11 breo.k II 11 B Output of Level Detector I1 a D L9.1 Tracing of a Call Set-Up in College Exchange N V7 0

126 126. Fig The Response of Level Detectors to Ringing Current. 1 cr

127 . ---' ao+++.v..r-sr~rvr. p,~,.nr. rti.t 1 e +-~-~.-r-.~.rr a. r.a..~~:~_ >r =.++»^.-~.- ~...r rcw. r-r~ns~ _.-_ -.tz. - 1 i /.s.f r #M r x,'" f 4w ~'+&'"~ --~` # i^.~x? (i'," r4r,.~1'un~.. ` z Rl~ 5.,,46'. ` iyt, St'y9i t i _)._;;-*ti; _ _ - t J...._,yr +. - ;--'..~.'"r "~.._j.~ ( ~F:' l'i~..-4,44 ' J~_ ~ '~ rics 'r'1b'6~..yll.l.d14 -.~- _.1=..._ T _ _- _-- -_ - -_ Fig Response of Tone Decoder to Busy Tone