CMP 301B Computer Architecture. Appendix C

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1 CMP 301B Computer Architecture Appendix C

2 Dealing with Exceptions What should be done when an exception arises and many instructions are in the pipeline??!! Force a trap instruction in the next IF stage According to the exception, flush any instruction that should not be executed For example instructions after data cache page fault Save the PC and flags registers To return from the exception, restore the machine status and continue after the instruction in which exception arises 2

3 Out of Order Exceptions Example: A load might cause a data page fault (4 th stage), while a succeeding instruction might cause instruction page fault (1 st stage). Instruction page fault should be delayed and propagated with the instruction 3

4 Superscalar Processors Throw Multiple EXE units to allow more ILP Simple Superscalar Processors In order issue Stall if structural hazards unit is busy Stall if data hazards

5 Superscalar Processor: Pipelined EXE stage Floating Point (FP) operations takes more than one cycle to execute EXE stages are pipelined to allow overlapping more instruction during execution assuming no data hazards. te: DIV unit is not pipelined

6 Superscalar Processor: Pipelined EXE stage Other than DIV, EXE could accept a data hazard free instruction every cycle initiation or repeat interval of 1 Latency: Number of intervening cycles between an instruction generate a result and another instruction uses it Number of stall cycles in case of data hazard Depth of execution pipeline -1

7 Superscalar Processor: Hazards Structural hazards might occur (For example, due to the unpipelined divide unit) Because of the deep pipeline, stalls for RAW hazards become more frequent

8 Superscalar Processor: Hazards WAW hazards might occur due to the different latencies of EXE units There might be more than one writes required in the same clock cycle (Solutions: duplicate write port or serialize writes in ID or WB )

9 Superscalar Processor: Imprecise exception Instructions complete out of order If a succeeding instruction causes an exception, how to save the status of the machine Consider an exception occurs in the SUB after the ADD completes, but no the DIV DIV.D F0, F2, F4 ADD.D F10, F10, F8 SUB.D F12, F12, F14 If ADD is allowed to write back, it changes the state of the machine (F10) The processor could not retrieve the state of the machine Imprecise exception Someone might say let the DIV to finish then start servicing the exception. Ok, but what if the DIV itself causes an exception

10 Out of order Completion: Approaches Allow imprecise exception: 1960s and early 1970s Store results in buffer and write back in order: needs large queue and complex forwarding logic Keep the original values of registers in a history file so that you could roll it back if needed Issue only if it is guaranteed that all the instructions in the pipeline will not cause exception: performance deterioration Software solution: pass all the PCs of the instructions in the pipeline to the exception handling routine. The routine should check which instruction should be re-executed and which should not.

11 Dynamic Scheduling Static scheduling is a software solution to reorder the instructions to resolve hazards Dynamic scheduling is to do the same, but on the hardware level In order issue: pipeline stall if dependency arises Out of order issue: any ready instruction out of order is issued to avoid pipeline stall

12 Dynamic Scheduling: Scoreboard Scoreboard is a data structure for dynamic scheduling that allows out of order execution Decode stage is divided into two stages Issue: decode and check for structural hazard Read operand: check for data hazard and read operand instruction buffer IF IS RO EX WB ID

13 Dynamic Scheduling: Scoreboard Instructions pass the issue stage in order and pass the operand read stage out of order Out of order execution could result in WAR and WAW hazards. Therefore, later instructions is stalled in scoreboard Scoreboard schedules only a straight-line instructions (i.e., scheduling window is limited by branches)

14 Stages of Scoreboard Control Issue decode instructions & check for structural hazards (ID1) If a functional unit for the instruction is free and no other active instruction has the same destination register (WAW), the scoreboard issues the instruction to the functional unit and updates its internal data structure. If a structural or WAW hazard exists, then the instruction issue stalls, and no further instructions will issue until these hazards are cleared. 14

15 Stages of Scoreboard Control Read Operands wait until no data hazards, then read operands from registers (ID2) A source operand is available if no earlier issued active instruction is going to write it, or if the register containing the operand is being written by a currently active functional unit. When the source operands are available, the scoreboard tells the functional unit to proceed to read the operands from the registers and begin execution. The scoreboard resolves RAW hazards dynamically in this step, and instructions may be sent into execution out of order. Scoreboard doesn t use forwarding 15

16 Stages of Scoreboard Control Execution operate on operands (EX) The functional unit begins execution upon receiving operands. When the result is ready, it notifies the scoreboard that it has completed execution. Write result finish execution (WB) Once the scoreboard is aware that the functional unit has completed execution, the scoreboard checks for WAR hazards. If none, it writes results. If WAR, then it stalls the instruction. Example: DIVD F0, F2, F4 ADDD F10, F0, F8 SUBD F8, F8, F14 Scoreboard would stall SUBD until ADDD reads operands 16

17 Scoreboard Data Structures Instruction status Which of 4 steps the instruction is in Functional unit status Busy Whether the unit is busy or not Op Operation to perform in the unit (e.g., + or ) Fi Destination register Fj, Fk Source-register numbers Qj, Qk Functional units producing source registers Fj, Fk Rj, Rk ready bits for Fj, Fk Indicates which functional unit (if any) will write each register. Blank when no pending instructions will write that register 17

18 Scoreboard Example LD LD MULT SUBD DIVD ADDD F6, 34(R2) F2, 45(R3) F0, F2, F4 F8, F6, F2 F10, F0, F6 F6, F8, F2 What are the hazards in this code? Latencies (clock cycles) LD 1 MULT 10 DIVD 40 ADDD, SUBD 2 18

19 Scoreboard Example Instruction j k Issue operandcomplet Result LD F6 34+ R2 LD F2 45+ R3 MULTDF0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Mult1 Mult2 Add Divide FU 19

20 Scoreboard Example: Cycle 1 Instruction j k Issue operand completeresult LD F6 34+ R2 1 LD F2 45+ R3 MULT F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F6 R2 Yes Mult1 Mult2 Add Divide Issue LD #1 Shows in which cycle the operation occurred. 1 FU Integer 20

21 Scoreboard Example: Cycle 2 LD F6 34+ R2 1 2 LD F2 45+ R3 MULTDF0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F6 R2 Yes Mult1 Mult2 Add Divide LD #2 can t issue since integer unit is busy. MULT can t issue because we require in-order issue. 2 FU Integer 21

22 Scoreboard Example: Cycle 3 LD F6 34+ R LD F2 45+ R3 MULTDF0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F6 R2 Yes Mult1 Mult2 Add Divide 3 FU Integer 22

23 Scoreboard Example: Cycle 4 LD F6 34+ R LD F2 45+ R3 MULTDF0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F6 R2 Yes Mult1 Mult2 Add Divide 4 FU Integer 23

24 Scoreboard Example: Cycle 5 LD F6 34+ R LD F2 45+ R3 5 MULTDF0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F2 R3 Yes Mult1 Mult2 Add Divide Issue LD #2 since integer unit is now free 5 FU Integer 24

25 Scoreboard Example: Cycle 6 LD F6 34+ R LD F2 45+ R3 5 6 MULTDF0 F2 F4 6 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F2 R3 Yes Mult1 Yes Mult F0 F2 F4 Integer Yes Mult2 Add Divide Issue MULT 6 FU Mult1 Integer 25

26 Scoreboard Example: Cycle 7 LD F6 34+ R LD F2 45+ R MULTDF0 F2 F4 6 SUBD F8 F6 F2 7 DIVD F10 F0 F6 ADDD F6 F8 F2 MULT can t read its operands (F2) because LD #2 hasn t finished Integer Yes Load F2 R3 Yes Mult1 Yes Mult F0 F2 F4 Integer Yes Mult2 Add Yes Sub F8 F6 F2 Integer Yes Divide 7 FU Mult1 Integer Add 26

27 Scoreboard Example: Cycle 8a LD F6 34+ R LD F2 45+ R MULTDF0 F2 F4 6 SUBD F8 F6 F2 7 DIVD F10 F0 F6 8 ADDD F6 F8 F2 Integer Yes Load F2 R3 Yes Mult1 Yes Mult F0 F2 F4 Integer Yes Mult2 DIVD issues. MULT and SUBD both waiting for F2 Add Yes Sub F8 F6 F2 Integer Yes Divide Yes Div F10 F0 F6 Mult1 Yes 8 FU Mult1 Integer Add Divide 27

28 Scoreboard Example: Cycle 8b LD F6 34+ R LD F2 45+ R MULTDF0 F2 F4 6 SUBD F8 F6 F2 7 DIVD F10 F0 F6 8 ADDD F6 F8 F2 Integer Mult1 Yes Mult F0 F2 F4 Yes Yes Mult2 LD #2 writes F2 Add Yes Sub F8 F6 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 8 FU Mult1 Add Divide 28

29 Scoreboard Example: Cycle 9 LD F6 34+ R LD F2 45+ R MULTDF0 F2 F4 6 9 SUBD F8 F6 F2 7 9 DIVD F10 F0 F6 8 ADDD F6 F8 F2 w MULT and SUBD can both read F2 How can both instructions do this at the same time?? Integer 10 Mult1 Yes Mult F0 F2 F4 Yes Yes Mult2 2 Add Yes Sub F8 F6 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 9 FU Mult1 Add Divide 29

30 Scoreboard Example: Cycle 11 ADDD can t start because Add unit is busy LD F6 34+ R LD F2 45+ R MULTDF0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F2 Integer 8 Mult1 Yes Mult F0 F2 F4 Yes Yes Mult2 0 Add Yes Sub F8 F6 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 11 FU Mult1 Add Divide 30

31 Scoreboard Example: Cycle 12 SUBD finishes. DIVD waiting for F0 LD F6 34+ R LD F2 45+ R MULTDF0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F2 Integer 7 Mult1 Yes Mult F0 F2 F4 Yes Yes Mult2 Add Divide Yes Div F10 F0 F6 Mult1 Yes 12 FU Mult1 Divide 31

32 Scoreboard Example: Cycle 13 LD F6 34+ R LD F2 45+ R MULTDF0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F2 13 Integer 6 Mult1 Yes Mult F0 F2 F4 Yes Yes Mult2 ADDD issues Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 13 FU Mult1 Add Divide 32

33 Scoreboard Example: Cycle 14 LD F6 34+ R LD F2 45+ R MULTDF0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F Integer 5 Mult1 Yes Mult F0 F2 F4 Yes Yes Mult2 2 Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 14 FU Mult1 Add Divide 33

34 Scoreboard Example: Cycle 15 LD F6 34+ R LD F2 45+ R MULTDF0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F Integer 4 Mult1 Yes Mult F0 F2 F4 Yes Yes Mult2 1 Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 15 FU Mult1 Add Divide 34

35 Scoreboard Example: Cycle 16 LD F6 34+ R LD F2 45+ R MULTDF0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F Integer 3 Mult1 Yes Mult F0 F2 F4 Yes Yes Mult2 0 Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 16 FU Mult1 Add Divide 35

36 Scoreboard Example: Cycle 17 ADDD can t write because of DIVD RAW! LD F6 34+ R LD F2 45+ R MULTDF0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F Integer 2 Mult1 Yes Mult F0 F2 F4 Yes Yes Mult2 Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 17 FU Mult1 Add Divide 36

37 Scoreboard Example: Cycle 18 LD F6 34+ R LD F2 45+ R MULTDF0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F Integer 1 Mult1 Yes Mult F0 F2 F4 Yes Yes Mult2 thing Happens!! Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 18 FU Mult1 Add Divide 37

38 Scoreboard Example: Cycle 19 LD F6 34+ R LD F2 45+ R MULTDF0 F2 F SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F Integer 0 Mult1 Yes Mult F0 F2 F4 Yes Yes Mult2 MULT completes execution Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 19 FU Mult1 Add Divide 38

39 Scoreboard Example: Cycle 20 LD F6 34+ R LD F2 45+ R MULTDF0 F2 F SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F Integer Mult1 Mult2 MULT writes Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Yes Yes 20 FU Add Divide 39

40 Scoreboard Example: Cycle 21 LD F6 34+ R LD F2 45+ R MULTDF0 F2 F SUBD F8 F6 F DIVD F10 F0 F ADDD F6 F8 F Integer Mult1 Mult2 DIVD loads operands Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Yes Yes 21 FU Add Divide 40

41 Scoreboard Example: Cycle 22 w ADDD can write since WAR removed LD F6 34+ R LD F2 45+ R MULTDF0 F2 F SUBD F8 F6 F DIVD F10 F0 F ADDD F6 F8 F Integer Mult1 Mult2 Add 40 Divide Yes Div F10 F0 F6 Yes Yes 22 FU Divide 41

42 Scoreboard Example: Cycle 61 LD F6 34+ R LD F2 45+ R MULTDF0 F2 F SUBD F8 F6 F DIVD F10 F0 F ADDD F6 F8 F Integer Mult1 Mult2 Add DIVD completes execution 0 Divide Yes Div F10 F0 F6 Yes Yes 61 FU Divide 42

43 Scoreboard Example: Cycle 62 LD F6 34+ R LD F2 45+ R MULTDF0 F2 F SUBD F8 F6 F DIVD F10 F0 F ADDD F6 F8 F Integer Mult1 Mult2 Add DONE!! 0 Divide 62 FU 43

44 Scoreboard: Cons Operands for an instruction are read only when both operands are available in the register file Scoreboard does not take advantage of forwarding Instructions write to register file as soon as they are complete execution (assuming no WAR hazards) and do not wait for write slot One additional cycle of latency as write result and read operand stages cannot overlap In-order issue for WAW/structural hazards limit scheduling flexibility Bus structure Limited number of buses to register file represent structural hazards 44

45 Scoreboard: Performance enhancement Performance 1.7X for FORTRAN programs 2.5X for hand-coded assembly Implement forwarding Solutions for WAR Queue both the operation and copies of its operands Solution for Structural Hazards Multiple execution units or pipelined execution units 45

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