AC-1: A Clock-Powered Microprocessor

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1 AC-1: A Clock-Powered Microprocessor W Athas, N Tzartzanis, L Svensson, L Peterson, H Li, X Jiang, P Wang, W-C Liu USC/Information Sciences Institute, 4676 Admiralty Way, Marina del Rey, CA 90292, USA Sony Semiconductor Company of America, San Jose, CA Rockwell Semiconductor Systems, Newport Beach, CA {athas,nestoras,svensson,lena}@isiedu, huaimin@ssa-deselsonycom, {jianx,wangp}@nbrockwellcom, weichuan@isiedu Abstract We describe the design of AC-1, a low-power 16-bit microprocessor which utilizes clock-powered logic to reduce dissipation in its power-intensive sections We present power measurements for a 05-µm n-well CMOS implementation A resonant clock driver recovers and reuses energy that would otherwise be dissipated as heat, yielding measured overall power reduction factors of four to five 1 Background Clock-powered logic is the energy-recovery logic style chosen for AC-1 In clock-powered logic, large on-chip capacitive loads are charged and discharged directly by the clocks Figure 1(a) depicts a simple circuit that works in this fashion The input, in dual-rail form, controls a transmission gate and a clamp transistor When the input is a logic zero, the output is held low by the clamp transistor When the input is one, clock charge passes to the output via the transmission gate Figure 1(b) depicts a conventional dynamic latch that, when contrasted to Figure 1(a), clearly demonstrates the fundamental difference between conventional power and clock power In this circuit, as in other conventionally clocked cir- V in dd q in q clock clock in C L clock q C in L The AC-1 microprocessor project is the culmination of our efforts to apply the principles of energy-recovery CMOS to the design of a complete, general-purpose microsystem The principal advantage of energy-recovery CMOS [1] is that power can be reduced well below the conventional fcv 2 limit by recovering and reusing circuit energies that would otherwise be dissipated as heat (a) (b) Figure 1: Clock-powered circuit (a) and conventional circuit (b) for similar function cuits, the clock lines control the gates of transistors which in turn steer charge from V dd to the output or from the output to ground Clock-powered logic is low-power logic when the path from clock source to the output charges adiabatically In the case of adiabatic charging [1, p 66], the clock transition time T is made greater than the RC time constant of the path from the clock source to the logic output There are myriad ways to model the energy dissipation in this case A simple and useful first-order approximation is RC E diss CV 2 T If the RC product is small compared to the transition time T, then energy dissipation per transition will be less than ( 1 2)CV 2 This is the well-known theoretical power advantage of energy-recovery CMOS and adiabatic computing The practical disadvantages have been the circuitry overhead for the energy-recovery process, the inevitable extra capacitance that must be charged and discharged each cycle by the clock, and reduced voltage scalability compared to other approaches [5] Energy-recovery CMOS does not require a small signal voltage swing to dissipate little power This property opens up the possibility of using it with small, fast, mostlynmos circuit structures that do not work well at low supply voltages The extent to which these reductions and optimizations in circuitry would offset the above mentioned disadvantages cannot be readily determined by single-gate power-delay calculations and simulations Our investigations of particular logic functions produced differing results depending upon the function and the input and output assumptions [2,3] We therefore decided to undertake the design of a microprocessor, which should represent a good cross section of different circuit elements, ie, latches, drivers, control logic, arithmetic, and storage In this paper, we present the design and implementation of the first AC-1 microprocessor and also laboratory performance measurements In Section 2, we present our general approach to clock-powered logic Section 3 contains a description of the high-level instruction set architecture and how it was realized with clock-powered logic Section 4 describes our implementations and the experi-

2 mental results of measuring the power-versus-frequency performance of the microprocessor chip In Section 5, we discuss some of the implications of resonant-clock drive We conclude with our conclusions in Section 6 2 Approach ϕ 1 ϕ 2 To meet our goal of developing clock-powered logic as a competitive low-power technology, we set out to solve two engineering problems simultaneously: to devise an energyefficient clock-power source, and to invent a style of clockpowered logic compatible with said source 21 Clock-power generation The two general approaches to the clock-power source are resonant drivers and stepwise-charging drivers [4] The resonant approach utilizes inductances to commute clock energy between electric and magnetic form The stepwise approach uses banks of switched capacitances to incrementally deliver and recover energy The stepwise approach is simpler to control and to integrate into a single-chip CMOS design, but we chose the resonant approach because of its inherently higher efficiency We used the blip circuit [6] which has been the workhorse for our energy-recovery CMOS experiments [2,7] The blip circuit has an extremely simple all-resonant circuit topology which consists of a pair of cross-coupled nfets and a pair of inductors that are in series with the power supply and clock rails (Figure 2) A small-signal model of the FET predicts that sinusoidal oscillations will be sustained on the outputs when the loop gain is exactly one However, when the loop gain is greater than unity, the output amplitude will grow until it becomes limited by the nonlinearities of the FETs We use this property to our advantage to generate the outputs waveforms of Figure 3, which resemble nonoverlapping half sinusoids Because the waveforms are not exactly half sinusoids, we refer to them informally as blips The blip circuit is a self-starting, self-oscillating, energy-efficient driver It can be locked to an external frequency at some loss of energy efficiency Hence, there is a trade-off between timebase instability, ie, jitter, and power efficiency Figure 3: Scope traces of the almost-non-overlapping two-phase clock waveforms of AC-1 s blip circuit 22 Clock-powered logic An immediate application for a resonant driver is to recycle clock-line energy of an otherwise conventional CMOS chip We have tried this approach for a small DSP chip that was clocked by a blip circuit SPICE simulations indicated an overall twofold reduction in power across a wide frequency range [2] The obvious next step was to use the clock lines as a power source for power-critical data and control lines The crucial component for speed and power performance is the circuit that passes charge to and from those loads We investigated many candidate circuits, starting with the simple transmission gate of Figure 1(a) Numerous parametric SPICE simulations of different circuits were conducted to evaluate performance and robustness We finally selected the bootstrapped energy-recovery latch () of Figure 4 The clock inputs of this circuit are compatible with the blip circuit Additionally, it exhibits high gain, high noise immunity, and very high energy-transfer efficiency Our design was inspired by the bootstrapped drivers proposed for hotclock nmos [8] ϕ ϕ D I V ISO I 1 I 2 V in bn M 1 M M 3 2 V out V dc L ϕ 1 C ϕ L ϕ 2 C ϕ 0 0 ϕ I V bn V out ϕ D M 4 C L Figure 2: The blip circuit as a resonant clock driver Figure 4: The and its voltage waveforms

3 The works as follows Input data input is sampled on ϕ I as shown in Figure 4 The transistor M 1 and the inverters I 1 and I 2 comprise a conventional dynamic CMOS latch The transistor M 2 isolates the boot node bn from the output of inverter I 2 when the boot-node voltage V bn exceeds V ISO minus one threshold voltage For normal operation, the isolation voltage is set to one threshold voltage above the V dd of the inverters (ie, V ISO = V dd + V TE ) When the input goes high, the bootstrap node charges up to the V dd of the inverters and a channel forms between M 3 s source and drain The rising edge of ϕ D causes V bn to also rise because of M 3 s gate-to-channel capacitance The extent to which V bn rises above the clock voltage depends on many factors, including the size of M 3, the inverter supply voltage ( V dd ), the magnitude of the clock-voltage swing, the threshold voltage of M 3, the body effect of M 3, and the size of the parasitic capacitances at the boot node Many of these factors are influenced by second-order device phenomena However, these are all localized to the two devices connected to the boot node We applied simple modeling equations [7] to rough in the transistor sizes and then ran SPICE simulations for final adjustments to the geometry For the AC-1 implementation, only a small set of sizes were utilized, so the latches could be simulated exhaustively When there is sufficient charge at the boot node, the clock pulse will pass through M 3 to the output A logic one is represented by a pulse which lasts one clock phase During both clock phases, the output provides a low-impedance path to either ground or the clock rail: M 4 holds the output low when the input is low; M 3 connects the output to the clock rail whenever the input is high The clocks run hot, in that the clock swing is greater than V dd : the magnitude of the clock swing equals V ISO The principal reason for running the clocks hot is to eliminate pfets in pass-gate structures and precharged gates and thereby the need for complementary clock pulses, which we do not know how to resonantly generate from the blip circuit There is also a performance advantage from the elimination of pfets in that the layout is more compact and parasitic capacitances are reduced The sample on one phase and then drive on the other nature of the meshes neatly with the two-phase waveforms of the blip circuit Figure 5 shows how E-R latches can be used with precharged logic or pass-transistor logic In both cases, it is important to note that not all of the energy is available for recovery, only that used to charge the path from the clock rail to the gate of the logic transistor Hence, if this path represents a significant capacitive load relative to the energy dissipated in the, it is worthwhile to use clock-powered logic Otherwise, it is more energy-efficient to use a conventional output buffer ϕ 1 V iso ϕ 2 X i ϕ 1 ϕ 1 V iso ϕ 2 Z i ϕ 1 ϕ 1 V iso ϕ 2 W i ϕ 1 X o ϕ 2 W o ϕ 2 (b) Figure 5: es operated with precharged logic (a) and pass-transistor logic (b) The serves three important functions: it is a latch, an energy-efficient driver, and also a level shifter This last function is because the clock swing is greater than V dd Hence, it is possible to generate hot logic signals and use these signals to control the gates of pass transistors With this arrangement, there is no threshold drop for normal- V dd signals that are steered through the pass transistors This capability is exploited in some of AC-1 s pass-transistor logic structures Hot signals increase the risk of latch-up There are two places where a hot signal could possibly forward-bias a pfet body diode The first is inside the at the output node of I 2 If V ISO is set too high, then a reverse current could flow from the boot node through the isolation transistor M 2 The second is from gate-to-channel capacitive coupling when a hot signal controls a pass gate that in turn has a source or drain connection to a pfet channel In addition to the well-known techniques for reducing latch-up risk, we ensure that all such circuit points are actively driven by a static logic gate Typically, the gate is an inverter, eg, I 2 of Figure 4 and I 1 of Figure 5(a) 3 The AC-1 architecture V dd ϕ ϕ 2 V iso ϕ 1 1 Y i ϕ 2 Precharged Gate Z o ϕ 2 (a) Pass- Transistor Gate U i ϕ V iso ϕ 1 Y o ϕ 1 The AC-1 datapath consists of a 16-by-16 three-ported register file connected by two operand buses and one result bus to the function units These units include an ALU, a shifter, a compare unit, and a load/store unit The instruction set is based on the 32-bit DLX [9] format but is pared down to 16 bits [10] The major difference between the formats is that the AC-1 instructions specify only two registers per operation with one register address serving as both a source and destination In all, there are 39 instructions of five types: load/store, register to register, move immediate, branch, and load constant I 1 ϕ 2 U o ϕ 1

4 Read Dec0 Read Register Dec1 File Write Dec Control Signals Control Unit ALU Comp Unit Shift PC Unit Figure 6: es in AC-1 datapath The AC-1 implementation is pipelined so that, in the best case, one instruction completes per clock cycle There are five pipeline stages: fetch, decode, execute, load/store, and writeback Pipelining works in favor of clock-powered logic, since it opens up new places in the design for inserting E-R latches Figure 6 shows the assignment of es to pipeline stages in the datapath Much of the logic in AC-1 is conventional The register file is built from the classic 6-T static RAM cell [7] es, as in Figure 4, drive the instruction-decode PLAs, the register-file decode inputs, the register-file word enable and writeport bit lines, the operand buses, the inputs of the PC-unit adders, and the control signals We use precharged circuits for the register file s NAND-style decoders and read bit lines The controller consists of precharged gates and domino PLAs The adder is a carry-select design based on passtransistor logic and precharged gates This design is used both in the ALU and in the PC unit The es serve to sequence the pipeline stages, to inject power into the logic blocks, and to convert the normal logic levels into hot signals In the case of precharged logic, the gate energy and accompanying parasitic capacitances are recovered in part For some of the pass-transistor logic, the es also drive the paths as well as the gates In these circuits, some of the path energy is also recovered 4 AC-1 implementation and measurement We have implemented AC-1 in a 05-µm n-well HP CMOS process made available to us through MOSIS The microprocessor core (not counting the pad circuitry) contains 12,737 transistors, 17% of which are pfets The core size is 69 mm 2 The layout could be made significantly more compact Since the chip size was limited by its pad ring, little effort was made to compactly place and route the major function blocks The design is fully custom Layout was done using Magic D-Bus es Clock- Powered Buses Conventional- Clock-Driver Enable Vdc External Clock on-chip circuitry Figure 7: On-chip clock driver schematic Figure 7 is a schematic of the AC-1 clock circuitry There are two on-chip clock drivers for experimentation purposes An external pin selects which clock driver is engaged The first driver is a conventional design It consists of cross-coupled NOR gates which are driven from an external clock source The outputs of the NOR gates are internally buffered to drive the large clock loads The entire conventional clock driver circuit is powered by a separate supply,, to make it possible to measure clock power separately The other clock driver is the blip circuit Its power nfets are on chip and are connected to two external inductors The required values of the external inductors are less than 100 nh for above-50-mhz operation With more than 4 nh of bond wire inductance in the present package (a 108 PGA), future generations of these chips will likely have the inductors built into the chip packaging It may even be possible to resonate the clock grid with no external inductors [11] Considerable effort went into the design of the global clock grid To minimize skew, we placed the conventional clock driver at the center of the chip (see Figure 8) From the center, the global clock rails form a coarse grid of three horizontal tracks and three vertical tracks spanning the entire chip This configuration yields a worst-case resistance of less than 4 Ω A drawback is that the metal wiring of the clock grid contributes 35% of the total clock-wiring capacitance The layout strategy for the blip circuit was different Since the blip circuit drive transistors are connected in parallel with the circuit load, we partitioned each of the two large drive transistors into 153 small transistors which we interspersed around the clock grid as space would permit To measure power, we downloaded small test programs into 7-ns static RAMs that made up the chip s external instruction store We observed no significant dissipation difference between different programs To measure power dissipation ϕ 2 ϕ 1

5 16 14 Conventional drive Resonant drive mw / MHz vs Frequency Control Unit Conven Clock Driver mw / MHz Datapath PC Unit Frequency (MHz) Figure 9: Power versus frequency for AC-1 Figure 8: Photomicrograph of AC-1 chip Note: this is a 08-µm part The 05-µm part is a re-framed linear shrink, but it photographs less well due to silicides for the conventional driver, we varied the external clock-frequency input from 35 MHz to 54 MHz For each frequency setting, we decreased the supply voltage until the part produced incorrect results and took measurements at the lowest voltages for which the chip was functional The core V dd ranged from 19 V to 26 V; ranged from 25 V to 33 V For the resonant driver, we attached external RF inductors ranging from 290 nh down to 99 nh We measured the frequency and power for each inductor pair As with the conventional driver, we decreased supply and clock voltages until the parts failed The core V dd ranged from 18 V to 25 V; the blip circuit V dc (see Figure 2) ranged from 10 V to 14 V The clock swing is approximately three times larger than V dc The graph of Figure 9 summarizes the power-versus-frequency performance of the processor from 35 to 58 MHz The net difference between the conventional-clock mode and the resonant-clock mode ranges between factors of four and five In conventional drive, the clock power was approximately 90% of the total power In resonant energy drive, clock power ranged from 60% to 70% 5 Discussion The laboratory performance-measurement results have been somewhat limited by our test setup PowerMill simulations indicate that the top speed should be 74 MHz SPICE simulations for the resonant drive circuitry indicate that the clock grid could support chip operation up to 150 MHz The following discussion is intended to explore the upper frequency limitations for future chip generations Under resonant drive, the duration of the clock pulses varies as the square root of the LC product of the inductance and the driven capacitance This variability makes it difficult to control or minimize clock skew and jitter for high-frequency operation Since data and control lines are clock-powered, the loading of the clock lines is data and instruction dependent, and can change for each clock phase A straightforward method to neutralize this effect is to use dual-rail encoding of data Then, the capacitive loading remains relatively constant, albeit at the worst-case level Alternative, less expensive approaches are also of interest For skew, the local RC delay per clock-rail segment varies with the driven capacitance Wider clock rails yield smaller values of R and thus reduce the skew The cost is additional clock-rail capacitance, but the energy associated with driving this capacitance is the most efficiently recoverable energy in the path from clock to logic output Clock jitter occurs when variations in the driven capacitance change the width of the clock pulses and thereby the relative position of the clock edges The minimum clock-pulse width is determined by the minimum capacitance, that is, excluding all single-rail conditionally-driven signals To ensure correct operation, it would be sufficient to design the combinational logic such that the maximum delay is shorter than the minimum clock-pulse width This rule, while simple, will lead to overly pessimistic design: combinational logic activated by a resonantly-driven single-ended signal will be exercised only when the clock load is larger than its minimum value, and therefore the clock pulse is wider than the

6 minimum Thus, the logic would be over-engineered if designed to the minimum clock-pulse width For the best match of logic delay to clock-pulse width, the capacitive load would have to track the maximum delay of the currently active logic This would be a daunting task in practice The LC product variation can also cause clock-pulse amplitude variation from one phase to the next There are two cases If the capacitance decreases rapidly from one phase to the next, the clock-voltage swing for the second phase will be too large The excess charge can be safely shunted away by diodes with some loss of efficiency A rapid increase in the capacitive load from phase to phase is more serious The inductor current built up during the first phase may not produce a sufficiently large voltage pulse for the second, more heavily loaded, clock phase Any fail-safe solution to this problem will likely involve a dissipation cost which must be traded off against the cost of the alternative: to limit the amount of clock-load variation by always driving more than the minimum possible load, for example by using dual-rail signalling To date, we have used the blip circuit in its simplest, most efficient configuration No extra circuitry was included to stabilize amplitude or frequency We did observe frequency and amplitude variation, but it did not appear to limit the performance in any significant way Overall, the blip circuit has served us well Our initial expectation was that AC-1 would operate at 20 MHz with off-chip blip circuit switches With the switches on-chip, the processor now runs at nearly three times the original target speed 6 Conclusion The AC-1 microprocessor project has demonstrated that clock-powered logic and resonant clock drivers can be used to build low-power microsystems At 54 MHz and under conventional drive, the AC-1 chip is a low-power microprocessor which dissipates 86 mw Under resonant drive, the part is a very-low-power microprocessor which dissipates 26 mw at 588 MHz These results are encouraging, but the ultimate question is how a clock-powered processor would compare to a conventional alternative A second implementation of the AC-1 instruction set architecture that would aggressively use conventional techniques for low power would be highly desirable but is unfortunately currently beyond our resources Instead, we will undertake a detailed examination of the AC-1 implementation through simulation to answer the question Of particular interest in this investigation will be the distribution of the parasitic capacitances The distribution for our clock-powered logic is significantly different from conventional CMOS These differences in terms of size and location bear directly on the relative benefit of the clock-powered approach Also, the importance and relevance of the distribution will likely change with further decreases in device feature sizes Acknowledgments The research described in this paper was supported by DARPA contracts DABT63-92-C0052 and DAAL K3528 We thank Jim Jones of Epic, Inc and Bart Richards of Tektronix The design and implementation of AC-1 s clock-power grid was inspired by discussions with Dr Tom Knight of MIT References [1] W Athas, Energy-Recovery CMOS, in J Rabaey, M Pedram (Eds) Low-Power Design Methodologies, Kluwer Academic Press, 1996, pp [2] W Athas, W-C Liu, L Svensson, Energy-Recovery CMOS for Highly Pipelined DSP Designs, 1996 Intl Symposium on Low Power Electronics and Design, Aug 1996, pp [3] N Tzartzanis, W Athas, Design and Analysis of a Low Power Energy-Recovery Adder, Fifth Great Lakes Symposium on VLSI, Mar 1995 [4] L Svensson, Adiabatic Switching, in AChandrakasan, R Brodersen (Eds) Low Power Digital CMOS Design, Kluwer Academic Press, 1996, pp [5] WC Athas, L Svensson, JG Koller, N Tzartzanis, EY-C Chou, Low-Power Digital Systems Based on Adiabatic- Switching Principles, IEEE Trans on VLSI Systems, Vol 2, No 4, Dec 1994 [6] WC Athas, L Svensson, N Tzartzanis, A Resonant Signal Driver For Two-phase, Almost-non-overlapping Clocks, Intl Symposium on Circuits and Systems, May 1996 [7] N Tzartzanis, W Athas, Energy Recovery for the Design of High-Speed, Low-Power Static RAMs, 1996 Intl Symposium on Low Power Electronics and Design, Aug 1996, pp [8] CL Seitz, A Frey, S Mattisson, S Rabin, D Speck, V van de Snepscheut, Hot-clock NMOS In Proc of the 1985 Chapel Hill Conference on VLSI, 1985 [9] D Patterson, J Hennessy, Computer Architecture: A Quantitative Approach, Morgan Kaufman Publishers, Inc, San Mateo, Calif 1990 [10] J Bunda, Instruction-Processing Optimization Techniques for VLSI Microprocessors, PhD Dissertation, Univ of Texas at Austin, 1993 [11] J Burghartz, K Jenkins, M Soyuer, Multilevel-Spiral Inductors Using VLSI Interconnect Technology, IEEE Electron Device Letters, Vol 17,No 9, Sept 1996, pp