To Boldly Do What Can t Be Done: Asynchronous Design for All. Kenneth S. Stevens University of Utah

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1 To Boldly Do What Can t Be Done: Asynchronous Design for All Kenneth S. Stevens University of Utah 1

2 Scaling Moore s Law transistor counts double every one to two years Cost has followed inverse trend Imagine this in other scenarios... Will scaling continue? 2

3 Manufacturing Size of wafers (single silicon crystal) 3

4 Education and Engineering Observation: Our Engineering proofs and professors appeared to be wrong... Why? 1. What affect do our assumptions have on our results? 2. Disruptive ideas change the foundations of our work. 4

5 Learn the rules so you know how to break them properly. Dalai Lama 5

6 Dynamic Logic Example What are the advantages of this logic style? What are the disadvantages? p p a b c a b footed, f = a + b + c unfooted, f = ab 6

7 Dynamic Gate Example Advantages: low latency, high gain Disadvantages: high power, noise Why are dynamic gates high power? They are high gain devices - is this contradictory? Assumption: We connect precharge to the clock. Low data activity, high precharge activity due to clocked configuration create power problem. Rule Breaker: Using dynamic gates as set-reset gates in sequential asynchronous logic results in over 2 the performance and energy efficiency of static gates. 7

8 Noise in Dynamic Gates Assumption: We use a simple jam-latch for a keeper to reduce noise in dynamic gates. p a b unfooted, f = ab o p a b a b unfooted, f = ab p o Is the Complementary Dynamic Gate keeper better? 8

9 Complementary Dynamic Logic These gates can be sized to give a better noise margin than static logic DC curves showing hysteresis of a dynamic CDL gate with keeper sizes ranging from 1, 5, to 10 the pull-up/pull-down stack. 9

10 VLSI is becoming Ubiquitous Proposition: The price of a product is proportional to it s weight 10

11 Technology and Art Technology is: formal creative predictable artistic How do we combine disparate requirements? 11

12 The Macintosh Inventor Model 12

13 Asynchronous Design: What are the Right Questions? What are your questions? 13

14 What are the Right Questions? What is async design? Why does async have a bad reputation? Are reactive designs a good thing? Is asynchronous design really faster? Where do theoretical advantages come from? What is relationship of Async and PVT variations? What are the overheads for handshaking? Is asynchronous design lower power? How does one achieve an advantage with this stuff? Are async designs { reliable, predictable, repeatable }? 14

15 What are the Right Questions? Can Async circuits be tested, DFT? Is Async modularity for real? Is async modularity practical (IP Reuse)? What would best be designed async? How to interface to clocked design? 15

16 What are the Right Questions? What are typical protocols? Various protocol benefits and disadvantages? What is the relationship between timing and async ckts/protocols? Are races versus speed paths a big issue? What is key requirement for async/protocol design? There are a million methodologies - which do I choose? 16

17 What are the Right Questions? What classes of circuits should I use? Do I need custom cell libraries? Why would one want to adopt async? (The Big 3) Why would one not want to do async? Should I do async? 17

18 Key Messages Async logic design techniques will be increasingly important for: power (thermal limits, battery life for mobile/wireless) design reuse (high integration, PVT variations) Developing CAD for async will likely be key to applying the techniques effectively to commercial designs sequential design has different CAD requirements state of the art is significantly behind 18

19 Characteristics Traditional Clocked Design Precise synchronization to central clock Low skew clock distribution network Provides same frequency and phase everywhere Faces challenges to reuse Optimality of frequency, re-pipelining for frequency changes, etc. Wires scale differently than gates: up to 40% dead cycle time needed to account for wire scaling for future process shrinks to avoid redesign Desire to move toward decentralized clocking Data valid bit emulates locality of self-timing clock gating, multiple frequencies, reuse 19

20 Characteristics Traditional Async Design statistical behavior based on function & data State transitions when data becomes valid Modular interfaces using handshake protocols Faces challenges with deployment Synchronization, validation challenging with clocked systems Hazard-free logic: control and data Delay-Insensitive protocols inefficient Moving toward increased timing in design Building data with timing reference Relative timing in protocols 20

21 Circuit Timing Protocol Matrix 21

22 Apples-to-Apples Comparison 22

23 Timed Asynchronous Designs 23

24 In some sense, Apple s most fundamental problem, perhaps, is that a modestly superior technology is still an inferior solution if it lacks synergy with the mainstream. The Mac just isn t enough better to justify its isolation. Michael Slater, MPR Vol 11 No. 17, Dec , p27 There is more to a successful technology than technology itself. 24

25 Gaining Synergy with the Mainstream As Steve Jobs learned, going mainstream might not be as distasteful as one might think... New Direction for Async Design: Utilize clocked CAD to synthesize, place, and route unclocked designs. (But I still can t force myself to use MS Widoze... ) 25

26 Relative Timing Relative timing approach is novel: 1. timing representations are now explicit, not implicit designers and tools can reason about, specify, manipulate timing, measure coverage,... automatically support far more general circuit structures 2. timing based on logical representation, not absolute (ps) allow efficient search and verification algorithms interface to other tools: static/statistical timing, place and route verify nondeterministic interfaces (bisimulation)... yet include absolute values for setup, hold, etc. This can alter the way designers think about timing! 26

27 FF data clk What is Relative Timing FF clk data i i + 1 Express RT as relative relationship between signal events RT creates Formal proof of timing & behavior correctness Complements static timing tools by providing coverage clk } i data {{ clk i+1 }}{{} +m spec. design timing assumptions RT-FV initial conditions RT constr. absolute margins STA signoff 27

28 Designing RT for Commercial CAD Relative timing a characterization Fixed template methodology Tightly coupled to timing, design tools Direct RT formats & optimizations based on existing CAD Directly operate on templates Template abstractions.sdc constraint mappings Completeness and correctness Formal gate and verification models Timing driven synthesis and P&R constraints Post layout constraints Algorithm development Methodology for evaluating RT set quality in clocked CAD 28

29 Template Based Design Flow Small set of pre-designed templates in library Templates are technology mapped RT Flow: Characterize and map to sdc constraints AO32HVTD0 lc0 (.A1(lr),.A2(ra_),.A3(y_),.B1(lr),.B2(la),.Z(la)); AOI32HVTD0 lc1 (.A1(lr),.A2(ra_),.A3(y_),.B1(ra_),.B2(rr),.ZN(rr_)); NR2HVTD0 lc2 (.A1(la),.A2(rr),.ZN(y_)); NR2HVTD0 lc4 (.A1(rst),.B1(rr_),.ZN(rr)); INVHVTD0 lc5 (.I(ra),.ZN(ra_)); associated sdc file set_size_only -all_instances [ find -hier cell *lc0 ]... set_disable_timing -from A3 -to Z [find -hier cell *lc0] set_disable_timing -from B2 -to Z [find -hier cell *lc0]... set_data_check -rise_from */lc0/a3 -fall_to */lc0/b2 -setup $race_margin set_data_check -fall_from */lc0/a2 -rise_to */lc0/b2 -setup $race_margin... report_timing -delay max CLK -rise_to */lc0/b

30 Bisimilar Logic Conformation A binary relation LC P P over agents is a logic conformation between implementation I and specification S if (I,S) LC then α Act and β A {τ} (outputs and τ) and γ A (inputs) (i) (ii) Whenever S α S then I such that I α I and (I,S ) LC Whenever I β I then S such that S β S and (I,S ) LC (iii) Whenever I γ I and S γ then S such that S γ S and (I,S ) LC 30

31 Formal Verification Models Implementation is parallel composition of gates Compositional formalism allows direct netlist translation bi IMPOR ( A121O2I0bc01[li/a, ri_/b, y_/c, lo/d, lo_/e] \ INV[lo_/a, lo/b] \ A121O2Ia0c01[ri_/a, li/b, y_/c, ro/d, ro_/e] \ INV[ro_/a, ro/b] \ ORNB000[lo/a, ro/b, y_/c] \ INV[ri/a, ri_/b] \ ) \ { y_, lo_, ro_, ri_ } Specification bi LEFT lr. c1. la. c2.lr. la. LEFT bi RIGHT c1. rr. c2.ra. rr.ra.right bi SPEC (LEFT RIGHT) \ {c1, c2} 31

32 Test Chips Designed: 1. Simple MIPS processor 2. Baseband Controller In progress: 1. FFT chip using polyphase decimation 32

33 Break Rules with Care The good news is we ve created a highly sophisticated, multi-processor computer that s the size of a doughnut. The bad news is... Fitsimmons just dunked it in his cocoa. 33

34 We cannot solve our problems with the same thinking we used when we created them. Albert Einstein This is what Asynchronous Design is all about. Let s think about our problems differently and use this rich VLSI canvas to solve them in ways never previously dreamed. 34