QDI Fine-Grain Pipeline Templates

Transcription

1 QDI Fine-Grain Pipeline Templates Peter. eerel University of Southern alifornia Outline synchronous Latches Fine Grain Pipelining Weak ondition Half uffer Template uffer Logic Examples Precharge Full uffer Template 9/9/2 US synchronous VLSI/D 2

2 synchronous Latches: -elements Generalization of synchronous dynamic latch to store state Most ommon Example: The Muller -element fter all inputs rise, output rises Output stays high until after all inputs fall when output goes low Output stays low until all inputs rise again wk 2-input -element 9/9/2 US synchronous VLSI/D 3 Staticizer Design Used to hold state when output is not actively driven Fight leakage current and to some degree noise Weak inverter needed: (W/L) 5-x smaller than nominal If nominal size is small, need to use big L (more than minimal) to make W/L small enough Problem: adds significant capacitance to output node Solution Use weak P and N that are always on to make inverter weak (Paver 94) L >> min wk L >> min Weak inverter : schematic + possible implementation 9/9/2 US synchronous VLSI/D 4

3 Fully-Static -element Staticizer can be removed by feeding back output of -element to create fully-static -element design etter noise margin, but more input capacitance Fully Static 2-input -element 9/9/2 US synchronous VLSI/D 5 symmetric -element Have inputs removed from either pullup or pull-down stack + denotes only in pull-down stack (involved in only -t- transition) - denotes only in pull-up stack (involved in only -to- transition) Generalized -elements have multiple pullup and/or pull down stacks + wk symmetric 2-input -element 9/9/2 US synchronous VLSI/D 6

4 Four-phase Protocol quest Sender ck nowledge ceiver quest c k nowledge st communication 2nd communication Two-phases active communication Two-phases turn to zero phases 9/9/2 US synchronous VLSI/D 7 synchronous Functional locks Input hannels F Output hannels Functionality ad a subset of input channels Waits for input channels to have data tokens ompute F and write to a subset of output channels Waits for output channels to be reset cknowledges input channels sets output channels Upon being acknowledged 9/9/2 US synchronous VLSI/D 8

5 Fine Grain Pipelining Input hannels F Output hannels asic Idea Each stage very small Fast latency Two gate delays forward latency One dynamic gate plus the inverter Fast cycle time -8 gate delays depending on template chieves 7+ in.25 micron technology 9/9/2 US synchronous VLSI/D 9 Dual-rail Encoding Dual-rail (-of-2) 2 wires per bit Generalizes to -of-n dvantages quest encoded in data Less timing assumptions Disadvantages More wires Generalizes to -of-n F Data T ck Data (2N-bits) Dual-Rail hannel Data F Logical Value set Invalid F2 9/9/2 US synchronous VLSI/D

6 ompletion Detectors sponsible for determining when set of -of-n channels have valid data when set of -of-n channels have reset V h OR h OR V D h n OR h h n ompletion Detector & Implementation for n dual-rail channels 9/9/2 US synchronous VLSI/D Weak ondition Half uffer Weak ondition Validity of outputs implies validity of inputs Inputs consumed -> can assert acknowledgement set of outputs implies reset of inputs Inputs reset -> can de-assert acknowledgement Le L R Le L ank of -latches R L R WH -of-n uffer WH -of-2 uffer (optimized) 9/9/2 US synchronous VLSI/D 2

7 WH w/ Logic Logic becomes complex Pull-up and pull-down stacks are big _ e _ R_ Weak ondition OR WH OR R R_ Function lock 9/9/2 US synchronous VLSI/D 3 Pre-charge Half-uffer Goals Use pre-charge logic and an input completion detector instead of weakcondition logic quires 2 guard transistors (Pc and Eval) in Function blocks moves many P-transistors in pull-up and pull-down Eval Pc Le Rx L LD Eval Pc F RD R L Pull-down Logic Function block schematic for each output rail 9/9/2 US synchronous VLSI/D 4

8 PH Handshaking Operation Precharge stage N : When stage N-, stage N,stage N+ completes evaluation Evaluate stage N : When stage N-, stage N,stage N+ completes precharging LD F RD LD F2 RD LD F3 RD 9/9/2 US synchronous VLSI/D 5 onditional ading and Writing onditional ading of Input hannels Le generation modified Need one Le per input rail cknowledge only input channel that is read ontrol signals need to be part of Le logic onditional Writing of Output hannels Skip circuitry Generate extra N+ output that is not routed out but goes to completion detection Modify circuitry so that you don t wait for reset of output channels that were not written 9/9/2 US synchronous VLSI/D 6

9 Summary asic WH and PH templates shown Fine grain pipelining Great for high-speed an it be used efficiently? Depends if can feed pipeline fast enough ut can this also yield low-power for a applications that need not so much speed? Maybe if Use more sequential rather than parallel algorithm Use lower power supply to get quadratic savings 9/9/2 US synchronous VLSI/D 7