Introduction to VLSI Design

Transcription

1 Introduction to VLSI Design Instructor: Steven P. Levitan TA: Gayatri Mehta, Jose Martinez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed out 1 Digital EE141 ECE Integrated 1192 Circuits 2006, 2nd Steven Levitan, University of Pittsburgh Introduction

2 Course Outline (approximate) Introduction and Motivation The VLSI Design Process Details of the MOS Transistor Device Fabrication Design Rules CMOS circuits VLSI Structures System Timing Real Circuits and Performance 2 Digital EE141 ECE Integrated 1192 Circuits 2006, 2nd Steven Levitan, University of Pittsburgh Introduction

3 Reference Books Digital Integrated Circuits: A Design Perspective Rabaey et. al CMOS VLSI Design A Circuits and Systems Perspective (3rd Edition) Neil Weste and David Harris Addison Wesley Introduction to VLSI Circuits and Systems Uyemura More on reserve in the Library Chen, Smith, Sedra & Smith, etc. 3 Digital EE141 ECE Integrated 1192 Circuits 2006, 2nd Steven Levitan, University of Pittsburgh Introduction

4 Software Cadence icfb Schematic and Layout editors Unix Based Some Auto-Layout generation Batch Design Rule Checking Circuit Extraction - LVS Many Supported Technology files HSPICE Based on well known SPICE (HSPICE is better) Good support/documentation Interface with both schematic and Layout Verilog / (later) High level design and evaluation Fast functional validation Synthesis from Verilog to circuit to layout Others Micro Magic Max and Sue and Data Path Compiler Etc. 4 Digital EE141 ECE Integrated 1192 Circuits 2006, 2nd Steven Levitan, University of Pittsburgh Introduction

5 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30,

6 What is this book all about? Introduction to digital integrated circuits. CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies. What will you learn? Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability 6

7 Digital Integrated Circuits Introduction: Issues in digital design The CMOS inverter Combinational logic structures Sequential logic gates Design methodologies Interconnect: R, L and C Timing Arithmetic building blocks Memories and array structures 7

8 Introduction Why is designing digital ICs different today than it was before? Will it change in future? 8

9 The First Computer The Babbage Difference Engine (1832) 25,000 parts cost: 17,470 9

10 ENIAC - The first electronic computer (1946) cost: ~$500,000 17,468 vacuum tubes, 7,200 crystal diodes, 1,500 relays, 70,000 resistors, 10,000 capacitors 30 tons 8 feet by 3 feet by 100 feet 150 kw of power I/O via IBM cards Patch cords, NOT a stored program Electronic Numerical Integrator and Computer EE141 Integrated Digital Circuits2nd 10 Introduction

11 The Transistor Revolution First transistor Bell Labs,

12 12 Copyright 2005 Pearson Addison-Wesley. All rights reserved.

13 The First Integrated Circuits Bipolar logic 1960 s 6 Transistors 5 Resistors True and complement outputs ECL 3-input Gate Motorola

14 14 Copyright 2005 Pearson Addison-Wesley. All rights reserved.

15 Intel 4004 Micro-Processor transistors 1 MHz operation 15

16 Intel Pentium (IV) microprocessor M Transistors 100MHz (?) 16

17 Moore s s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months 17

18 Moore s s Law LOG2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION Electronics, April 19,

19 19 Copyright 2005 Pearson Addison-Wesley. All rights reserved.

20 Transistor Counts 1,000,000 K 1 Billion Transistors 100,000 10,000 1, i486 Pentium i Pentium III Pentium II Pentium Pro Source: Intel Projected 20 Digital EE141 Integrated Circuits 2nd Courtesy, Intel Introduction

21 Moore s s law in Microprocessors Transistors (MT) X growth in 1.96 years! Digital EE141 Integrated Circuits 2nd Courtesy, Intel Introduction 486 P6 Pentium proc Year Transistors on Lead Microprocessors double every 2 years

22 Die Size Growth 100 Die size (mm) P6 Pentium proc ~7% growth per year ~2X growth in 10 years Year Die size grows by 14% to satisfy Moore s Law 22 Digital EE141 Integrated Circuits 2nd Courtesy, Intel Introduction

23 Frequency Frequency (Mhz) Doubles every 2 years P6 Pentium proc Year Lead Microprocessors frequency doubles every 2 years 23 Digital EE141 Integrated Circuits 2nd Courtesy, Intel Introduction

24 Evolution in Complexity 24

25 Power Dissipation 100 Power (Watts) P6 Pentium proc Year Lead Microprocessors power continues to increase 25 Digital EE141 Integrated Circuits 2nd Courtesy, Intel Introduction

26 Power will be a major problem Power (Watts) Pentium proc 18KW 5KW 1.5KW 500W Year Power delivery and dissipation will be prohibitive 26 Digital EE141 Integrated Circuits 2nd Courtesy, Intel Introduction

27 Power density Power Density (W/cm2) Rocket Nozzle Nuclear Reactor Hot Plate P6 Pentium proc Year Power density too high to keep junctions at low temp 27 Digital EE141 Integrated Circuits 2nd Courtesy, Intel Introduction

28 Not Only Microprocessors Cell Phone Small Signal RF Power RF Units Digital Cellular Market (Phones Shipped) M 86M 162M 260M 435M Power Management Analog Baseband Digital Baseband (DSP + MCU) (data from Texas Instruments) 28

29 Challenges in Digital Design DSM Giga = 1/Nano 1/DSM Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different? Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and There s a Lot of Them! 29

30 CMOS:Complementary MOS Means we are using both N-channel and P- channel type enhancement mode Field Effect Transistors (FETs). Field Effect- NO current from the controlling electrode into the output FET is a voltage controlled current device vs. BJT (which is a current controlled current device) N/P Channel - doping of the substrate for increased carriers (electrons or holes) 30 Digital EE141 Integrated ECE 1192 Circuits 2nd Steven Levitan University of Pittsburgh Introduction

31 Silicon Doping Group V atoms: Phosphorus or Arsenic, one more electron n-type Group III atoms: Boron, one less electron p-type Doping concentrations: 10e-5 (strong) to 10e-8 (weak) 31 Copyright 2005 Pearson Addison-Wesley. All rights reserved.

32 N-Channel Enhancement mode MOS FET Four Terminal Device - substrate bias 32 Digital EE141 Integrated ECE 1192 Circuits 2nd Steven Levitan University of Pittsburgh Introduction

33 33 Copyright 2005 Pearson Addison-Wesley. All rights reserved.

34 VLSI:Very Large Scale Integration Integration: Integrated Circuits multiple devices on one substrate How large is Very Large? SSI (small scale integration) 7400 series, transistors MSI (medium scale) series LSI 1,000-10,000 transistors VLSI > 10,000 transistors (original definition) ULSI/SLSI (some disagreement, VLSI > 10M) 34 Digital EE141 Integrated ECE 1192 Circuits 2nd Steven Levitan University of Pittsburgh Introduction

35 VLSI Design But the real issue is that VLSI is about designing systems on chips. The designs are complex, and we need to use structured design techniques and sophisticated design tools to manage the complexity of the design. We also accept the fact that any technology we learn the details of will be out of date soon. We are trying to develop and use techniques that will transcend the technology, but still respect it. 35 Digital EE141 Integrated ECE 1192 Circuits 2nd Steven Levitan University of Pittsburgh Introduction

36 The Process of VLSI Design: Consists of many different representations/abstractions of the system (chip) that is being designed. System Level Design Architecture / Algorithm Level Design Digital System Level Design Logical Level Design Electrical Level Design Layout Level Design Semiconductor Level Design (possibly more) Each abstraction/view is itself a Design Hierarchy of refinements which decompose the design. 36 Digital EE141 Integrated ECE 1192 Circuits 2nd Steven Levitan University of Pittsburgh Introduction

37 Help from Computer Aided Design tools Tools Editors Simulators Libraries Module Synthesizers Placers/Routers Chip Assemblers Silicon Compilers Experts Logic design Electronic/circuit design Device physics Artwork Applications - system design Architectures 37 Digital EE141 Integrated ECE 1192 Circuits 2nd Steven Levitan University of Pittsburgh Introduction

38 New Design Methodologies Methodologies which are based on: System Level Abstractions v.s. Device Characteristic Abstractions Logic structures and circuitry change slowly over time trade-offs do change, but the choices do not Scalable Designs Layout techniques also change slowly. But the minimum feature size steadily decreases with time (also Voltage, Die Size, etc.) 38 Digital EE141 Integrated ECE 1192 Circuits 2nd Steven Levitan University of Pittsburgh Introduction

39 Technologies Bipolar (BJT) dual Junction, current controlled devices TTL, Schottky ECL I^2 L Voltage controlled devices Metal Oxide Silicon Field Effect Transistors (MOS FET) NMOS, PMOS (enhancement, depletion) CMOS <== our course Single Junction voltage controlled devices GaAs (typically JFET s) OEIC s - MQW s, Integrated Lasers,? 39 Digital EE141 Integrated ECE 1192 Circuits 2nd Steven Levitan University of Pittsburgh Introduction

40 Design Approaches Custom full control of design best results, slowest design time. Semi-custom (std cell) use Cell libraries from vendor cad tools, faster design time Gate Array fastest design time worst speed/power/density best low volume (worst high volume) EPLA/EPLD - FPGA - electrically programmable (in the field) - 40 Digital EE141 Integrated ECE 1192 Circuits 2nd Steven Levitan University of Pittsburgh Introduction

41 Productivity Trends 10,000,000 10,000 1,000,000 1, , , , Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity growth rate 100,000,000 10,000,000 1,000, ,000 10,000 1, Complexity Logic Transistor per Chip (M) Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity 41 Digital EE141 Integrated Circuits 2nd Courtesy, ITRS Roadmap Introduction

42 Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly (effective area grows by 2x) Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Exploit different levels of abstraction 42

43 Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT S n+ G DEVICE n+ D 43

44 Figure 1.2 (p.4) General overview of the design hierarchy. 44 Introduction to Circuits, Fourth Edition by Peter Uyemura, Copyright 2004 John Wiley & Sons. All rights reserved.

45 Design Metrics How to evaluate performance of a digital circuit (gate, block, )? Cost Area Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function 45

46 Cost of Integrated Circuits NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area 46

47 NRE Cost is Increasing 47

48 Die Cost Single die Wafer Going up to 12 (30cm) From 48

49 Cost per Transistor cost: -per-transistor Fabrication capital cost per transistor (Moore s law)

50 Yield Dies No. of good chips per wafer Y = 100% Total number of chips per wafer Die cost = π per wafer = Wafer cost Dies per wafer Die yield ( wafer diameter/2) die area 2 π wafer diameter 2 die area 50

51 Defects die yield = defects per unit area die area 1+ α α is approximately 3 α die cost = f 4 (die area) 51

52 Some Examples (1994) Chip Metal layers Line width Wafer cost Def./ cm 2 Area mm 2 Dies/ wafer Yield Die cost 386DX $ % $4 486 DX $ % $12 Power PC $ % $53 HP PA $ % $73 DEC Alpha $ % $149 Super Sparc $ % $272 Pentium $ % $417 52

53 ITRS Technology nodes International Technology Roadmap for Semiconductors Sponsored by the five leading chip manufacturing regions in the world: Europe, Japan, Korea, Taiwan, and the United States. The objective of the ITRS is to ensure cost-effective advancements in the performance of the integrated circuit and the products that employ such devices, thereby continuing the health and success of this industry. --- Moore s Law Police 53

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63 Silicon in 2010 Voltage: V Technology: μm Metal layers: Clock: 10-15GHz Metal Pitch: 45nm Active length: 30nm/18nm (38/23nm low power) DRAM: 32Gbit on 24x24mm die Logic Transistors: 6G on 30x30mm die Pins: 1,000 4,000 (66% Power Pins) Power: W Wafer Size: 12 diameter 63 EE141 Digital Integrated ECE Circuits 1192 Circuits 2nd Steven Levitan Introduction University of Pittsburgh Prentice Introduction Hall 1995

64 more than Moore 64

65 Summary Digital integrated circuits have come a long way and still have quite some potential left for the coming decades Some interesting challenges ahead Getting a clear perspective on the challenges and potential solutions is the purpose of this book Understanding the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipation 65

66 Reliability Noise in Digital Integrated Circuits i(t) v(t) V DD Inductive coupling Capacitive coupling Power and ground noise 66

67 DC Operation Voltage Transfer Characteristic V(y) V OH f V(y)=V(x) VOH = f(vol) VOL = f(voh) VM = f(vm) V M Switching Threshold V OL V OL V OH V(x) Nominal Voltage Levels 67

68 Mapping between analog and digital signals 1 V OH V out V OH Slope = -1 V IH Undefined Region V IL Slope = -1 0 V OL V OL V IL V IH V in 68

69 Definition of Noise Margins "1" V OH V OL NM H NM L V IH Undefined Region V IL Noise margin high Noise margin low "0" Gate Output Gate Input 69

70 Noise Budget Allocates gross noise margin to expected sources of noise Sources: supply noise, cross talk, interference, offset Differentiate between fixed and proportional noise sources 70

71 Key Reliability Properties Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric the capability to suppress noise sources Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver; 71

72 Regenerative Property out out v 3 f (v) v 3 finv(v) v 1 v 1 finv(v) v 3 f (v) v 2 v 0 Regenerative in v 0 v 2 Non-Regenerative in 72

73 Regenerative Property v 0 v 1 v 2 v 3 v 4 v 5 v 6 A chain of inverters 5 V (Volt) 3 1 v 0 v 1 v 2 Simulated response t (nsec)

74 Fan-in and Fan-out N M Fan-out N Fan-in M 74

75 The Ideal Gate V out g = R i = R o = 0 Fanout = NM H = NM L = V DD /2 V in 75

76 ( V ) V o u t An Old-time Inverter NM L V M 1.0 NM H V in (V) 76

77 Delay Definitions V in 50% t V out t phl t plh 90% 50% 10% t t f t r 77

78 Ring Oscillator v 0 v 1 v 2 v 3 v 4 v 5 v 0 v 1 v 5 T = 2 t p N 78

79 A First-Order RC Network R v out vin C t p = ln (2) τ = 0.69 RC Important model matches delay of inverter 79

80 Power Dissipation Instantaneous power: p(t) = v(t)i(t) = V supply i(t) Peak power: P peak = V supply i peak Average power: 1 P ave = ) T V t+ T supply t+ T p( t dt = t t T i supply () t dt 80

81 Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = P av t p Energy-Delay Product (EDP) = quality metric of gate = E t p 81

82 A First-Order RC Network R v out v in C L E 0 1 T T Vdd = Pt ()dt = V i t dd supply ()dt = V C dv dd = C V L out L 2 dd E cap T T Vdd = P cap ()dt t = V out i cap ()dt t = C L V out dv out = C 2 L 2 V dd 82