Advanced ROIC designs for cooled IR detectors. Xavier Lefoul, Patrick Maillart, Michel Zécri, Eric Sanson, Gilbert Decaens, Laurent Baud

Transcription

1 Advanced ROIC designs for cooled IR detectors Xavier Lefoul, Patrick Maillart, Michel Zécri, Eric Sanson, Gilbert Decaens, Laurent Baud Outline Introduction Presentation of latest FPA currently available at Sofradir New ROIC design functionalities ROIC design tendencies & Power management Conclusion

2 Introduction Cooled infrared technologies are covering a wide range of detection and performances are regularly increased à ROIC designs have to deal with all these requirements and are requested to offer new advanced functions Technology and application needs New IR detector technology needs Third generation developments Larger formats & smaller pixel pitches Use of avalanche photodiodes (e-apd) Use of dual band detectors New processing functions Double Time Integration mode (DTI) Pixel peak current controller ADC on chip Þ design activity highly challenged

3 Circuit Latest FPA currently available at Sofradir Neptune Saturne Epsilon Scorpio Jupiter Input stage CTIA CTIA DI DI DI Array format 500 * * * * * 1024 Pixel pitch 30 µm 30 µm 15 µm 15 µm 15 µm Nb of output 2 or 4 4 or or 8 Nominal pixel rate (Mpixels/s/output) Maximum pixel rate (Mpixels/s) Readout mode Snapshot Snapshot Snapshot Snapshot Snapshot Window mode Each line may be selected or not Each line may be selected or not 384 * 288 or 320 * 256 Random (min. 128 * 1) Random (min. 256 * 1) Storage Capacity 525 Ke- or 2.2 Me- 525 Ke- or 2.2 Me- 3.9 Me- 4.4 Me- 4.2 Me- Readout noise < 100 e- or 240 e- < 100 e- or 240 e- < 260 e- < 390 e- < 350 e- New ROIC functionalities Bicolor ROIC Bicolor readout circuits allow to integrate currents issued from two diodes operating at different bandwidths (SWIR/MWIR, MWIR/MWIR, ) while keeping spatial and temporal coherence. dual band pixel Array size : 640x512 Pixel pitch : 24µm Storage capacity : 3,5 Me-/10,5 Me- Integration mode : Snapshot Readout modes : ITR, IWR, DTI Nb of outputs : 4 Pixel rate : 20 Mpixels/s/output Power consumption : < 80 mw Readout noise : < 130 µv rms

4 New ROIC functionalities Double Time Integration (DTI) mode High dynamic of the scene may be limited by the readout circuit signal to noise ratio (SNR). To overcome this issue, two integrations may be performed in the same pixel with two different integration times, thus allowing to see faint glimmers as well as hot spots in the same scene. t1 INT1 INT2 t2 Þ improves the contrast New ROIC functionalities Pixel peak current controller Up to a certain level of blooming, it may be important to limit the current through the diode and the ROIC to avoid any perturbation and/or damage Current limitation Response to a triangle current source input

5 New ROIC functionalities ADC on chip (1/2) > Three main approaches Pixel Column Amplifier Output Amplifier Pixel ADC + Need the lowest clock frequency + Best performances + Lowest power consumption - Large area Column ADC + Need lower clock frequency + Lower power consumption + Easily pipelined - Column dispersion - Full digital Video Output ADC + No conversion dispersion on die + Reduced area + Choice between and digital - Performances - Power Consumption New ROIC functionalities ADC on chip (2/2) : Column ADC Sigma-delta converters Large number of bits High power consumption in large array applications Need of a very high frequency clock Large area Ramp converters Lower clock frequency than the previous Σ- converter Power consumption reduced but still high compared to a purely readout circuit Algorithm converters Good control of power consumption Lowest clock frequency Constant conversion time Lower number of bits than Σ- conversion

6 Example of column ADC Algorithm ADC on chip performances TV format, 15 µm pitch Non linearity : <10 bits (0.1%) SNR : > 13 bits (noise < 200µV RMS ) frame frequency : 80Hz Output data format : 2 x 8 bits Master clock frequency: 60MHz Power consumption : less than 70 µw per column The key success for on chip ADC is the good control of power consumption. ROIC design tendencies Nbr of pixels 4M 1.3M 300K 95% 99% 95% 96% 95% 74% 95% <60% 100K digital digital digital digital digital digital digital digital Years Power sharing Exponential development of digital part in Area sharing cooled FPAs is becoming a reality requiring to use power management and adapted technologies.

7 ROIC design tendencies Power management Analog domain supply : ^ SNR Digital domain supply : Power dissipation Year < Typical array format Digital power consumption 320 * * * % 3.9 % 26 % Silicon technologies trend is to increase the density and therefore reducing the supply voltage. Infrared ROICs will take benefit of it for designing smaller pixel pitches while lowering the per pixel power consumption. CONCLUSION Innovative ROIC s design solutions to meet performances and power constraints are necessary to answer the needs of new IR detectors * FPA technology evolutions pixel pitch shrink larger HgCdTe arrays Dual band detectors APD (Avalanche photodiodes ) * New ROIC design solutions Low power ADC on-chip Þ Signal Processing on-chip DTI (Double Time Integration) mode Local current limitation through the pixel ROIC design in IR detectors is more and more complex à requiring not only more aggressive deep sub-micron CMOS technologies but also more aggressive power management techniques.

8 The author thanks the CEA-Leti and Sofradir teams for their outstanding work, as well as the French MoD for its support Thank you for your attention