Power and Area Efficient Column-Parallel ADC Architectures for CMOS Image Sensors

Transcription

1 Power and Area Efficient Column-Parallel ADC Architectures for CMOS Image Sensors Martijn Snoeij 1,*, Albert Theuwissen 1,2, Johan Huijsing 1 and Kofi Makinwa 1 1 Delft University of Technology, The Netherlands 2 Harvest Imaging, Belgium * Now with Texas Instruments, Germany 4 th Fraunhofer IMS Workshop on CMOS Imaging May 6 th, 2008

2 Outline Why column-level A/D conversion? Application of existing ADC architectures Development of new custom Architectures: Multiple-Ramp Single-Slope (MRSS) ADC Multiple-Ramp Multiple-Slope (MRMS) ADC Conclusions 2

3 Why A/D Conversion in CMOS Imagers? A key advantage of CMOS imagers is cointegration of analog & digital signal processing Camera-on-a-chip On-chip A/D converter essential! Properties: Complex analog function Important factor in overall quality Significant fraction of overall power consumption System-level of ADC is of key importance: Place of ADC within signal processing chain ADC architecture 3

4 Chip-Level ADC approach + Single ADC: Robust, simple solution + ADC separate from imager: standard cell can be used Single ADC: bottleneck for high readout speeds 4

5 Column-Level ADC Approach ADCs working in parallel allows for higher speeds + Shorter analog signal path Ensuring uniformity between ADCs design problem More chip area 5

6 Pixel-Level ADC Approach + 1 million ADCs per chip extremely high framerates possible + Very short analog signal path + Digital processing within array possible Ensuring uniformity between ADCs design problem Very large chip area impractical for most applications 6

7 Approaches for CMOS Imager A/D Conversion Total ADC speed Chip-level ADC (1/chip) Column-level ADC ( 1k/chip) Pixel-level ADC ( 1M/chip) Complexity / Chip area Power efficiency rather than absolute speed limitations often decisive Number of pixels strongly increasing in mainstream imagers Trend from chip-level towards column-level ADC 7

8 Architectures for Column ADCs What are column ADC requirements: Small circuit Uniformity between columns Good power/speed ratio Existing ADC Architectures used in column ADCs: Cyclic/algorithmic [1-2] Successive approximation [3-4] Single-Slope [5-8] Custom ADC Architectures for column ADCs: Multiple-Ramp Single-Slope (MRSS) Multiple-Ramp Multiple-Slope (MRMS) 8

9 Single-Slope ADC Architecture NB ramp generator is implemented centrally comparator only analog part in column 9

10 Single-Slope Architecture Pros & Cons Advantages: Simple column circuit Easy to correct for nonuniformities Disadvantage: Conversion time takes 2 n clocks for n-bit poor power/speed ratio Long conversion time can force designer to reduce resolution to increase speed [8] Existing, faster solutions are the Successive Approximation (SAR) or Cyclic ADC 10

11 SAR ADC Architecture DAC output depends on input signal Each column needs its own DAC! 11

12 Cyclic (Algorithmic) ADC Architecture Every circuit block function depends on input Apart from Vref, no central circuitry possible 12

13 SAR/Cyclic Architectures Pros & Cons Advantages: Conversion takes n clocks for n-bit Disadvantages: Column circuit too complex Uniformity between columns major issue 13

14 Problems of Conventional ADC Architectures Single-slope very suited for use in parallel system (central ramp generator), but too slow SAR good improvement in conventional ADC applications, but difficult in parallel system Some compromise between single-slope and SAR would be good Idea for new architecture found at Linköping University [9] and Delft University [10][11] First prototype presented Feb [10] 14

15 SAR & Single-Slope Common Principle Comparator basis of both architectures Reference signal fed to comparator different SAR requires feedback from comparator to DAC 15

16 SAR & Single-Slope Common Principle Comparator basis of both architectures Reference signal fed to comparator different SAR requires feedback from comparator to DAC Approach: comparator only analog in column no feedback Multiple reference outputs 16

17 Multiple-Ramp Single-Slope (MRSS) Concept Input signal is compared to ramp voltage To increase speed, use multiple ramps concurrently 17

18 MRSS Concept: Coarse & Fine Phase 2-step Conversion: 1. Coarse phase: Determine which ramp should be connected to comparator 2. Fine phase: Multiple ramps run concurrently 18

19 MRSS Concept: Overlap in Fine Phase Small error in coarse phase can cause comparator being connected to wrong ramp Some overlap between ramps required to prevent dead-bands 19

20 MRSS ADC Block Diagram Number of ramps is trade-off between ramp generator power and ADC speed First prototype uses 8 ramps 20

21 MRSS Column Circuit Compared to single-slope, only additional circuitry are switches + some logic Small column circuit 21

22 MRSS ADC Block Diagram Column-level additions for MRSS are simple Increased design complexity mainly in ramp generator 22

23 Ramp Generator Requirements Main Requirements: 1. All ramps need a welldefined offset 2. All ramps should have same slope Ramp generator implemented as 8 matched DACs 23

24 Multiple Ramp Generator Principle Generator consists of: 1 coarse ladder 8 fine ladders Common coarse ladder ensures matching between ramps 24

25 Chip Micrograph Specifications: 400 x 330 pixels 7.4µm pixel pitch 20MHz system clock 0.25µm 1P3M process 2.5V/3.3V supply Die size: 5mm x 5mm 25

26 Image Captured in Single-Slope Mode Single-slope image for comparison 10-bit resolution A/D conversion time 20MHz =53µs 50 frames / second 26

27 Image Captured in MRSS Mode 10-bit resolution A/D conversion time 20MHz =16µs 142 frames / second Speed increase: 3.3x conversion time 2.8x frame rate 16% power increase 27

28 MRSS Architecture Pros & Cons Advantages: In theory, conversion takes 2 p + 2 q clocks for n-bit, n = p + q in practice some more clocks needed Simple column circuit Easy to correct for nonuniformities Disadvantages: Ramp generator more complex Slight increase in digital overhead More details can be found in [10] & [11] 28

29 Extending the MRSS ADC: MRMS ADC All imagers exhibit photon shot noise, which has unique property of increasing with signal In principle, any ADC can exploit this property to reduce power and/or increase speed In practice, few ADC architectures are suited for this some implementations shown in singleslope ADCs [12][13] The MRSS concept is very suited Multiple-Ramp Multiple-Slope (MRMS) ADC 29

30 Exploiting Photon Shot Noise in ADC 30

31 Exploiting photon shot noise in ADC 31

32 Reducing ADC Performance 32

33 Reducing the Number of Quantization Steps By increasing quantization step, total number of steps is reduced: Step size (LSBs): Total: Number of steps: Table shows number of steps needed for 10b resolution 2x smaller then normal quantization If effectively implemented, this means 2x less power or more speed, without visible image quality loss 33

34 A Multiple-Ramp Multiple-Slope ADC In an MRSS ADC, quantization step defined by increase of ramp voltage per clock Photon shot noise exploitation by changing ramp slopes: Multiple-Ramp Multiple- Slope (MRMS) ADC 34

35 MRMS Measurement results 10-bit resolution A/D conversion time 20MHz =12.8µs frame rate not increased due to digital limitation Speed increase: 25% compared to MRSS 4.1x compared to singleslope 35

36 MRMS Architecture Pros & Cons Advantages: Further reduction in conversion time compared to MRSS Simple Column circuit Easy to correct for nonuniformities Disadvantages: Ramp generator more complex compared to MRSS Perceptual impact not fully studied (digital still vs video) Slight increase in digital overhead More details can be found in [11] 36

37 Summary Column-Level ADC provides good trade-off between power-efficiency and complexity for high resolution CMOS image sensors Existing ADC architectures have either too complex column circuits or are too slow MRSS architecture significantly increases speed and power efficiency of column-level ADC Further increase in speed & power efficiency by exploiting photon shot noise with MRMS ADC 37

38 References [1] S. Decker, R.D. McGrath, K. Brehmer, and C.G. Sodini, A 256 x 256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output, IEEE Journal of Solid-State Circuits, vol 33, no. 12, pp , Dec [2] M. Mase, S. Kawahito, M. Sasaki, Y. Wakamori, and M. Furuta, A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters, IEEE Journal of Solid-State circuits, vol. 40, no. 12, pp , Dec [3] Z.Zhou, B. Pain, and E.R. Fossum, CMOS active pixel sensor with on-chip successive approximation analog-to-digital converter, IEEE Transactions on Electron Devices, vol. 44, no. 10, pp , Oct [4] B. Mansoorian, H. Yee, S. Huang and E. Fossum, A 250mW 60 frames/s 1280 x 720 pixel 9b CMOS digital image sensor, IEEE International Solid-State Circuits Conference, vol. XLII, pp , Feb [5] W. Yang, O-B. Kwon, J-I. Lee, G-T. Hwang and S-J. Lee, An integrated 800 x 600 CMOS imaging system, IEEE International Solid-State Circuits Conference, vol. XLII, pp , Feb

39 References [6] T. Sugiki et al., A 60 mw 10b CMOS image sensor with column-to-column FPN reduction, IEEE International Solid-State Circuits Conference, vol. XLIII, pp , Feb [7] K. Findlater et al., SXGA pinned photodiode CMOS image sensor in 0.35ìm technology, IEEE International Solid-State Circuits Conference, vol. XLVI, pp , February 2003 [8] Y. Nitta et al., High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor, IEEE International Solid-State Circuits Conference, vol. XLIX, pp , Feb [9] L. Lindgren, A new simultaneous multislope ADC for array implementations, IEEE Trans. On Circuits & Systems II vol. 53, pp , September 2006 [10] M.F. Snoeij, P. Donegan, A.J.P. Theuwissen, K.A.A. Makinwa, and J.H. Huijsing, A CMOS image sensor with a column-level multiple-ramp singleslope ADC, ISSCC Dig. Tech. Papers pp , February

40 References [11] M.F.Snoeij, A.J.P. Theuwissen, K.A.A. Makinwa, and J.H. Huijsing, Multiple-Ramp Column-Parallel ADC Architectures for CMOS Images Sensors, IEEE Journal of Solid-State Circuits, Vol. 42, No. 12, pp , December 2007 [12] O-B. Kwon et al., A Novel Double Slope Analog-to-Digital Converter for a High- Quality 640x480 CMOS Imaging System, IEEE Int. Conference on VLSI and CAD, pp , October 1999 [13] T. Otaka et al., 12-Bit Column-Parallel ADC with Accelerated Ramp, IEEE Workshop on CCDs and Advanced Image sensors 2005, pp , Karuizawa, Japan, June