Outline. Introduction 2/2. Introduction 1/2. Paper presentation Ultra-Portable Devices. Introduction. System Design for Ultra-Low Power.

Transcription

1 Paper presentation Ultra-Portable Devices Paper: Bernier, C. Hameau, F., et al. An Ultra Low Power SoC for 2.4GHz IEEE wireless communications, Solid-State Circuits Conference, ESSCIRC th European, On page(s): , Publication Date: Sept Outline Introduction. System Design for Ultra-Low Power. Digital Design for Ultra-Low Power. RF/Analog Design for Ultra-Low Power. Presented by: S. M. Yasser Sherazi Measurement Results. Summary. 1 2 Introduction 1/2 IEEE , 2.4GHz transceiver designed in 130nm CMOS A novel mini. complexity partial correlation algorithm At 1.2V, the RX/TX drains 5.4mW in RX and 8.1mW in TX 1% PER for a -81 dbm input power 250kbit/s data rate, the RX/TX energy efficiency is 21.5nJ/bit RX and 32.5nJ/bit TX Introduction 2/2 Complete system modeling for ULP direct conversion RX/TX. Elementary function optimization for minimum power. A novel digital baseband demodulation algorithm for minimum power and area. The RX/TX integrated on a SoC with an 8051 micro-controller clocked at 8MHz. 32kbyte memory (SRAM) & 4kbytes for user data. All internal clocks derived from a single 40MHz external clock. 3

2 SOC Architecture System Design for ULP Spreading of the 250kbps data stream into a 2Mchip/s Mapping 4-bit symbol onto one of 16 quasi-orthogonal Seq. 32-chip pseudo-random sequences. Chip stream is modulated using O-QPSK Digital part of receiver, half of the spreading codes are complex conjugates. Reduced Correlation algorithm. System Design for ULP 32-chip (GC) vs 8 4-chip (PC) Implementation (Digital) Eight non-coherent 4-chip partial correlations. Rather than a single 32 chip correlation. Well suited for ULP. Most Complex calculation is square Most Multiplications are by + 1.

3 System Design for ULP Simulated PER vs. Input Power Implementation (Analog) Information in sign of baseband I and Q signal. Non-linear amplification used in analog RX chain. Reduced resolution and low sampling rate ADC. ADC sampling rate 4MS/s and 3-bit dynamic range. Drastic reduction of consumption of RX/TX digital operator. Digital Design for ULP Digital RX Architecture Packet format for IEEE consective 0 symbols. Start Frame Delimiter (SFD). PBY Header (length of PSDU). PSDU is the payload.

4 Partial Correlation Algorithm Architecture of PC bank For each symbol period, the received symbol is: max( corr _ out( n)), N = 0,..,15 with corr _ out( n) = 7 3 p= 0 k= 0 s 2 n * p k ( c4 p k ) where s m is the m th complex signal sample (of 32) and c n m is the m th complex chip (of 32) of the n th spreading code (of 16). Generation of Spreading Codes RF/Analog Design for ULP Direct Conversion reciever architecture. Bandwidth of baseband chain is minimized. Amplifier s outout impedence can be increased. Its bias current is decreased withot sacrificing gain. Transistors can be biased in weak inversion. At weak inversion gm/ids ratio is highest.

5 2.4-GHz Transceiver Measurement Results State of the art transceivers (250 KBit/S). Measurement Results Measured Consumption Per Block Measured Digital RX current consumption (PSDU = 20 bytes)

6 Die Photograph (130nm CMOS) Picture of Demonstration Board 4mm 2 Digital, 5mm 2 Analog Circit area. Summary Papers to Look into High-level system modeling. High-level system simulation. It is at the architectural level that most power is saved. Through high-level simulations that the impact of each. W. Kluge et al., A Fully Integrated 2.4-GHz IEEE Compliant Transceiver for ZigBeeTM Applications, IEEE JSSC,Vol. 41, NO. 12, Dec. 2006, pp H. Ishizaki, K. Nose, M. Mizuno, A 2.4GHz ISM-band digital wireless transceiver with an intra-symbol adaptively intermittent RX, 2007 IEEE Symposium on VLSI Circuits Dig. Tech. Papers, pp Minimizes complexity in Algorithms. 23