Trend of CMOS Imaging Device Technologies

Transcription

1 004 6 ( ) CMOS : Trend of CMOS Imaging Device Technologies Abstract Which imaging device survives in the current fast-growing and competitive market, imagers or CMOS imagers? Although this question is still argued among experts, the conclusion has not come out yet. In recent years, the power balance of imagers and CMOS imagers has been changing quickly every two years. Now, CMOS image sensors challenge to take the market of s again. In this paper, I introduce the state-of-the-art technologies of CMOS image sensors behind the present trend of the image sensor market. 1 The Number of Image Sensor Products 700M 600M 00M 400M 300M 00M 100M Year Fig. 1. Trend of the world-wide image sensor products [1]. (Fig.1) vs. CMOS 30 MOS [] 3 CMOS [3] CMOS 1993 E. R. Fossum CMOS APS (Active Pixel Sensor)[4] CMOS vs. CMOS CMOS (FPN) CMOS vs. CMOS 000 CMOS 1 00 CMOS CMOS 1970 [3] Fig. (a),(b) (a) ( ) (b) 0% Fig. (c) 1

2 (a) Full-frame sensor array VDD VDD vertical transfer horizontal transfer (b) Interline transfer vertical transfer horizontal transfer (c) operation V3 V3 V3 V1 V1= +Vo V= +Vo V3= +3Vo V V3 V1 V V3 V1 V V3 V1= +Vo V= +Vo V3= +Vo V1= +Vo V= +3Vo V3= +Vo RST n + n + MR (a) Photodiode CMOS APS (a) before 001 Quality Power Cost Module size For movie VDD X Vb pixel PG TX RST n + n + FD MR VDD (b) Floating gate CMOS APS Fig. 4. Basic structures of CMOS APS. CMOS APS (b) after 00 Quality Power Cost Module size For movie X Vb pixel CMOS APS Fig.. Comparison between imager and CMOS imager: (a) before 001, (b) after 00 []. Fig.. Basic structure and operation of image sensor. (a) passive pixel sensor row1 row row3 out col1 col col3 (b) active pixel sensor (APS) row1 row row3 col1 col col3 CDS CDS CDS Fig. 3. Passive and active CMOS image sensors. (FPN) n 10 V 1967 MOS Passive Pixel Sensor(PPS) Fig.3 (a) MOS PPS CMOS Active Pixel Sensor(APS) CMOS APS 1993 CMOS Fig.3 (b) Fig.4 (a) PN 3 (b) CMOS APS PPS (CDS) CMOS vs. CMOS 3.1 ( ) 000 CMOS

3 Pixel pitch (µm) CMOS APS For over 100M pixel image sensor on Cellphone Fig. 6. Pixel pitch of and CMOS APS [, 7]. Year CMOS APS CMOS (a) CMOS CMOS CMOS 1? 3. ( ) (a) CMOS APS (b) <10% PD amp. PD circuit 30% transfer Fig µm-pitch pixel layout: (a) CMOS APS, (b). 1 V 1 V 7V 8V [6] CMOS CMOS 000 CMOS Fig mm 1/4 [7] µm Fig.6 Fig.7 (a) CMOS APS 3.8 µm 10%.8 µm 30% CMOS CMOS 00 CMOS 000 Fig. (b) 4 vs. CMOS 004 S/N 3

4 Minumum lithographic feature size (µm) CMOS imager pixel size (µm) future prospects (3.) (.4) (1.7) (1.) Fill factor (%) 3 () 8 () 91 () 96 () Fig. 8. Future prospects at 1996 [8]. 004 Fig [8, 9] [8] Moore [10] 1996 Fig.8 CMOS 001 µm Fig. 9. Input referred noise charges as a function of the minimum feature size [8]. 70 S/N 0. µm CMOS 6 CMOS 60 Fig [9] (DR) SN (SNR) DR = 0 log 10 i max i min = 0 log 10 q max i dc t int σ r + qi dc t int (1) DR and SNR (db) DR SNR Pixel size (µm) Fig. 10. Dynamic range and signal-to-noise ratio as a function of pixel size [9]. i max i min q i dc t int σ r ktc ( ) SN i ph SNR(i ph ) = 0 log 10 i ph t int σ r + q(i ph + i dc )t int () [11] Fig.10 SN q max C V s C ktc i ph SN CDS / 1 Fig.11 S-CIELAB[1] 4

5 Average E µm 0.µm 0.18µm Conventional color imager three color filters X3 image sensor three separate layers Red Green Blue RGB colors are detected by different pixels Blue Green Red RGB colors are detected by the same pixel Blue Green Red Mosaic three images Blue Green Red Complete three images Pixel size (µm) Fig. 11. Average E versus pixel size as technology scales (estimated at 000) [9]. column read line column reset line P HAD row address line M1 M4 N M M3 N + N + FD M signal line Fig. 13. [14]. X3 photodiode structure Incident light n lightly doped drain p-well n-well p-substrate Blue photo collection Green photo collection Red photo collection 0. µm 0.6 µm.0 µm Sensing scheme and photodiode structure of X3 HAD M1 FD Fig. 1. Buried photodiode structure with a transfer gate and a floating diffusion region [13]. Fig. 14. VMIS pixel structure [16]. CSF(Contrast Sensitivity Function) E E CMOS CMOS 0. µm 1996 µm CMOS µm CMOS Fig (3 µm ) CMOS µm 4 µm CMOS [13] [17] µm CMOS [18] [0] (Fig.6) 004 vs. CMOS CMOS CMOS.1 CMOS CMOS 000 CMOS CMOS CMOS [13] Fig.4(b) CMOS APS CMOS APS S/N 00 CMOS 4 µm CMOS Fig.(b) PD CMOS

6 (a) conventional structure <10% PD amp. PD circuit 30% (b) new structure amp. circuit Fig µm-pitch pixel layout: (a) the conventional structure (see Fig.7(a)), (b) a new structure. CMOS X3 [14, 1] VMIS [16, 17] CMOS X3 Fig.13 3 RGB VMIS Fig.14 p+ (Hole Pocket) 0% 4. µm 00. CMOS 3 µm Fig Canon ( ) Sony 3 Fig.1.8 µm 30% Fig.16 νmaicovicon [19] CMOS CMOS Fig. 16. Pixel structure [19, 1]. Fig. 17. Fill factor as a function of the number of transistors per pixel [19, 1]. CMOS CMOS MOS XY νmaicovicon Dynastron CMOS CMOS CMOS Fig.16 4 FD [19] 0. µm. µm % (Fig.6, Fig.7, Fig.1 ) Fig.17.µm 1 4 % % 6

7 (a) reference level detection (b) signal level detection (c) timing diagram Fig. 18. Readout operation diagram [19, 1]. (a) structure diagram (a) chip microphotograph (b) sample image Fig. 1. Chip microphotograph and sample image [19, 1]. (b) potential diagram Table 1. Chip specifications [19]. Pixel size. µm. µm Optical format 1/4 inch The number of pixels 1616 (H) 117 (V) = M Transistors per pixel 1.7 Fill factor % Saturation 000 electrons Sensitivity 3800 electrons/lx s Frame rate 1 frames/s Image lag No image lag Power supply voltage. V 6 CMOS APS Fig. 19. Device structure [19, 1]. Pixel pitch (µm) 4 3 Target.80µm new CMOS APS.µm Year Fig.. Leading-edge trend of pixel pitch of and CMOS APS. Fig. 0. Potential diagram of a readout part [19, 1]. Fig.18 4 OFF CDS ON FD Fig.19. V 60% P Fig.0 60% FD Fig.1 1/4 (30 µm 640 µm) 00 Table 1 6 vs. CMOS CMOS (Fig.6) CMOS Fig.6. µm µm 004 CMOS 7

8 Table. Comparison among the latest and scheduled products of and CMOS imagers [7]. Types Pixel reso. Pixel pitch Min. lux. Power Commercial production Matsushita CMOS M.8 µm lx (7. fps).9 V Mar. 004 Sony CMOS M.9 µm lx (1 fps).7/1.8 V 3rd Qtr of 004 Toshiba CMOS 1.3 M 3.3 µm lx.8/1. V nd Qtr of 004 Renesas Tech. CMOS 1.3 M 3.8 µm.8/1.8 V 3rd Qtr of 004 Micron Tech. CMOS 1.3 M 3.6 µm 3 lx. 3.1 V Now available Sony 1.3 M 3.1 µm lx (1 fps) 1.//3/ 6. V Mar. 003 Sharp M 3. µm lx ( fps) 1 8 V Dec. 003 Sanyo 1 M.7 µm.9 V Aug. 004 Fuji Film 1 M lx 3.. V Oct. 003 / CMOS [] Table CMOS 100 CMOS CMOS CMOS 7 vs. CMOS CMOS CMOS CMOS CMOS CMOS CMOS [1] 003, No. 840, BP. [] G. P. Weckler, Operation of p-n junction photodetectors in a photon flux integration mode, IEEE J. Solid-State Circuits, vol. SC, pp. 6 73, [3] W. S. Boyle and G. E. Smith, Charge-coupled semiconductor devices, Bell Systems Technical Journal, vol. 49, pp , 1970 [4] E. R. Fossum, Active Pixel Sensors: Are s Dinosaurs?, in Proc. SPIE, vol. 1900, pp. 14, [] 003 1, No. 11, BP. [6] SANYO NewRelease, Feb. 7, 001 ( co.jp/koho/hypertext4/010news-j/007-.html) [7] 004 4, No. 6, BP. [8] H. S. Wong, Technology and Device Scaling Considerations for CMOS Imagers, IEEE Trans. Electron Devices, vol. 43, no. 1, [9] T. Chen, P. Catrysse, A. E. Gamal, and B. Wandell, How Small Should Pixel Size Be? in Proc. SPIE, vol. 396, pp , 000. [10] G. E. Moore, Cramming More Components Onto Integrated Circuits, Electronics, vol. 38, no. 8, pp , 196. [11] D. X. Yang and A. E. Gamal, Comparative Analysis of SNR for Image Sensors with Enhanced Dynamic Range, in Proc. SPIE, vol. 3649, pp , [1] Z. Zhang and B. A. Wandell, A Spatial Extension of CIELAB for Digital Color Image Reproduction, Society for Information Display Symposium Technical Digest, vol. 7, pp , [13] K. Yonemoto and H. Sumi, A CMOS Image Sensor with a Simple Fixed-Pattern-Noise-Reduction Technology and a Hole Accumulation Diode, IEEE J. Solid-State Circuits, vol. 3. no. 1, 000. [14] Foveon Inc., [1] United States Patent,96,87 [16] T. Miida, K. Kawajiri, H. Terakago, T. Endo, T. Okazaki, S. Yamamoto, and A. Nishimura, A 1.M Pixel Imager with Localized Hole-Modulation Method, IEEE ISSCC Dig. of Tech. Papers, pp. 4 43, 00. [17] United States Patent 6,01,87 [18] H. Takahashi, M. Kinoshita, K. Morita, T. Shirai, T. Sato, T. Kimura, H. Yuzurihara, and S. Inoue, A 3.9µm Pixel Pitch VGA Format 10b Digital Image Sensor with 1.- Transistor/Pixel, IEEE ISSCC Dig. of Tech. Papers, pp , 004. [19] M. Mori, M. Katsuno, S. Kasuga, T. Murata, and T. Yamaguchi, A 1/4in M Pixel CMOS Image Sensor with 1.7 Transistor/Pixel, IEEE ISSCC Dig. of Tech. Papers, pp , 004. [0] K. Mabuchi, N. Nakamura, E. Funatsu, T. Abe, T. Umeda, T. Hoshino, R. Suzuki, and H. Sumi, CMOS Image Sensor Using a Floating Diffusion Driving Buried Photodiode, IEEE ISSCC Dig. of Tech. Papers, pp , 004. [1],,,,, 1.7 1/4 00 CMOS,, vol. 8, no. 3, pp , 004. [] 004 3, No., BP.