IT IS widely expected that CMOS image sensors would

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1 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 1, JANUARY A DPS Array With Programmable Resolution and Reconfigurable Conversion Time Amine Bermak, Senior Member, IEEE, and Yat-Fong Yung Abstract A CMOS digital pixel sensor (DPS) with programmable resolution and reconfigurable conversion time is described. The chip features a unique architecture based on the pulse width modulation (PWM) technique and operates with either an 8-b or 4-b accuracy. The 8-b conversion mode is used for high-precision imaging while the 4-b conversion mode provides a shorter conversion time and a two times increase in spatial resolution. Two quantization schemes are studied, namely, the uniform and the nonuniform time-domain quantizers, which are referred to as UQ and NUQ, respectively. It is shown that the latter scheme not only permits to linearize the nonlinear response of the PWM sensor, but also allows to significantly speed up the conversion time, particularly for wide dynamic range and low coding resolutions. A prototype of 32 32/64 32 pixels has been fabricated using 1-poly, 5-metal CMOS m n-well standard process. Power dissipation is 10 mw at DD =33 V, dynamic range is 90 db, while dark current was measured at 1 pa. The reconfiguration features of the chip have been verified experimentally. Index Terms CMOS imager, digital pixel sensor (DPS), programmable resolution. I. INTRODUCTION IT IS widely expected that CMOS image sensors would allow the realization of next-generation on-chip visual systems, ultimately associating image capture devices with intelligent processing. The aggressive device scaling found in today s CMOS technologies has opened the door to even more on-chip signal processing, allowing CMOS imagers to provide Camera-on-a-chip solutions [1]. New pixel structures, incorporating even digital conversion at the pixel level, have emerged, thus leading to the digital pixel sensor (DPS) concept. A particularly interesting processing which was widely reported in the literature is the multiresolution image acquisition [2], [3]. Traditionally, multiresolution is implemented by decreasing the spatial resolution via averaging the photo-signals within a cluster of neighboring pixels to reduce the resolution to regions of interest. Multiresolution is a very important processing stage for a large number of applications such as pattern recognition, target tracking, image compression, and stereo range finding. Acquiring images at different resolutions can increase speed and processing efficiency and can reduce power and storage requirements [2]. However, it Manuscript received March 3, 2005; revised July 8, This work was supported by the Research Grant Council of Hong Kong SAR, China, under Project HKUST6148/03E. A. Bermak is with the Electrical and Electronic Engineering Department, Hong Kong University of Science and Technology, Kowloon, Hong Kong ( bermak@ieee.org). Y.-F. Yung is with PROMAX Technology, Ltd., Kowloon Tong, Hong Kong. Digital Object Identifier /TVLSI is surprising to note that the multiresolution concept has been assigned by default to the spatial resolution, and, to the best of our knowledge, no prior research work has addressed the multiresolution concept from a coding resolution point of view. Typically, CMOS imagers produce a fixed 8 12 b of brightness information using array-level [4], column-level [5], or pixel-level analog-to-digital converter (ADC) [6], regardless of the application requirements. However, it should be noticed that different applications are very likely to require different coding and spatial resolutions as well as frame rates. In addition, natural light levels can vary by over eight orders of magnitude [7], and producing wide-dynamic-range CMOS imagers is quite challenging. One interesting way to improve the dynamic range of CMOS imagers is to employ time-based conversion using self-resetting architectures based on either a pulse-frequency modulation (PFM) scheme [8] [10] or pulse-width modulation (PWM) scheme [11], [12]. The self-resetting scheme improves the dynamic range by recycling the well such that higher photocurrents are detected. The output takes the form of a series of spikes, resulting in the so-called spiking pixel [9], which is of particular interest when mimicking the processes of biological vision [10]. This method presents several issues when dealing with high-resolution pixel arrays mainly related to the need for a complex bus-arbitration system, termed address event representation (AER), and the temporal jitter due to the collision problem in the output bus which affects the SNR. In addition, the synchronous self-resetting scheme suffers from higher dynamic power consumption as the pixel is constantly allowed to fire whenever it reaches a threshold voltage. Therefore, the power consumption of a large array of free-running pixels can be very significant. In this paper, we propose to implement a CMOS DPS with programmable coding (4/8-b) and spatial resolution using the PWM technique. A single digital pulse is used to sense the photocurrent, which is then encoded with either 8- or 4-b accuracy. This is greatly beneficial, particularly for exploiting the CMOS imager for various problems with different precision requirements. The 8-b conversion mode is used for high-precision imaging while the 4-b conversion mode provides a reduced conversion time and a two times increase in spatial resolution. This reconfiguration concept makes the imager a general-purpose camera-on-chip which can fulfill either high-frame-rate requirement (motion detection applications) or higher accuracy image capture (still camera applications). As the on-pixel ADC is based on the time-encoding concept, a number of additional benefits are featured in our design, such as wide dynamic range (90 db) and low power consumption, as compared to the spiking pixel architecture. The remainder of the paper is organized as /$ IEEE

2 16 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 1, JANUARY 2006 Fig. 1. Pixel block diagram. Timing diagram. SI, V, Out, and AR are the start integration, the photodiode node voltage, the comparator output, and the asynchronous reset, respectively. follows. Section II describes the pixel circuit and its operating principle and timing. Section III describes the chip architecture and the read-out circuitry. The characterization and experimental results as well as sample images obtained at different configurations are described in Section IV. Section V concludes this study. II. PIXEL DESCRIPTION AND ANALYSIS A. Principle of Operation Fig. 1 illustrates the principle of a PWM DPS. Each pixel, as shown in Fig. 1, is composed of a photosensitive device (reverse-biased photodiode ) with its internal capacitance, a reset transistor, a comparator, and a feedback circuit. In contrast to conventional pixels, our architecture uses a start integration signal (SI) which enables the start of the integration phase. The SI pulse turns on transistor M12, hence, switching off the reset transistor. The light falling onto the photodiode discharges, resulting in a decreasing voltage across the photodiode node. Once the voltage reaches a reference voltage, the output of the comparator switches. This will turn on transistor M13, allowing the pixel to asynchronously self-reset. This asynchronous self-reset is achieved through the reset circuit consisting of transistors, and. The pixels start to integrate at the same time but are recharged asynchronously, so a large recharge peak current encountered in a synchronous reset is avoided in our proposed scheme. The discharge time of the photodiode from an initial reset voltage to the reference voltage is represented by the active low pulse shown in the bottom figure of Fig. 1. The width of the active low pulse can be expressed by (1) where represents the discharge time of the capacitor from to and is the photocurrent. The capacitance can be expressed as, where, and are the photodiode capacitance, the gate capacitance of, and the diffusion capacitance of, respectively. The total capacitance is mainly dominated by as the photodiode occupies an area of about 250 m, which is chosen in order to keep the fill factor to a reasonable level. The obtained pulse width is inversely proportional to the photocurrent, as described by (1). This relationship between the photocurrent and conversion time, as illustrated in Fig. 2, results in a nonuniform pixel response of the PWM sensor. Fig. 1 shows the corresponding waveforms obtained from a PWM pixel. represents the voltage of the photodiode node for two different illuminations ( and corresponding to high and low illuminations, respectively). Out represents the output of the comparator while is the reset signal generated asynchronously from each pixel, which is responsible for self-resetting the sensor. and are examples of the pulse width for the two different levels of illumination. The interesting fact about this PWM coding scheme is that the illumination received by each pixel is coded using a single pulse. This represents a major advantage as switching activity is reduced to only a single transition in each frame for each pixel, thus allowing for lower power consumption and reduced switching noise when compared to the spiking pixel. In order to convert the PWM signal into a digital code, the Out pulse, which marks the end of the conversion, is used to trigger the writing of a time stamp from the global data bus into the pixel-level memory. This time stamp is generated using a global timer circuit, which, in fact, provides the quantization boundaries used in our time-to-digital conversion assuming a dynamic range.two quantization approaches will be illustrated in this paper. The first approach, which is referred to as uniform quantization (UQ), relies on uniformly sampling the time domain from to,

3 BERMAK AND YUNG: DPS ARRAY WITH PROGRAMMABLE RESOLUTION AND RECONFIGURABLE CONVERSION TIME 17 Equation (3) suggests that, in the UQ scheme and for a fixed, it is reasonable to assume that the conversion time is constant and independent of the dynamic range (i.e., ) as long as. It is clear from (3) and Fig. 2 that the saving of the UQ scheme in terms of conversion time is less than 50%, even when using 1- instead of 8-b precision. Let s now examine the conversion time for the NUQ case. The latter can be written as (4) where and are the current quantization step and the number of bits, respectively. Assuming that the PWM sensor is being operated in a wide-dynamic-range environment using a limited number of bits, it is reasonable to assume that. In contrast to the UQ scheme, (4) suggests that, in the NUQ scheme, greater savings in terms of conversion time is obtained when using lower precision, particularly when the sensor is operated in a wide-dynamic-range environment and using a limited number of bits. In order to compare the conversion time of the two conversion schemes, we can express the NUQ-to-UQ conversion time ratio by Fig. 2. Uniform time-domain quantizer (UQ) and nonuniform time-domain quantizer (NUQ) schemes. as shown in Fig. 2, while, in a second approach, the quantization times are chosen such that the resolved photocurrent is uniformly sampled. This results in a nonuniform time-domain quantization (NUQ), as shown in Fig. 2. In this NUQ scheme, the nonlinear pixel response described by (1) is overcome using a nonuniform time-domain quantizer. The latter can be implemented using a digital timing circuit providing the nonuniform quantization levels. B. Conversion Time Analysis For both UQ and NUQ, the digital code is updated at each quantization level obtained in the time domain. The conversion time is therefore defined by the time required to reach the last quantization level. At this point in time, all digital codes have been allocated, and the frame cycle will start again by triggering the start integration signal SI [Fig. 1]. Fig. 2 shows the distribution of the quantization levels for both UQ and NUQ using both 1- and 2-b precisions. The conversion time of the UQ, as shown in Fig. 2, can be expressed as (2) Equation (5) can be rewritten as For and,wehave suggesting that is always lower than 1. As a consequence, the conversion time of a NUQ is always shorter than that of a UQ. In addition, (6) suggests that the NUQ scheme achieves even shorter conversion time when, which is satisfied when The condition illustrated by (8) is well satisfied for higher dynamic range and lower coding accuracy (small ). This result is confirmed by the simulation results of Fig. 3, which shows that the effectiveness of the NUQ scheme in reducing the conversion time is more evident for higher dynamic range (higher values of ) combined with lower coding accuracy (small values of ). Fig. 3 shows a plot of the NUQ and UQ conversion times for, and, respectively. (5) (6) (7) (8), (2) can be approxi- Assuming that mated as (3) III. VLSI ARCHITECTURE A. Pixel Architecture From the previous discussion, we concluded that reducing the precision is very effective in speeding up the conversion process

4 18 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 1, JANUARY 2006 Fig. 3. NUQ-to-UQ conversion time ratio in log scale as function of the number of bits (n = 1...8)and x = I =I represented in log scale. NUQ and UQ conversion time as function of the number of bits for x =10 ; 10, and 10, respectively (two, four, and six decades of dynamic range). Fig. 4. Schematic and layout of the 4/8-b reconfigurable pixel. The pixel occupies an area of 50 m2 50 m and a fill-factor of 20%. using the NUQ scheme. However, using lower precision can result in inefficient exploitation of the hardware resources, as only a fraction of the on-pixel memory will be used. In order to overcome this problem, our approach relies on a 2 4-b reconfigurable DPS, as shown in Fig. 4. Each pixel includes two photodiodes, two comparators, a select mode transistor,two reset circuits, and an 8-b memory, which allows the data to be randomly and repeatedly accessed. The proposed image sensor can be configured in two modes. Mode 1: 8-b conversion In this mode, the two photodiodes are combined as a single photodetector by switching on. The second comparator, COMP2, is disabled to reduce power consumption. In this scheme, the pixel will be configured as a single 8-b pixel. Mode 2: 4-b conversion In this mode, is switched off and COMP2 is enabled, such that there are two photodiodes and two comparators operating in parallel in each pixel. The pixel is therefore configured as two spatially independent pixels operating in parallel and each uses half of the 8-b memory. In this mode, the horizontal resolution of the array is doubled while keeping a high frame rate. This configuration allows to effectively utilize the hard-

5 BERMAK AND YUNG: DPS ARRAY WITH PROGRAMMABLE RESOLUTION AND RECONFIGURABLE CONVERSION TIME 19 Fig. 5. Architecture and layout of the reconfigurable spatial/coding resolution CMOS imager. The chip occupies an area of 2.7 mm mm. ware resources and improve the conversion speed particularly when using the NUQ scheme. It is important to note that, in both modes 1 and 2, the values of the photodiode node capacitance (and hence ) as well as the photocurrent are not the same. As an approximation, we can assume that both the photocurrent and the capacitance values are doubled when moving from 4- to 8-b precision, mainly because the capacitances are dominated by the large photodetector area of our DPS (2 250 m ). This will result in a constant pulse width, and, therefore, our theoretical analysis of the conversion time still holds. Fig. 4 shows the layout of the reconfigurable pixel. The floorplan is optimized in order to increase the spatial resolution of the imager in either column or row directions. It should be noticed that the same concept can be used to increase the spatial resolution in both column and row directions, even though the layout will be much more complex as this will require a fourpixel layout. Work is underway in order to improve the floorplanning and to exploit this multiresolution concept row- and column-wise. The reconfigurable DPS occupies an area of 50 m 50 m, with a fill-factor of 20%. B. Imager Architecture and Layout The architecture of the 4/8-b programmable resolution CMOS image sensor is shown in Fig. 5. It includes a reconfigurable 32 32/64 32 pixel array, and a control circuit which implements the NUQ scheme. Column and row decoders are used for scanning out the memory data through a sensing amplifier. Data are generated by the control circuit and distributed to all of the pixels through the data bus during the conversion phase. Global signals, such as start integration (SI) and 4/8-b mode selection signal, are also transmitted to the pixel array through global bit lines. During the readout phase, pixel contents are scanned out using on-chip row and column counters as well as column and row decoders implemented within the pixel pitch. Sensing amplifiers placed at the periphery of the imager are used to increase the read-out speed. The image sensor was implemented in m CMOS technology. Fig. 5 shows the microphotograph of the chip and illustrates the floorplan of the design. The chip occupies an area of 2.7 mm 2.3 mm with more than 85% of the chip area dedicated to the pixel array. The control circuit, including the NUQ, occupies only a very small part of the chip (140 m 450 m). C. NUQ Circuit Fig. 6 shows the block diagram and the corresponding layout of the control circuit used in our CMOS imager. The blanking circuit is used in order to set the lower bound of the dynamic range (i.e., ) by disabling the clock initially in order to disable the counting for. The upper bound of the dynamic range is set using the clock frequency of the primary clock. A lower clock frequency permits to extend the upper range of the dynamic (i.e., ) but at the expense of the conversion resolution. A multiplexer is used in order to switch between both NUQ and UQ modes. In the UQ mode, uniform quantization levels are obtained using a uniform clock signal, which constitutes the clock input for the 8-b Gray counter. The same counter can be triggered by a second clock referred to as used to obtain the NUQ levels described in Fig. 2. The uniform clock signal drives a frequency divider circuit, which was constructed from a 16-b counter, a comparator, and a lookup table (LUT). The 16-b counter increments until the count is equal to the LUT divisor value, when it will reset, and generates a clock pulse for the Gray counter. The output from the Gray counter is fed

6 20 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 1, JANUARY 2006 Fig. 6. Circuit diagram and layout of the control circuit realizing the NUQ scheme. back to the frequency divider, as an address input to the LUT. The values necessary to obtain the NUQ levels are obtained analytically [see (1) and Fig. 2] and stored into the LUT. The dynamic range of the sensor is set by externally tuning the frequency of the uniform clock signal and the blanking time. The data bus signals are buffered and distributed to the pixel array. Before they are routed to the pixel array, the data signals undergo a signal multiplexing circuit which allows to configure the data bus as a single 8-b data bus or two parallel 4-b buses, depending on the mode signal. Gray code is used in order to reduce switching activity and hence to lower power consumption. IV. EXPERIMENTAL RESULTS In order to test the different building blocks of the imager, a modular test strategy was adopted. Test structures were added in order to test separately each block within the DPS. Each test structure permits to separately test the signal path at a given stage. An electro-optical experimental setup was developed in order to characterize the sensor array. The electrical part consists of a PCB on which the device under test (DUT) is mounted. Control signals required for the DUT are provided through the National Instrument Data Acquisition board. The 8-b digital output of the DUT is captured and used to display the grabbed frame on the PC. A single clock signal is used to generate internally all of the timing control required for the chip, and hence no control circuit is required and the chip is fully operational without extra hardware. The optical part of the setup consists of a light source and an integrating sphere, which are used to provide uniform illumination to the sensor array. First, the functionality and the sensor response were tested by placing the sensor Fig. 7. Pulse width as function of illumination for 4- and 8-b accuracy. The linear data fitting is based on minimizing the mean square error function. very close to the integrating sphere, and the light intensity provided by the light source was measured. The experiment was repeated for different light intensities. Fig. 7 shows the active low pulse-width values for almost five decades of illuminations and for both 4- and 8-b accuracy. The relationship is confirmed through the linear response in the log log plot for both modes of operation. The lower limit is theoretically set by the dark current measured at 1 pa. The maximum available intensity level used in our experimental setup did not bring the sensor to saturation and more than 90 db operating range was still achievable. Fig. 8 (top) reports the asynchronous self-reset (AR) signal measured experimentally. The active low signal corresponds to the PWM signal.

7 BERMAK AND YUNG: DPS ARRAY WITH PROGRAMMABLE RESOLUTION AND RECONFIGURABLE CONVERSION TIME 21 Fig. 8. Top: PWM signal for 10 lux illumination. Bottom: LSB of the data bus in the NUQ scheme. TABLE I SUMMARY OF THE CHIP FEATURES Fig. 9. Spectral response of the sensor. Fig. 8 (bottom) shows the data bit in the NUQ scheme. The figure illustrates the successful operation of the nonuniform clocking of the Gray counter needed for the NUQ scheme. Fig. 9 shows the measured spectral response of the sensor. For this measurement, a monochrometer with a calibrated light source was employed and a sweep of 25 nm was applied. The obtained response confirm the expected visible range. Using a light source and an integrating sphere, the fixed pattern noise (FPN) was analyzed for both accuracies. The values obtained for the flat field images were summed and averaged for the two configurations (4- and 8-b). The mismatch between pixels was evaluated for a fixed mv and was around 0.8% for both configurations. The power dissipation was observed to be Fig. 10. Sample images from the reconfigurable CMOS imager. The top row of images correspond to images acquired at 8-b accuracy and spatial resolution. The figures shown in the two bottom rows were captured with 4-b accuracy and spatial resolution. 10 mw at 3.3 V. It should be noticed that the chip was successfully tested at a power supply of 2.5 V. Table I summarizes the performance of the imager. The figures related to power, FPN,

8 22 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 1, JANUARY 2006 and dark current are taken as the worse case scenario for both configurations. Fig. 10 reports some sample images acquired for both modes of operation. V. CONCLUSION A reconfigurable spatial and coding resolution CMOS imager based on PWM and asynchronous self-reset schemes was presented. The proposed architecture is based on an SI signal instead of a global reset signal, avoiding large peak currents, using a three-transistor reset circuit. The CMOS imager can operate with either 8- or 4-b conversion modes using two possible quantization schemes, namely, the UQ and NUQ. The two schemes were thoroughly analyzed by comparing their respective conversion times for different dynamic range and precision requirements. It was found that the NUQ scheme not only linearizes the pixel response but also permits to shorten the conversion time as compared to its UQ counterpart. It was also demonstrated that the effectiveness of the NUQ in reducing the conversion time is more evident for higher dynamic range combined with lower coding accuracy. However, using lower precision can result in inefficient exploitation of the hardware resources, as only a fraction of the on-pixel memory of the DPS is used. In order to overcome this problem, we proposed a unique DPS architecture in which both coding and spatial resolutions are configured. The image sensor, including a reconfigurable 32 32/64 32 pixel array, was implemented in m CMOS technology. Each pixel occupies an area of 50 m 50 m and presents a fill-factor of 20%. REFERENCES [1] E. Fossum, CMOS image sensors: Electronic camera-on-chip, IEEE Trans. Electron Devices, vol. 44, no. 10, pp , Oct [2] S. E. Kemeny, R. Panicacci, B. Pain, L. Matthies, and E. Fossum, Multiresolution image sensor, IEEE Trans. Circuits Syst. Video Technol., vol. 7, no. 4, pp , Aug [3] Z. Zhou, B. Pain, and E. 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Streil, and A. Konig, An HDR CMOS image sensor with spiking pixels, pixel-level ADC, and linear characteristics, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 2, pp , Feb [10] E. Culurciello, R. Etienne-Cummings, and K. A. Boahen, A biomorphic digital image sensor, IEEE J. Solid-State Circuits, vol. 38, no. 2, pp , Feb [11] X. Qi, X. Guo, and J. G. Harris, A Time-to-first spike CMOS imager, in Proc. ISCAS, vol. 4, 2004, pp [12] A. Kitchen, A. Bermak, and A. Bouzerdoum, PWM digital pixel sensor based on asynchronous self-resetting scheme, IEEE Electron Device Lett., vol. 25, no. 7, pp , Jul Amine Bermak (M 99 SM 04) received the M.Eng. and Ph.D. degrees in electronic engineering from Paul Sabatier University, Toulouse, France, in 1994 and 1998, respectively. While completing his doctoral work, he was part of the Microsystems and Microstructures Research Group, French National Research Center LAAS-CNRS, where he developed a three-dimensional VLSI chip for artificial neural network classification and detection applications. He joined the Advanced Computer Architecture Research Group, York University, York, U.K., where he was a Postdoctoral Researcher working on VLSI implementation of a CMM neural network for vision applications in a project funded by British Aerospace. In November 1998, he joined Edith Cowan University, Perth, Australia, first as a Research Fellow, working on smart vision sensors, and then as a Lecturer and a Senior Lecturer with the School of Engineering and Mathematics. He is currently an Assistant Professor with the Electrical and Electronic Engineering Department, Hong Kong University of Science and Technology (HKUST), Kowloon, where he is also serving as the Associate Director of the Computer Engineering Programme. His research interests are related to VLSI circuits and systems for signal, image processing, sensors, and microsystems applications. He has published extensively on the above topics in various journals, book chapters, and refereed international conferences. Dr. Bermak was the recipient of the Bechtel Foundation Engineering Teaching Excellence Award and the IEEE Chester Sall Award in Yat-Fong Yung received the B.S. and M.Phil. degrees in electronic engineering from Hong Kong University of Science and Technology, Kowloon, in 2002 and 2004, respectively. He is currently an IC Design Engineer with PROMAX Technology, Ltd., Hong Kong. His interests are in mixed-ic design for CMOS imagers and vision sensors.