Element InSb Detector with Digital Processor

Transcription

1 Element InSb Detector with Digital Processor O. Nesher, S. Elkind, I. Nevo, T. Markovitz, A. Ganany, A. B. Marhashev, and M. Ben-Ezra a Semi Conductor Devices (SCD), P.O. Box 2250, Haifa 31021, Israel a Israeli MOD, MAFAT, Optronics, Tel-Aviv 63734, Israel ABSTRACT After completing the development of a digital detector with a format of elements ("Sebastian"), SCD is now developing a mid format digital detector with elements. This detector is based on the same concept as Sebastian, which was introduced last year at the SPIE conference in Orlando. The element detector has all the features and performance of Sebastian as then introduced, and in addition exhibits some additional functionality. The format of the element detector was chosen in order to maintain the same active area as in a standard format element detector of today. Thus with specific system optics, a higher resolution is achieved with our new detector. As a direct consequence, the detection range is increased by 22-35% depending on the target type, when using this detector instead of the conventional element detector in a typical system. The element detector is designed to be integrated both into imaging systems and into head seekers missile-applications. In this paper we present the concept and the basic structure of the detector, the special operation modes unique to the digital detector, and the results of detection range calculations. Keywords: Digital Detector, element detector, Focal Plane Array, Digital Focal Plane Processor, FPGA, IR detector, InSb detector, 15 bit digital video. INTRODUCTION During 2003 SCD completed the development of the first detector which is based on a digital signal processor on the Focal Plane Array (FPA) itself 1, 2. The main challenge in designing a high performance signal processor for a cooled IR detector with digital output was to maintain power consumption similar to that in an analogue processor. Predictions showed that the conventional design for analogue to digital conversion (ADC) results in power consumption over 1Watt under the operation conditions of a standard IR detector 3, 4. However, the special design at SCD of the ADC and the whole signal processor has resulted in a power consumption of the digital signal processor which is even lower compared to existing analogue processors 1, 2. Detectors based on a digital FPA are considered to be very attractive due to their many advantages over detectors with an analogue FPA, which are expressed especially on the system level. These include: Lower level of readout noise due to immunity of the analogue signal to external noise Higher linearity Less sensitivity to external ambient conditions Higher long term stability of the Residual Non Uniformity (RNU) Removal of the requirement to develop low noise electronics in the system The distance between the detector and the system electronics can be increased up to several meters without affecting the performance The integration of the detector into the system is much simpler and faster Last year at the SPIE conference at Orlando SCD introduced for the first time the fully integrated element digital detector (Sebastian) with its measured performance 2. All the above advantages of the digital detector were demonstrated by the performance measured on the Sebastian detector. The measurements of the detector showed a high linearity of 0.01% with Residual Non Uniformity of 0.015% over a range of 2-90%, and with both spatial and temporal NETD of 10mK together with high RNU stability. In this paper we present the second digital detector after the Sebastian, with elements for the mid format, currently under development at SCD and based on Sebastian. First the general structure of the signal processor and its

2 main features are described. Then, the performance of the detector is calculated on the system level and is compared to a standard analog element detector. It shows a significant improvement in recognition range for the digital detector. Next, special integration modes implemented in the detector for large dynamic range with high sensitivity will be discussed. Finally, results of frame to frame mode transition measurements are presented. GENERAL DESCRIPTION OF THE DIGITAL DETECTOR The Digital Focal Plane Processor (DFPP) is fabricated with a 0.5 micron double-poly, triple metal CMOS process and it consists of 4.5 million transistors. It is designed to work with Indium-Antimonide (InSb) and related diodes and for snapshot mode operation. The DFPP is connected to proximity electronics that contain a FPGA component, which controls its operation and samples the output data from the DFPP and processes it. Signal processor structure The DFPP consists of the following parts as described schematically in figure 1: Pixel cells Integrate the photo-currents generated in the detector pixels. A/D Converters Two rows of 15-bits A/D converters exist, providing two A/Ds per column. One row above the active matrix, and one row below it. Thus, at each given time during the Frame-Read process, two rows are converted (while the two rows that were previously converted are read-out). Row Shift Register Responsible for the connection of the proper rows of the matrix to the A/D converters. Column Shift Register and Readout Circuitry Multiplexing the digital data from the A/D converters and sending them out. Frame-Timing This circuitry advances the A/D converters and the shift registers mentioned above, through their operation states. The Frame-Timing is fully controlled by the FPGA. Communication The DFPP is rich with features and possibilities. All the operation modes are controlled by the FPGA via a serial communication channel, transferring a long communication word. Figure 1: Block diagram of the DFPP

3 Digital Detector structure Unlike other focal plane processors, there is no internal correlation between the integration and the frame-read procedures in the DFPP. These functions are fully controlled separately by the FPGA, residing in the proximity card. The DFPP is designed as an open system, meaning that the controller of the frame states and the integration activities is not a part of the DFPP. On the other hand, the control of the DFPP and the interface to it is quite complicated. Therefore the proximity card contains a FPGA which functions as the controller of the DFPP and as the arbitrator between the system and the DFPP. The combination of the DFPP-FPGA makes a universal system, where the FPGA can be programmed specifically for each application. The relationship between the System, FPGA, and DFPP is described schematically in figure 2. As mentioned above, the DFPP is operated directly by the FPGA, with a local oscillator on the proximity card. Therefore there is no need for the system to handle the timing requirements of the frame-read sequence and the diversity of the parameters. The readout data from the DFPP are collected, preprocessed and arranged sequentially by the FPGA before it is transferred to the system. Because of the diversity of modes and features and since each application requires different settings and ways of operation, the definition and characterization of the system requirements are done at SCD, in advance. Thus the FPGA is programmed accordingly, with the proper parameters and the user receives a Detector-Module that is specifically tailored to his needs. In most cases these parameters are constant in the FPGA and do not need to be changed. In more complicated applications, some parameters may change dynamically by external intervention. The communication between the system and the FPGA is simple and deals just with the topics that are of system interest, like cycle rate, integration time, window, etc. The interface between the FPGA and the system can either be standard (e.g. Camera link), or specific as per system requirements. Figure 2: Block diagram of System-Proxy-Detector Main features The conversion resolution of the detector can be controlled externally, up to 15 bits. There is a tradeoff between the A/D resolution and the maximum frame rate achievable. For example: with a 15 bit resolution the detector can operate at a maximum frame rate of 165Hz with full window, whereas at 13 bit resolution the detector can operate at 200Hz with a full window. The pixel unit can store up to 14Me-. Five different variable gains are available with a full range of: 1Me-, 3Me-, 7Me-, 10Me- or 14Me-. An anti-blooming feature was designed to avoid a very strong light source from disrupting the operation of the detector. The saturation level of the input stage at the DFPP can be controlled gradually by the FPGA. Using this feature, the performance of the detector can be optimized to the level of photocurrent. A dilution in rows readout (reading every 2 nd or 6 th row) enables the user to increase the frame rate. In addition there is an option of joining every two adjacent pixels in rows or columns (achieving large size pixels), or joining every four adjacent pixels (quadruple pixel). Operating the readout dilution together with the pixel merging enables the operation of the detector at high frame rate with a higher signal to noise ratio per pixel. The number of the data output lines from the

4 Dewar can be changed according to the maximum frame rate, 16 outputs for 200Hz, 8 outputs for 100Hz and 4 outputs for 50Hz at 13 bit resolution. The following modes can be changed on-line: Window dimensions and location. Readout direction (Up or down, left or right) IWR or ITR or any other combined integration modes. Pixels readout dilution. Pixels unification: every two horizontally, every two vertically, or four adjacent pixels. Optimization of digital resolution with frame rate. One of five gain values. Optimization of the power dissipation vs. frame rate. Anti blooming operation. One of ten different bias operating points for the InSb diode: from 50pA to 1nA Basic performance The measured radiometric performance of the Sebastian detector was reported elswere 2. Briefly, the deviation from linearity over a regime of 2-90% well fill capacity is below 0.01% of the full range. A direct outcome of this high linearity is a Residual Non Uniformity (RNU) of less than 0.05% STD/DR for a range of 2-90% well fill capacity. In the digital detector a linear relationship between the noise and the signal was measured, meaning that the signal sampling inside the signal processor is very clean. An NETD of 10.5mK was measured at 50% well fill capacity with a black body temperature of 25 C, meaning that a similar value of 10mK is achieved for the spatial and the temporal noise in the digital detector. This demonstrates the great advantage of systems using SCD's digital detector, where the detector performance is not limited by the spatial noise. SPECIAL ASPECTS OF THE FORMAT Lately there is a growing need to improve the resolution of systems in order to improve their performance but to maintain the same detection area as current detectors. For the next generation of SCD mid format digital detectors, a format of elements was chosen. The format was chosen in order to maintain the same detector dimensions and active area (Field Of View) as today's standard mid format of Any other formats such as or can be derived immediately from the detector. This new format together with the performance of the digital detector can improve significantly the performance of the system compared to an analogue detector with elements. In order to illustrate the differences between digital detector with elements and the analog detector with the elements, we performed calculations at the system level. All these calculation were carried out with TRM3 simulation model. For these calculations we assume a system with objective lens of 65mm diameter, F/3.8 and a focal length of 250mm, resulting in a field of view of Other parameters used for the calculations: optical transmittance of 0.8, Optics MTF quality factor of 1.15, a good display with 1000 TVL and an atmospheric transmittance of 0.85Km -1. Two targets were used for recognition calculations: a NATO tank target of 2.3m 2.3m with a temperature difference of 1.25 C between the target and the background, and a human target with a size of 1.5m 0.5m and a temperature difference of 5 C between the target and the background. For the analog element detector an excess current of 30pA (the sum of the stray and the dark current), a system readout noise of 2000e- and a system RNU of 30mK were used. For a 60Hz frame rate with a temperature background of 23 C and 10msec integration time (integration capacity limited), a system NETD of 20mK was used. For a system based on this detector, recognition ranges of 4.4Km for the tank target and 2.3Km for the human target were calculated. For the digital detector with elements with exactly the same FOV, an excess current of 15pA, a system readout noise of 1000e- and RNU of 10mK were used 2. For a 60Hz frame rate with a temperature background of 23 C and 10msec integration time (integration capacity limited), a system NETD of 15mK was used. It is important to note that this value of 15mK NETD was measured in systems into which Sebastian has been integrated. For a system based on this detector, recognition ranges of 5.3Km for the tank target and 3.1Km for the human target were calculated. These calculation results show improvements of 22% for the tank recognition range and 35% for the human recognition range, respectively, due to the digital detector. The improvement in the recognition range of the tank is mainly

5 influenced, but not only by the improvement of the system NETD, whereas the improvement in the human recognition range is mainly due to the improvement of the resolution and the spatial noise. SPECIAL INTEGRATION MODES At the past few years there is a growing need for applications which related to Missile Warning Systems (MWS) and Muzzle Flash Detection System (MFDS) for air and ground platforms. In these systems, where the principle need is to identify the sources of threat, the main challenge today is to reduce the number of false alarms. In order to get performance with high reliability there is a need for detector that are operation with a high dynamic range and a high rate of image sampling. In our digital detector family, special integration modes were implemented inside the signal processor, enabling an operation mode, combining high dynamic range with high sensitivity, and an operation mode which combines high dynamic range with a high frame rate. In these modes the detector can also be operated with a high rate of image sampling, in order to be able to detect events of very short duration,. 1) Combined Integrate Mode High dynamic range with high sensitivity. This Mode was first implemented in the Blue Fairy detector 5 and later in the Sebastian detector. The sequence of one cycle of the Combined Mode is shown in Figure 3. Two integration pulses are used, a short and a long one for frames A and B respectively. For example Integrate-B is 8 times longer than Integrate-A. Time simultaneity between the frames can be improved by splitting the integration pulse B into two equal pulses and inserting integration pulse A in-between. Each frame is read at the end of its integration. By using the appropriate algorithm, the user can choose the best frame out of the two, or fuse two frames with the corresponding weight for each one, in order to get an image with hot and cold details together. This mode is thoroughly discussed and demonstrated in a previous article of SCD 5. Figure 3: Timing diagram for one cycle of the Combined Integrate Mode 2) Multi-step integration mode high dynamic range with high frame rate. Another operation mode enables dynamic optimization of the detector operation in one frame. This mode enables an increase of dynamic range in one frame, and thus allows higher frame rate operation compared to the combined mode. In this mode the pixel saturation level is changed according to the level of the photocurrent, together with the use of multiple integration pulses in the same frame. Such a mode with two integrations per frame, each with a long pulse and a short pulse is demonstrated in figure 4. Before each integration starts, the saturation level parameter is changed (by the communication channel) as shown in the drawing. A low Saturation level is set before the long integration pulse, and a high saturation level is set before the short integration pulse. For a low irradiated pixel, the signal will be proportional to the total integration time. For a highly irradiated pixel the signal level will be the sum of the low saturation level and the signal accumulated during the short integration with the high saturation level. Thus two ranges are used in the same frame: one with the low saturation level for the low radiant pixels and the second between the low and the high saturation levels for the high radiant pixels. For example: for the first range with the low saturation level, a background temperature up to 150 C can be detected with NETD up to 20mK, whereas for the second range a background temperature from 150 C to 800 C can be detected with NETD of 1-2 K. Using this mode the dynamic range is increased, as demonstrated in figure 4, with high frame rate. This method can be extended to more than two integration pulses per one frame together with the use of the multiple saturation levels available.

6 Figure 4: Timing diagram of Multiple-step integration mode 3. Multiple integration mode high rate image sampling As was mentioned above, the frame read and the integration events are not correlated, thus a large flexibility can be achieved in various modes of operation. As a consequence an operation mode with several integration pulses within one readout cycle can be performed. The timing diagram of such a mode is described schematically in figure 5. In this mode we overcome the limitation of the maximum readout rate of the FPA. The integration pulse is divided into many integration pulses at the required frequency (For example: 1KHz), where the total number of electrons which are collected in the integration capacitor can be controlled by the ratio between the single integration pulse and the non integrating period (duty cycle). Using this integration mode the system can have high rate sampling of the background with the ability to detect events with short time duration, and to track targets with high speed. Figure 5: Timing diagram of the multiple integration mode FRAME TO FARAME MODE CHANGES For systems that are designed to cope with high dynamics, especially in missile applications, there is a need to change operation modes during flight but the system cannot afford to lose any frame due to these mode changes. A special effort was made in the design of the detector in order to avoid unwanted effects in the following frame after changing a mode of operation. Measurements of the following four mode changes are presenting in figure 6: frame rate, DFPP gain, integration time and recovery from saturation. For these measurements a series of 90 consecutive frames was measured and the median of each frame was calculated. The measurements were made with 15 bit resolution. In the graphs the

7 median of the signal is shown as a digital level and is plotted as a function of the frame number. For all the graphs, the change of the mode was performed at frame number 45. In figure 6a a change in the gain of the signal processor is shown, from 3Me- to 6.5Me-. In figure 6b a change in the frame rate is shown, from 32Hz to 80Hz. In figure 6c a change in the integration time is shown, from 5msec to 10msec. In figure 6d a recovery from saturation is shown. One can see from all the four graphs that there is no loss of frame after the mode change is performed and that the first frame following the change is not disrupted. The only slight exception is the recovery from saturation where the first frame after the transition deviates by only 0.06% from the mean signal. Median signal (DL) Median signel (DL) Transition point Frame number Figure 6a: Gain change Frame number Figure 6b: Frame rate change Median signal (DL) Frame number Figure 6c: Integration time change Median signal (DL) Frame number Figure 6d: Recovery from saturation SUMMARY Today SCD is producing the element digital detector (Sebastian). Sebastian finished its development phase during 2003 and its performance was presented at the SPIE conference in April of that year. A few Sebastian detectors have already been integrated into some systems, and they have demonstrated excellent performance at the system level such as: Low noise level, high linearity and long term stability, as were demonstrated by the detector itself. Sebastian consists of a proximity electronics card which includes an FPGA component to provide direct operation of the signal processor and to enable the setting up of any standard interface to the system. An interface such as a camera link enables easy and fast integration of the digital detector into the system, by using standard components and software modules. Following on from Sebastian SCD is developing for the mid format, a digital IR detector with elements which has the same active area as the standard mid format of today that has elements. This detector, according to our calculations, is expected to improve the recognition range for a tank target by 22% and for a human target by 35%, in a typical system, compared to a standard analog detector with elements. The element detector is

8 integrated into our standard analog mid format dewars, including the compact "Piccolo" detector for hand-held applications 6, 7. Prototypes of the elements digital detector are expected to be ready during Special integration modes have been implemented in the signal processor which can be used for missile warning applications that require high dynamic range and a high rate of image sampling. These modes include the combined mode for high dynamic range combined with high sensitivity, the multi-step integration mode for large dynamic range combined with high frame rate, and the multiple integration mode for high rate image sampling. We show that for highly dynamic applications that require mode transitions on a frame to frame basis, there is a smooth transition after the mode change. These transitions were demonstrated with changes of gain, frame rate and integration time and also recovery from saturation. The new family of the SCD's digital detectors will all have a similar interface to the system. The generic design of the signal processor enables us to develop any other formats of digital detector such as , or , at short notice and according to any customer requirement. ACKNOWLEDGMENTS The development of digital detector was partly supported by MAFAT, Israeli Ministry of Defense. We would like to thank to all the technicians and engineers which their dedicated contribution to the development, production and characterization of the digital detector where able to achieve the breakthrough of the Sebastian. REFERENCES 1. Shimon Elkind, Amnon Adin, Itzhak Nevo and Arkady B. Marhasev, "Focal plane processor with a digital video output for InSb detectors", Proceedings of SPIE vol. 4820, Infrared Technology and Applications XXVIII Conference, July. 2002, pp O. Nesher, S. Elkind, A. Adin, I. Nevo, A. B. Yaakov, S. Raichshtain, A. B. Marhasev, A. Magner, M. Katz, T. Markovitz, D. Chen, M. Kenan A. Ganany, J. Oiknine Schlesinger and Z. Calahorra, " A Digital Cooled InSb Detector for IR Detection", proceedings of SPIE vol. 5074, Infrared Technology and Applications XXIX Conference, April. 2003, pp L. J. Kozlowski et al., "Progress towards high-performance infrared imaging system-on-a-chip", Proceedings of SPIE vol. 4130, Infrared Technology and Applications XXVI Conference, July-Aug. 2000, pp L. J. Kozlowski, M. Loose, A. Joshi, K. Vural and M. Buchin, "Low power system-on-chip FPAs", Proceedings of SPIE vol. 4820, Infrared Technology and Applications XXVIII Conference, July. 2002, pp O. Nesher, S. Elkind, A. Adin, U. Palty, O. Pelleg, E. Jacobsohn, T. Markovitz, I. Szafranek, Z. Calahorra, and J. Oiknine Schlesinger, " Performance of BF Focal Plane Array InSb Detectors ", Proceedings of SPIE vol. 4820, Infrared Technology and Applications XXVIII Conference, July. 2002, pp T. Markovitz, F. Schapiro, D. Alfiya, S. Hasson, A. Magner and O. Nesher, "Piccolo A High Performance IR Detector Optimized for Handheld Applications", proceedings of SPIE Infrared Technology and Applications XXX Conference, April Ofer Nesher, Philip C. Klipstein and Eliezer Weiss, " Advanced IR Detector Design at SCD: From D 3 C TM to ABCS", proceeding of Photonic West conference, January 2004