Long Mid-Wave Infrared Detector with Time Delayed Integration

Transcription

1 Long Mid-Wave Infrared Detector with Time Delayed Integration M. Zucker, I. Pivnik, E. Malkinson, J. Haski, T. Reiner, D. Admon, M. Keinan, M.Yassen. I. Sapiro N. Sapir and A. Fraenkel Semi Conductor Devices P.O. Box 2250, Haifa 31021, Israel ABSTRACT In this paper we present a long Infrared Detector (LIRD) with Time Delayed Integration (TDI) mechanism in the 3µm - 5µm spectral band. The detector consists of four segments that are butted on a single substrate in a staggered format. A novel butting technique ensures high accuracy and extremely uniform temperature distribution along the array. Each detector segment (DS) consists of an advanced CMOS readout integrated circuit (ROIC) attached to a back-illuminated diode array. The diode array is implemented with SCD s proprietary high performance InSb process. The ROIC is designed and optimized to be used with high F#, slow scan rate systems. Very low power dissipation is emphasized. In order to achieve high flexibility, the signal processor is externally programmable, enabling TDI operation with or without over-sampling on any combination of elements. Some other features include: Bi-directional operation, defective pixel de-selection, variable line rates and integration times, externally controlled gain and background subtraction capability. The paper presents electrical and radiometric predictions. Measured results that were performed on the first prototype are also presented. Keywords: LIRD, TDI, CMOS readout, Butting 1. INTRODUCTION The development of a 2048X16 InSb FPA, with several levels of TDI, was ordered from SCD by ELOP Electrooptics Industries for the use in their dual band LOROP camera. This camera is constructed to be used for long range whiskbroom scanning photography. SCD has been a well established supplier of high performance infrared imaging detectors based on InSb and MCT, for at least past 5 years 1. Specifically, the back Illuminated InSb technology is very mature and demonstrates excellent performance in SCD s matrix products. TDI is successfully implemented with the MCT detectors. SCD has also a long experience with dewars, cold fingers, coolers, cold shields, vacuum techniques etc. Thus, encountering the need to design a 2048 TDI lines, InSb detector array, some of the needed technologies were already available. However, the extremely large size of the FPA introduced new challenges. Due to the unavailability of such large format Si-ROIC and InSb materials, the array had to be constructed from four separate Detector Segments (DSs). A butting technique had to be developed to locate the DSs with adequate precision on a large size Aluminium Nitrid(AlN) substrate. The (AlN) substrate, on which the ROICs are located, had to be of a non standard multilayer design, to support the extensive interface between the chips and to the external connections. The large substrate had to be placed on a specially designed support that was mounted on the top of the cold finger. So, the cold finger had to be constructed rigid enough to support the weight of the Focal Plane Array (FPA), with its support, and the cold shield on the top of them. The rigidity is required to prevent blur during vibrations. A new, large, light weight, non spherical, cold shield had to be developed. The high F# induced low radiation flux. In addition, the long array imposed considerable cos 4 θ signal nonuniformity. The combination of both was manifested in extremely low photocurrents, in the range of the dark current, especially at the detector edges. In order to minimize dark current and its fluctuations, a highly uniform and stable temperature distribution was essential 2. So, all the components had to be designed to have low thermal capacitance and good heat conductivity. The cold shield also had to be designed to minimize stray radiation. Because of the notably large dimensions of the dewar, 100 mm in diameter, a new design approach, as well as new soldering technologies had to be developed. As to electronic design, unprecedented number, for CMOS realization, of TDI stages, was required. The ROIC design had to support several applications. The numerous operation modes imposed the development of a very flexible interface to control the TDI. One of the applications imposed very low power dissipation design.

2 The resulting product and some of its main components are described in the next chapter. The following chapter will present main features and design goals. Next, a brief description of focal plane technologies and ROIC design concepts will be discussed. The last chapter will present performance predictions and measurements. 2. GENERAL DESCRIPTION Figure 1 shows the detector assembly with its cooler beside it. Dewar s window is facing upward (covered). The Proximity electronics can be also seen, wrapped around the upper part of the dewar. This electronics contains peripheral analog and digital circuitry that provides all the required low noise, stable power supplies and external interfaces. The cooler is a 1.6 Watt linear, twin-piston, Stirling cryo-cooler. Figure 2 shows the dewar without its upper cover. The shape of the Cold Shield can be seen. The base of the cold shield is at the level of the focal plane. The cold filter, which is mounted on the top side of the cold shield, can be observed. Figure 3 shows the focal plane, mounted on its support, on top of the cold finger. (The support and the finger are not seen). On both sides of the FPA two interconnection blocks can be seen. The electrical interfaces from the FPA to the external output pins are passing through these blocks. Figure 4 shows the FPA in detail with the four butted DSs in staggered format on the substrate. Four temperature diode elements can be seen between the DSs. The focal plane assembly is described in more detail, later on.. Figure 1. The Detector Assembly with its cooler Figure. 2. The Dewar with its upper cover removed. compressor. Figure 3. The FPA mounted inside the Dewar Figure 4. The FPA. 2.1 Features 3. MAIN FEATURES AND PERFOMANCE - High performance 2048X16 InSb IRFPA with several levels of TDI, in the µm Spectral Range. - Optimized to be used with high F#, slow scan systems. - Extremely versatile. - Large number of TDI stages, in CMOS realization.

3 2.2 Functionality: - TDI of all detector element signals for each channel. - Multiplexing of 2080 (2048 effective) channels through 8 video lines. - Over-sample & non-over-sample operation capability - Direction selection capability - Number of operating stages selection capability - Defective pixels de-selection capability - Variable integration time and line rate capability - Gain variation (4 steps) - Background Subtraction (BS) capability. - Embedded testability provisions 2.3 Performance: Typical performance is given in Table 1. The Design goals were set to ensure meeting the performance requirements. Table 1 Typical performance parameter Typical Value Comments Line Rate Up to 20,000 lines/sec Scan efficiency high rates Effective Output Span 3 0.1, 0.5pF integration capacitors Dynamic Range > 5000:1 Effective Output Span / Floor Readout Noise Video Output Frequency 5 MHz Per one output, out of 8. Integration Time ~1us to (Tl-Tt) Tl = 1/Line Rate, Tt = Transfers time D * (peak) 4*10 12 T int = 500µsec, 300K Background, full level TDI NETD (typical values) T int = 500µsec, 300K Background, full level TDI RNU (σ/effective Output Span) < 0.1% Responsivity Non-Uniformity < 3 % (σ/mean) Typical, uncorrected Operability > 99.5% D * > 0.5*D * (avg) Max. Charge Capacity Max. BS Gain Levels 18 Me 44Me 4 Levels Over Sampling Rate 2 In over-sample mode Readout Noise pF Full level TDI with over-sampling Cross-talk < 0.5% To nearest neighbor Power Dissipation < 100 2kHz line rate, all four ROIC s

4 4. THE FOCAL PLANE ARRAY STRUCTURE AND TECHNOLOGIES 4.1 FPA technologies The focal plane array is based on the well established, SCD s, back illuminated InSb detectors technology. The InSb photodiodes are formed by ion implanting a p-type junction into a bulk n-type substrate, resulting in a planar structure. Following wafer fabrication and dicing, the InSb die is bonded to the Si- ROIC by means of SCD s proven indium - bump hybridization process. The InSb is thinned to its final thickness, and the back surface is processed to prevent carrier recombination. Then, AR coating is applied. In order to implement the LIRD, the InSb detector array technology had to be adapted to handle long and narrow rather than a square matrix arrays. This imposed new demands on nearly all process procedures, including dicing, handling, bonding and thinning. The indium-bonded diode array and Si- ROIC are forming a DS that contains 520 lines. The structure of a diode array is shown on Figure 5. The staggered configuration allows more space for the circuitry adjacent to the detector element Four DSs are butted precisely by means of indium bumps, in a staggered configuration, with some overlap, on an AlN substrate to form the FPA, with 2048 effective scan lines. The FPA is shown on Figure 4. Neighbor detector segments are rotated, each toward the other by 180. The bonding of the ROICs to the substrate by indium bumps provides improved thermal conductivity and improved immunity to stresses. Thermal non uniformity of less than 1 C across the substrate was measured. The bumps were optimized in terms of durability and thermal cycling. The positioning accuracy required when bonding four DSs one next to each other, required the development of a new, in SCD, butting technology concept. This technology involves the use of high surface quality jigs with special alignment marks, within a bonder. The alignment marks on the jig and on the substrate ensure the placing of the DSs in the right position and orientation within several microns. Using this technology and methodology, high alignment accuracy, in the range of 2 microns of misalignment, was achieved. The AlN substrate, instead of the more commonly used alumina substrate, was chosen to ensure better thermal expansion compatibility to silicon. But AlN is more complicated than alumina for multilayer design. The multilayer design was produced with a 'greentape' technology. Figure 5.The detector array of one DS.

5 4.2 ROIC design Block diagram of the chip. A layout oriented schematic description of a single processor chip appears on Figure 6. On top of the chip is the digital periphery, at the bottom the analog periphery and between them is the TDI core. On the right side of the TDI core are located the Integration (I) cells, the detector elements are shown superimposed over them. At the center of the TDI core are the Over-Sample (OS) stages, and on the left are the Output stages. The outputs of the Output stages are multiplexed to two output lines. Outputs The TDI realization concept Figure 6. Single ROIC block diagram There are numerous ways to perform the TDI operation for multiple elements scanning vector. The general idea is to perform summation of the same information, viewed by consecutively scanning detectors with time delay. Commonly, integration of the detector elements currents is performed for some pre defined integration time and the summation can be performed during the next integration period. Several concepts were reviewed considering layout aspects, complexity of implementation, precision aspects, power dissipation, etc. The implementation method was chosen in view of the long integration times, specified for this design, as compared to time needed to sum and delay the appropriate signals and as compared to integration times common to FLIRs. According to the chosen concept only one Capacitive Trans Impedance (CTIA), per detector element, is needed to implement TDI that supports scan without over-sampling. The CTIA serves as an integration stage and also as an adder, when initialized by a voltage, which is transferred to it from another stage. It also may be regarded as a sample and hold stage. To support operation in over-sampling mode, an additional stage, an OS stage, per detector element, is needed. Its construction is similar to the integrating stage, although it does not perform integration. All the stages are connected by a single communication line, as shown in figure 7. One additional stage, per channel, serves as the channel s output stage. It is also connected to the communication line. Through this line, the transferring of signals from stage to stage is performed. When a transfer is performed, the transmitting stage connects to the communication line by means of its output switch and the receiving stage by means of its input switch. Generally, the order of the transfers is as

6 follows: from stage n to output stage, then from stage n-1 to stage n, then from stage n-2 to n-1 and so on. At the last transfer the first stage is initialized by to some predefined voltage level. Figure 7 The TDI implementation concept The programmable TDI control concept, as a solution to numerous operation modes requirement As was mentioned above, the processor was required to support: bi-directional scan, over-sample and nonover-sample modes of operation, the selection of variable size groups of detectors for operation and making the background subtraction operational or non-operational. (The relevance of the background subtraction to the issue will be explained later). Selecting a partial group of detectors for operation, differs from the defective pixel de-selection mechanism. In the first case the number of transfers, which are accompanied by noise is also reduced. As a solution to the numerous operation modes requirement, the externally programmable TDI control concept was introduced. According to this concept the sequence of transfers can be externally programmed on the fly, during the integration time. Thus, providing the user the complete freedom to choose any, potentially possible, sequence of transfers to be programmed into the ROIC s TDI Control Memory (TDICM). It should be mentioned that this attitude is also very useful for testability of the processor. One mode of operation is stored in an internal ROM. This mode is called the default mode. In default mode all the detectors are selected for over-sample TDI and background subtraction is enabled. The principle of the realization is as follows: The implementation of the programmable TDI controller is based on assigning an address to each logic unit that controls a specific TDI chain stage. The function of the logic unit is to convey control signals from the control bus to a controlled stage when it participates in a transfer. So, two stages are selected to participate in a transfer when their logic cells are being addressed by an appropriate address that appears at the time of the transfer on the address bus. The addresses on the address bus are being read out sequentially, from an externally programmable memory array. In this way the sequence of transfers is determined by programming the addresses of the stages into the dedicated memory. Actually there are two memory arrays. One is for the forward transfer sequence and the other for the backward transfer sequence. It should be noted that the forward and backward transfer sequences are not the same sequence in reversed order Background subtraction concept. Background subtraction is implemented by charge injection into the over-sample stages. The injected charge causes a potential change of opposite direction to the potential change that is created by the increasing signal. The charge is injected when performing the transfers. As a consequence of this solution, when subtracting background, the over sample stages are involved in the transfer process, also in non-over-sample mode of operation. If n detectors were selected to be operable, in order to subtract full voltage span at the output, the subtracted potential change in each oversample stage, should be: channel s voltage span divided by n. The charge injection is bipolar. So it can be used to subtract offsets that have polarity that is opposite to the signal polarity. Actually the charge injection, for background subtraction, could be implemented into the integration stage. But those stages had some layout area shortage, limited by the detector element size. In view of the considerable signal non uniformity that was expected along the 2048 element array, due to the cos 4 θ effect, the background subtraction has the capability to be not uniform, along the vector. Each DS has two separate background subtraction controls. Each one of them controls one half of the chip. The background subtraction control

7 has 5 separate inputs to the FPA. One of them controls the four central chip s halfs. The other four, enable to apply independent controls to the remaining chip halves Defective pixel de selection memory, DPDM, and its programming Each integrating stage and over-sample stage has a memory cell adjacent to it. In the case of the integrating stage the content of memory cell controls the connection between the detector and the input of the stage, enabling a defective pixel element to be deselected but leaving the stage valid for the transfers. In the case of the over-sample stage, the content of its memory cell controls its connection to the background subtraction. When a detector element is de selected, in an appropriate over-sample cell the background selection is eliminated. That implies that the appropriate memory cells in the integrating stages and over-sample stages are programmed to the same logic values. The de selection memory is a volatile kind of memory, so it has to be programmed during the power up procedure. To ease the programming of four chips that two of them are at 180º orientation to the others, provision were made, in hardware, that the array would be seen as one continuous 2048 element array. This is accomplished by aligning the direction of the memory write registers according to chip s location in the array Readout direction control To ease the treatment of the chip array as a single array, the readout direction of each chip in the array is controlled by its location so that al the chips are being read out in the same direction, in spite their different orientations. Additionally, the direction of readout for the whole array can be also chosen Power saving techniques. For some applications of the array, low power dissipation is crucial. Power managing methods were used to save power. These methods are based on current enhancement and de enhancement of appropriate stages, during the operation cycle. Specifically all the stages are in current de enhance mode unless they are required for operation. When a group of detectors is selected for operation, only their input stages and over-sample stages are enhanced Noise, linearity and settling times Noise, linearity and settling times were treated with special care. The noise was designed to get D*/D*blip ratios as close as possible to one, for all specified ranges and modes of operation. Four integration capacitors were implemented. The smallest was intended to support high line rates and short integration times. The larger capacitances are for intermediate and long integration times. Linearity is important for uniformity correction. To achieve linearity, high gain closed loop amplifiers were implemented and level depending charge injection was carefully treated. Settling and overload recovery issues are of crucial importance when dealing with multistage TDI channels. Other problems of settling can occur at the output multiplexer. Those potential hazards were treated by resetting TDI communication lines between transfers and resetting the output lines between successive pixels. 5.1 General 5. PERFORMANCE, PREDICTIONS AND MEASUREMENTS New design concepts, of almost all detector s sub subassemblies were to be tested and approved. A lot of effort has been applied on thorough characterization of all sub assemblies and their approval. In this chapter, only some of the ROIC and radiometric performance will be presented. The ROIC, being the most complicated sub assembly, has been tested extensively in a laboratory dewar, to prove full specification and design goals compliance. Each of the four DSs comprising the detector was tested separately in a laboratory dewar for functionality and radiometric performance prior to their assembly. The complete detector was tested for functionality, performance and for customer acceptance. The power dissipation was measured to be about 2kHz line rate.

8 5.2 Functionality testing results The ROIC and then after the whole FPA were found to be fully operational and functional. All the functionality requirements, as described in section 2.2, and all their detailed features, were realized to the last detail! 5.3 ROIC Performance testing results Integration capacitors Integration capacitors and full charge capacities were calculated from measurements of the output voltage dependence on detector array current, with predefined integration time. The results are presented in table 2. The measured results are quite close to the designed. Table 2 Integration capacitors, designed and measured Designed Designed Measured Charge capacity [Me] Capacity [pf] Capacity [pf] (linear over 3V) ~ (linear over 3V) ~ (linear over 2V) ~ (linear over 2V) ~ Readout noise Readout noise was measured for the whole TDI chain and then normalized per Link. The results are displayed in Table 3. In the limits of noise predictions precision and measurements precision, the results are remarkably close. It should be mentioned that the noise was designed to enable the detector to be near Background Limited Performance, at specified conditions. Table 3. TDI Link readout noise, predicted and measured in (electrons) and [uv] TDI Link Noise (electrons) [uv] With OS & with BS No OS & with BS Cint=0.1pF Cos=1pF Cint=0.5pF Cos=1pF Cint=1.5pF Cos=1.5pF predicted measured predicted measured predicted measured (137) (~130) (213) (~250) (385) (~420) Same as above With OS & with- out BS No OS (Only I stages participate) (137) 219 (143) 230 (~130) (203) 65 (187) 60 (~235) 75 (~202) 65 (346) 37 (281) 30 (~374) 40 (~290) 31 Remarks: 1. A Link is a repetitive sub assembly of a TDI Chain. A number of links that are selected for TDI, form the TDI chain. 2. TDI Chain is defined as the series of Links that are selected to participate in the TDI process. Chain noise is the RSS (Root Sum of Squares) of Link noises, not including the initialization noise of the first I stage, which

9 is: KT C int. For detector assembly with proximity electronics, channel noise is defined to be as the RSS of all the mentioned noise contributions, including proximity electronics contribution, which is 130 uv, assuming final bandwidth, until digitation, of about 16 to 20 Mhz Background subtraction Background Subtraction performance is presented in table 4. It was tested and found reasonably close to predictions. Its noise contribution, as appears, in Table 3 was measured to be adequately low. Integration capacitor Table 4. TDI Link Background Subtraction, predicted and measured Background Subtraction[Me] per TDI Link Maximal subtraction [Me] per TDI Link 0.1 pf 0.25*(1.1V - Vdcs_n) pf 1.25*(1.1V - Vdcs_n) pf 2.5*(1.1V - Vdcs_n) Dynamic Range Linear output span was verified to be > 3V for the 0.1pF, 0.5pF capacitors and >2V for the 1.1pF, 1.5pF capacitors. Exact linearity was not measured. The final goal is to achieve low Residual Non Uniformity (RNU), after two point correction. RNU was measured directly and is presented later on. Using voltage spans and data from Table 3, the full TDI chain noise for several cases, leads to the results presented in Table 5. Table 5. Dynamic Range: (Output voltage span)[v] / (Chain noise) [V RMS ], for full chain cases. Dynamic Range C int = 0.1pF C int = 0.5pF C int = 1.5pF O.S. & Skimming 3,570 9,400 11,000 O.S. & no Skimming 3,570 10,000 12,500 No O.S. (extrapolated) 3,400 10,700 15, The degradation of, 300K, D* due to readout noise Knowing the noise contributed by Shot Noise and noise contributed by the readout, at given conditions, it is possible to estimate the degradation of D* by the readout noise. A Figure of Merit (FOM) can be defined to be: FOM =D e */D* blip. D* blip - Denotes D* for which noise is determined by shot noise only. D e * - Denotes D* for which noise is determined by shot noise and readout noise Table 6 presents the FOM, considering the measured readout noise presented in table 3. Because the readout noise is integration time independent, The D e and the FOM are time integration dependent. It is seen that for long enough integration times, BLIP can be approached. It is seen that the degradation of D* due to readout noise is very low. Unfortunately, there are other sources of noise, like shot noise that is caused by stray radiation or excessive dark current or external electronics noise, that can reduce the D* of the whole assembly.

10 Tint [µsec] Table 6. FOM for various integration times and capacitors. Figure Of Merit: D e */D*blip Cint = 0.1pF Cint=0.5pF Cint=1.5pF Radiometric Performance testing results Radiometric measurements were performed in standard room temperature conditions on the compete Detector Dewar Cooler Assembly (DDCA). The proximity electronics outputs were sampled by means of a custom digitizing tester that also provided the controls and computation means. The Detector Assembly was cooled with the cooler to 78K. Integration time of 512µSec was chosen. The 0.5pF integration capacitor was used. All the TDI stages were operational. The leaky elements were deselected from the TDI operation by the DPDM function. The Background Subtraction function was used to place the mean video output level in the center of the output operating range and to correct for offset differences (to some extent) between the segments. The signal response measurements were performed by placing the detector against a calibrated extended blackbody source and measuring signal response at 5 background temperatures: 12º, 18º, 27º, 36º, 42º C. Noise was measured with the same testing setup with background temperature of 27ºC Raw signal levels, of all 8 video lines, as function of black body temperature. Figures 8 and 9, show the raw signal at three different background temperatures. The theoretical curves, containing the predicted COS 4 (θ) distribution, are superimposed on the same graph (dotted line), in figure 8, for reference. Figure 8. Raw signal levels of 8 outputs Figure 9. Raw signal levels of 8 outputs, with some outputs level shifted by BS. Some defected channels with lower response are present. These defects originate in low-response elements within the channel that were not deselected. In figure 8, the deviation from the predicted results is mainly due to stray radiation penetrating in the area of detector array edges. Slight offset differences between ROICs can be observed. These issues will be investigated and corrected in future detectors. In figure 9, back ground signal non uniformity reduction, by means of segmented BS control operation, is demonstrated.

11 5.4.2 Quantum efficiency per channel, for all 2080 channels. The Quantum Efficiency for each channel was calculated from the measured data. The QE and its distribution are shown in figures 10 and 11, respectively: Figure 10. Quantum efficiency per channel. Figure 11. Quantum efficiency distribution. The QE value and narrow distribution comply with theoretical predictions and performance of other InSb detectors manufactured in SCD. Note that the defect channels seen here are the same defects which were shown in the Signal response results RNU calculation. Applying a two point correction algorithm 2 to the measured data, the Residual Non Uniformity (RNU) for each channel representing each channel's deviation from the two-point corrected image, can be calculated. RNU at T=27ºC was calculated using T1=18ºC and T2=36ºC as correction points. The RNU is shown, for each channel, in figure 12. RNU distribution is shown in figure C = 0.05% Figure 12. RNU per channel. Figure 13. RNU distribution. σ(rnu) versus temperature can be seen in figure 14, indicating the dependence of the RNU on temperature. σ(rnu) is lower than 0.05% in the range of 285K to 310K, over a span that is about 85% of the full scale output span. This result is quite remarkable, in view of the large number of TDI stages in series and the possibility that the chosen two temperatures were not optimal.

12 5.4.4 D* peak and NETD evaluation. Figure 14. σ(rnu) versus temperature. Figure 15. D* peak Distribution Noise, D* and NETD performance Noise measurements were conducted by sampling 2000 consecutive frames and performing standard deviation calculations for each channel. The noise was measured against a 27Cº blackbody photon flux. D* peak (at peak wavelength) and NETD were then calculated and compared with the predicted BLIP values. The results are shown in the next figures 15, 16: Figure 16. The NETD distribution Figure 17. NETD versus temperature, assuming, several noise sources contribution. 99 percent of channels have D* above the specified 4* The D* average value ratio to D* BLIP value, is 0.8,which is less than predicted being limited by the ROIC noise performance, in Table 6, for 500us integration time and 0.5pF integration capacitor. This is due to noise sources, other than the ROIC s noise: the proximity electronics noise, and excess current noise. The average NETD is about 14 mk, which is ~1.3 times than higher than the predicted BLIP value. The degradation sources are mainly the same as for the D*. On Figure 17, the predicted NETD dependence, of a typical channel, on background temperature is shown. The contribution to NETD degradation by various noise origins is demonstrated. The lowest curve is the BLIP NETD curve. The middle curve is NETD with the contribution of the ROIC noise, added. On the top curve, the shot noise of 100pA excess current, per element, is added. The top curve fits the measured results (at 300K).

13 The excess current was measured to be in the range of 100pA. Three quarters of this current are believed to be due to stray radiation and the rest is the detector s dark current. The matter of stray radiation is currently investigated. 6. CONCLUSION The construction and performance of Long Infra Red Detector with TDI, recently developed by SCD, was presented. The technological goals that were challenged in this design were achieved. The electrical tests show that low power, analog CMOS TDI, with large number of stages is feasible. As to functionality, all the design goals were achieved completely. Although dynamic performance tests were not described in the article, the dynamic performance was tested intensely and found to be acceptable, in a whole. The radiometric performance is, in general, within specifications, even in present prototype phase. It has the potential to be improved towards theoretical limits, with the current ROIC, by reducing the stray radiation sources. 7. ACKNOWLEDGEMENTS The authors express their deepest appreciation to Dr. Z.Calahorra the developer of SCD s, now well established, InSb process. This process is used in all SCD s InSb based products as well as for this product. This project was supported by the ministry of defense of Israel Government. The authors would like to thank Dr. D. Rosenfeld, the head of the technology department, for his support. Group members of all SCD s development groups were involved in the development of this product. We wish to thank all of them for their contribution. Special thanks are given to: - M. Geva for supervising and performing the masterpiece layout of the ROIC. - M. Yaaro for ROIC development tests participation. - G. Fogel for his contribution to characterization of the product. - A. Naboshchik, Y. Mustaki for their contribution to electronics integration. - H. Schanzer for her contribution to attachment processing. - A. Shechter for his contribution to the multilayer substrate design and construction. - Y. Karasenti, M. Manai, B. Yariv for their support in realization of all the InSb modules. - A. Cohen for VLSI Group system management. We are also thankful to Mr. A. Magner, manager of the Electronics group, Dr. J. Oiknine-Shlesinger, the manager of Characterization group and Mr S. Hasson the manager of the Mechanics group for their cooperation. The dewar was developed by SNRC. The cooler was developed by Ricor Cryogenic & Vacuum Systems. 8. REFERENCES (1) D. Rosenfeld, Second generation detector work in Israel, SPIE 4369, (2001). (2) L. Shkedy, O. Amir, Z.Calahorra, J. Oicanine-Shlezinger, and I. Shafranek, Temperature dependence of spatial noise in InSb focal plane arrays, SPIE 4028, (2000).