Advanced ROICs design for cooled IR detectors

Transcription

1 Advanced ROICs design for cooled IR detectors Michel Zécri, Patrick Maillart, Eric Sanson, Gilbert Decaens, Xavier Lefoul, Laurent Baud SOFRADIR, Technologies and Products Department, ZI, BP21, Veurey-Voroize. FRANCE ABSTRACT The CMOS silicon focal plan array technologies hybridized with infrared detectors materials allow to cover a wide range of applications in the field of space, airborne and grounded-based imaging. Regarding other industries which are also using embedded systems, the requirements of such sensor assembly can be seen as very similar; high reliability, low weight, low power, radiation hardness for space applications and cost reduction. Comparing to CCDs technology, excepted the fact that CMOS fabrication uses standard commercial semiconductor foundry, the interest of this technology used in cooled IR sensors is its capability to operate in a wide range of temperature from 300K to cryogenic with a high density of integration and keeping at the same time good performances in term of frequency, noise and power consumption. The CMOS technology roadmap predict aggressive scaling down of device size, transistor threshold voltage, oxide and metal thicknesses to meet the growing demands for higher levels of integration and performance. At the same time infrared detectors manufacturing process is developing IR materials with a tunable cut-off wavelength capable to cover bandwidths from visible to 20µm. The requirements of third generation IR detectors are driving to scaling down the pixel pitch, to develop IR materials with high uniformity on larger formats, to develop Avalanche Photo Diodes (APD) and dual band technologies. These needs in IR detectors technologies developments associated to CMOS technology, used as a readout element, are offering new capabilities and new opportunities for cooled infrared FPAs. The exponential increase of new functionalities on chip, like the active 2D and 3D imaging, the on chip analog to digital conversion, the signal processing on chip, the bicolor, the dual band and DTI (Double Time Integration) mode is aiming to enlarge the field of application for cooled IR FPAs challenging by the way the design activity. KEY WORDS Cooled Infrared detectors, ROIC design, power management, CMOS focal plane array 1. INTRODUCTION Infrared detectors material hybridized with CMOS readout integrated circuits (ROICs) is used in SOFRADIR to cover a large infrared bandwidth from visible to 20µm. The ability of such materials to allow a tunable cut-off wavelength associated to the advanced ROICs design techniques are generating new challenges for cooled infrared focal plan arrays (FPAs) but also challenge the design activity. High performance 1280x1024, 640x512, 1000x256, 384x288 formats using various input circuit with improved features in term of noise, dynamic range and high speed are currently used by our customers in the field of ground, airborne and space applications. The recent developments of FPAs using deep sub-micron CMOS technology hybridized with IR detector material currently in production at SOFRADIR are presented. The exponential increase of new functionalities required in the pixel design, the digital signal processing and the multispectral applications for examples, push designers to think about innovative solutions but also to consider more adapted Infrared Technology and Applications XXXIV, edited by Bjørn F. Andresen, Gabor F. Fulop, Paul R. Norton, Proc. of SPIE Vol. 6940, 69402X, (2008) X/08/$18 doi: / Proc. of SPIE Vol X-1

2 power management techniques to meet power constraints. Such evolution for FPAs and CMOS circuits are offering a wider field of applications. Design solutions are now able to conjugate a high input flux while keeping a low noise level and increasing at the same time the pixel dynamic range. The Double Time Integration (DTI) mode, developed by Sofradir, made it possible. The DTI mode allows to mix within the same wavelength, two different dynamic ranges. Specific application need, is also driving to specific ROIC design solutions such as the blooming due to very high flux. By opposition to classical anti blooming solution, new design solution exists to locally limit the current through the photo diode. This current limitation, integrated in each input stage, allows an accurate and a local control of the FPA when submitted to a high input flux. Another way of improvement for the ROIC s design is the direct analog to digital conversion within the FPA facilitating the data processing at the application level and aiming to simplify the customer interface for cooled infrared detectors. The designer challenge in analog to digital conversion is not only to meet the growing demands of performance in term of linearity and noise but also to simultaneously consider the power constraints. The increase of device counts and the increase in number of functionality per chip will require not only more aggressive deep sub-micron CMOS technology but also more aggressive power management techniques. In this paper, the recent progress of SOFRADIR infrared detectors technology associated to scaled CMOS circuits considerations are explored. 2.1 IR Detectors detection ranges 2. SENSOR TECHNOLOGY Different sensors technologies may be considered to deal with the specified range detection. Uncooled IR detector arrays are the perfect solution for short range applications, but to increase the range detection, a higher sensitivity is required. In that case, only cooled detectors can address IR detection from medium to very long range applications. Figure 1 is illustrating the IR detector range. ng range) Very long range )' / / Cooled IR detectors redum rflge rort rang /Uncooled IR detectors 1km 5km 10km 50km Figure1: IR Detectors detection ranges High performance IR detectors for long detection systems are dealing with detection ranges ranging from 6 kilometers to tens of kilometers. The high performance detectors are mandatory for long detection range but also for scientific applications including spectrometry, where a very small signal has to be detected. Proc. of SPIE Vol X-2

3 2.2 Performance combination of detection range versus wavebands for the different IR technologies SOFRADIR is currently using various technologies for IR detector production, some of them are part of figure 2. The Quantum Well IR Photo detectors (QWIP) have been developed by Thales Research and Technologies (TRT) and are at mass production level in cooperation with Sofradir. The InSb technologies are also available in France. The HgCdTe technologies, have been widely used for high performance IR detectors and are at mass level production at Sofradir since many years. Finally uncooled technology was developed based on amorphous silicon microbolometers at CEA-Leti and transferred to ULIS (spin off of SOFRADIR) for mass production since Those different technologies are complementary and used in regards of the application need, in particular the detection range need and the ability of these materials to detect in bad weather environmental conditions. Detection ranges Very long Long C 0 - toj Medium a eimct Short Thermal detector (Micro bolometer) VIS Sw MW Dualband LW VLW Figure 2: Performance combination of detection range versus wavebands for the different IR technologies As it has been discussed above, different cooled sensor technologies may be used to cover the spectrum range from visible to very long infrared wavelength. 2.3 Architecture of hybrid CMOS focal plane array There are mainly three components contributing to build a hybrid CMOS focal plane array: the detector array, the readout circuit and the indium bump layer. The detector is responsible for photon to charge (electrons) conversion. The readout circuit role is first to read the photodiode signal and then to integrate the charge coming from the detector and secondly to convert charge to voltage in order to multiplex the voltage at the output stage for signal processing. The readout circuit and the detector area are hybridized together thanks to the flip chip bonding allowing their electrical and mechanical connection. Figure 3 illustrates this assembly made of: - the substrate for the sensitive layer, in the case of MCT, which is transparent in infrared spectrum down to 0.8 µm (most of the time this substrate is removed), - an antireflection layer deposited on the substrate to enhance the detector quantum efficiency by improvement of the infrared rays transmission, - the sensitive layer, (MCT for this illustration) - indium bumps which ensure the electrical connection between photodiode and the readout circuit - the silicon readout circuit which enables to readout the signal detected by the detector array Proc. of SPIE Vol X-3

4 AntireflecUon layer strata SeSlive array _Electsiml cormectio indium bump ' Silicon rdout circtit Figure 3: Cross section of a hybrid CMOS FPA 3. RECENT PROGRESS FOR FPAs CURRENTLY IN PRODUCTION AT SOFRADIR Since 2003, SOFRADIR is the leader in the development and production of the 15µm pitch node, derivative sensor from the 640 x 512 array has been developed and is now in production: 1280 * 1024 array (pitch 15 µm). This array is aligned with the need to increase the number of pixels in Cooled IR detectors. Other developments, focused on cost reduction, are also available in European TV format (384 x 288), with a fixed window corresponding to the US standard size (320 * 256), with a pitch of 15 µm. Simultaneously another large array has been brought to production at SOFRADIR: 1000 * 256 with a pixel pitch of 30 µm. This array is also declinable in a 500 * 256 matrix format. Such development has been mainly focused on spatial applications, requiring a very low input flux. The input stage is based on a Capacitive TransImpedance Amplfier (CTIA) architecture, with two maximum storage capacities (525 Ke- or 2.2 Me-), programmable line per line. The lines may also be read out or not on a line per line basis depending of the control register. Table 1 shows the main features of recent Sofradir components. This table shows that Sofradir components are declined in many different formats, with variable number of outputs, and high output rates, windowing mode. A new readout circuit with only a tenth electrons noise is under development. Circuit Neptune Saturne Epsilon Scorpio Jupiter Input stage CTIA CTIA DI DI DI Array format 500 * * * * * 1024 Pixel pitch 30 µm 30 µm 15 µm 15 µm 15 µm Number of 2 or 4 4 or or 8 output Nominal pixel rate 5 Mpixels/s/output 8 Mpixels/s/output 16 Mpixels/s/output 10 Mpixels/s/output 20 Mpixels/s/output Maximum 20 Mpixels/s 64 Mpixels/s 16 Mpixels/s 40 Mpixels/s 160 Mpixels/s pixel rate Read out Snapshot Snapshot Snapshot Snapshot Snapshot mode Window mode Each line may be selected or not Each line may be selected or not 384 * 288 or 320 * 256 Random (min. 128 * 1) Random (min. 256 * 1) Charge capacity 525 Keor 2.2 Me- 525 Keor 2.2 Me- 3.9 Me- 4.4 Me- 4.2 Me- Read noise < 100 e- or 240 e- < 100 e- or 240 e- <260 e- <390 e- <350 e- Table 1: Recent Sofradir components Proc. of SPIE Vol X-4

5 4. COOLED IR FPAs TECHNOLOGY NEEDS Like for visible imager, the tendency in infrared sensors is to exponentially increase the number of pixels accordingly to the pixel pitch reduction. The first version of Infrared arrays developed by Sofradir was with pitches at 50 µm going down step by step to 30 µm, 25µm, 20 µm and 15 µm. The diffraction limit of the IR radiation will be more and more difficult to overcome in future designs. The second tendency for sensor technology is the development of large monolithic detector circuits (for example,sofradir has designed a 34 mm long readout circuit). Readout circuits are generally limited around 20 mm (maximum reticule format) and will lead to use stitching techniques to make large readout circuits. Different approaches can be used, a true stitching made by combining two different set of reticules or by using two electrically separated circuits stepped aside. Sofradir has thus already developed a 1000 * 256 array with 30µm pixel pitch, and the same technique is allowing to realize circuits with 2000 pixels length using 15 µm pitch or even more. The dual band sensors [1] which allow addressing two different spectral bandwidths, i.e. for instance SWIR/MWIR, MWIR/MWIR, or MWIR/LWIR is also part of the growing demand. Different ways to design such dual band detectors have been investigated jointly by SOFRADIR and CEA-Leti, either pnp structures or two p/n diodes aside, with two bumps per pixel. Sofradir has designed a 320 * 256 pixels array operating in the SWIR/MWIR bandwidths as shown in figure 4. The main features for that product are described in the table below. Pitch 30 µm Waveband 1-3 µm / µm FPA Op. Temperature up to 110 K Storable charges 11.4 to 12 Medynamic range 80 db Windowing Min 128x1 Image mode Snapshot Readout mode ITR Video outputs 4:2 per band Max Pixel rate/output 10 MHz frame rate Up to 200Hz Table2: JANUS product: 320x256 pitch 30µm MCT MBE bicolor SWIR/MWIR Figure 4: dual band illustration for JANUS product: 320x256 pitch 30µm MCT MBE bicolor SWIR/MWIR Proc. of SPIE Vol X-5

6 For several applications involving low flux detection, the avalanche multiplication into the photo diode is a way to get current amplification [24]. Recent works at CEA- Leti demonstrated for n/p MWIR HgCdTe photo diode high avalanche gain together without any excess of noise. All these new features are source of challenges for the readout circuit designs, and Sofradir is therefore offering new functionalities to address these points. 5.1 Dual band and bicolor 5. NEW ROIC s FUNCTIONALITIES We can emphasize a new readout circuit designed for bicolor/dual-band applications. This circuit is based on a newly quasi planar technology for IR sensors developed by the CEA-Leti [5], [6], [7], [8]. Both sensors are n/p type. The sensitive diodes are connected with two indium bumps per pixel. The dual band pixel implementation is shown in figure 5 hereafter. N P Figure 5 : dual band pixel The array size is done by 640 * 512 bicolor pixels with a 24 µm pitch. The readout circuit size is * mm² with a maximum storage capability of 3.5 Me- for the first bandwidth and 10.5 Me- for the other one. Two separated input stages are designed in the same pixel in order to address the two different bandwidths. The circuit operates in a snapshot mode, and may be used following three different ways: Integrate While Read mode, Integrate Then Read mode or the new Double Time Integration mode which allows two different integration times during the same frame. The diodes are biased to the readout circuit in direct injection mode. The current is integrated in MOS capacitors and read out by a switched follower. The Switched follower output is sampled and multiplexed towards 4 outputs (two per spectral bands) at a maximum of 20Mpixels/s/output rate. The input stages have anti-blooming capability. The power consumption is < 80 mw for the complete circuit with a read out noise of 130µV. Proc. of SPIE Vol X-6

7 Folbwer Figure 6 : dual band readout circuit 5.2 DTI (Double Time Integration) mode A frequently encountered problem is due to the high dynamic range of the scene. In order to be able to identify a scene around a hot spot, it would be interesting to read out the data obtained with two different integration times. The Sofradir DTI mode provides both data of the first and second integration time at the readout circuit outputs within the same frame. At system or subsystem level, the most relevant output is chosen in order to obtain the best image. The most illuminated pixels of a scene can be extracted from the data obtained with the lowest integration time, and the least illuminated pixels can be extracted from those obtained with the highest integration time. With the DTI mode a double imaging contrast is obtained. 5.3 Pixel current peak controller Another unexpected situation which may arise is due to a very high illumination level on some of the pixel array. When the input flux is increasing suddenly, a high current can be generated. If an anti-blooming function is available on the readout circuit, this current will be maintained in the photodiode throughout the whole integration time. The antiblooming function is only required up to a certain level but, if too much current is going through the diodes and to avoid damaging the circuit a current peak controller, which will have the opposite behavior of a classical anti-blooming function, can be used. Proc. of SPIE Vol X-7

8 Such a function has been implemented in each pixel on a quarter TV format type with a pitch of 30 µm. This array uses the direct injection coupling and is read via the SCA technique patented by the infrared laboratory of CEA-Leti. When the input current is higher than a pre-defined threshold, the gate of the direct injection transistor is biased authorizing the maximum current to go through this transistor. Figure 7 shows the response of the current limiter when applying a triangle current source. It can be seen that the current is limited when exceeding a given threshold. Figure 8 shows the response to a current step. Current peak control / l7ø Figure 7: Illustration of the current limiting process Figure 8: Response to a high current step 5.4 ADC on chip Since several months Sofradir is investigating various possibilities for Analog to Digital conversion on chip. The first A/D converters were designed to be used at the analog chain output. This allows to provide either the analog output, with full performances, or the digital outputs coded on 12 bits. This output A/D converter operates up to 10 Msamples/s and was mainly dedicated to uncooled applications [9]. The performance required for cooled applications cannot be satisfied by only 12 bits. That was one of the reasons for Sofradir to work on column A/D converters in cooperation with the CEA-Leti. This kind of readout circuit doesn t provide an analog output, and then the full performances must be obtained through the A/D conversion. Proc. of SPIE Vol X-8

9 Sigma-delta converters have been studied for their ability to provide a large number of bits but, the power consumption and the high frequency clock required for this kind of conversion could be considered limiting the large arrays applications. The area used to implement such structure is also a limiting factor. A test vehicle was designed with a pitch of 25 µm showing good performance results but balanced by the limiting factors described above. The ramp A/D converters have been also evaluated. Their expected resolution were lower than Sigma-delta converters, but theoretically able to obtain the required 14 to 15 bits with a lower power consumption. The clock frequency for such architecture was also reduced resulting in lower coupling between the digital and the analog sensitive parts. A 640*512 readout circuit with a pitch of 15 µm was designed. It was based on a single ramp, dual slope, A/D column converters. The power consumption of such an array was increased by 90 mw comparing to a purely analog readout circuit. To further decrease the power consumption, which is the major issue for cooled infrared components, the algorithm A/D converters has been developed in a 640x512 format at 15 µm pitch. The clock frequency for this type of converter is reduced comparing to the previous architectures. This structure can also be easily pipelined. Another advantage of such architecture is a constant conversion time. The clock frequency is about 60 MHz, leading to an output rate of 30 Mpixels/s on 8 outputs. Regarding the power consumption, this ADC has been optimized to be very competitive in term of power consumption with less than 70µW per column. The noise is aimed at 200 µv RMS. The figure hereafter shows the simulated linearity error. Sofradir has thus investigated different kind of A/D converter, and may thus use the most relevant one regarding the needs, the required formats, the system constraints, and so on Critic@ m (V) In1jut voltage y) Figure 9: Simulated non linearity curve of the algorithm column ADC The next step of the ADC on chip is to bring the conversion directly within the pixel in order to reduce as much as possible the noise added by the analog chain. A first design has been made by the CEA-Leti on a 25µm pixel pitch. 6. ROIC s DESIGN TENDENCIES In the past, the evolution of readout circuit design was focused on the increase number of pixels and on the pixel pitch reduction. The main concern was so in analog design. Nowadays, customers request more and more flexibility and/or user friendly interface to simplify the use of readout circuits. This is leading to an increasing demand of digital design on the FPA. More flexibility means also to add new functionalities on chip, which were previously implemented at the subsystem level. Moreover new functionalities like DTI, peak current limiter, and even bicolor/dual band IRFPA are answering the growing demand of flexibility. User friendly circuits push to develop more robust solution, like having A/D converters on chip rather than outside. In that case, the proximity electronics, as well as the shielding, is widely simplified. Proc. of SPIE Vol X-9

10 ADC on chip must be as close as possible to the performances of the equivalent analog product but ADC on chip is not the achievement of the digital part for infrared ROIC s but the necessary bridge to go to the image processing on chip. Automatic offset and gain correction algorithms, for instance, will be implemented on chip. Primary subsystem functions will also be implemented on customer request. Adding functionality on chip requires of course more and more area available, although the overall need remains a small pitch and a small chip size. The silicon technology shrink is a solution but, if it allows to improve the density and to reduce the power consumption of the digital part, the price to pay for advanced technologies could be the signal over noise ratio before A/D conversion. The technology choice must take into account the analog parts in order to obtain the best signal over noise ratio before A/D conversion. The digital part of a ROIC will no longer be confined to the control logic and internal phase generation but, must take into account the new functionalities such as Inter Integrated Circuit Bus (I2C) serial interface for instance. The increase of the logic functionalities in a readout circuit would mainly demand a high performance digital technology. Figure 10 shows that the need of digital parts in readout circuit is growing while the supply voltages of the available silicon technologies decrease Supply voltage Percentage of digital part in readout circuits figure 10 : IR ROIC s power consumption projection This growing demand of digital parts for readout circuits will result in an increase of the power consumption. The power consumption is of huge importance for cooled IR applications. Up to now, the power consumption was mainly due to the analog parts. Today the power consumption due to the digital parts of the readout circuits can reach the analog parts ones. Power management techniques must be used in current designs to overcome such issue. 7. POWER MANAGEMENT AND ROIC s TECHNOLOGY The table hereafter shows, for the past years, the ratio evolution of the digital power consumption comparing to the whole power consumption. Year < Typical array format 320 * * *256 Digital power consumption 1.1 % 3.9 % 26 % Table 3 : Digital power consumption versus array format and year Proc. of SPIE Vol X-10

11 = Voltage(V) = The digital part of a circuit can be divided in two parts. One is mainly dedicated to the internal clocks generation, the second one to the control logic. The digital power consumption of the internal clocks generation has increased with the number of lines and columns of the array, but is no longer the major actor in digital power dissipation. The control logic has seen its power dissipation rise mainly with the need of large register used to control the gains, the actual format, or the redundancy. These registers can also be tripled to harden the devices against irradiation. When power management techniques are not used, the clock of these registers is continuously applied, and so the power dissipation due to these registers may be high, even if no new data are applied to them. For instance the power consumption of a register composed of static flip-flops operating near 4 MHz, have been reduced by 50mW only halting its clock when not used. Power management is an actual way of reducing the thermal load due to readout circuits. As digital power consumption varies as the square of the supply voltage, another important way to reduce the power dissipation is to decrease the digital power supply voltage. In this case, two different supply domain may be used, one for the analog domain, in order to achieve a good signal over noise ratio, and another one for the logic part of the circuit in order to reduce the power consumption. Level shifters are then used to interface those supply domains. As shown in figure 11, the semiconductor technology evolution, drove by other industry using embedded systems like mobile phone, automotive, wireless etc, go in this direction. Figure 11: design window evolution in function of the technology evolutions Unfortunately, the maximum ratings used within micro-electronic applications and the decreases of the CMOS device breakdown are significantly reducing the design window for ROIC s design. The increase of device counts and the increase in the number of functionality per chip will require, in a very near future, technology capable for high analog voltage mixed with digital CMOS technology operating at very low voltage. This need is exacerbated for cooled ROIC s where the power consumption is one of the most important criteria. Proc. of SPIE Vol X-11

12 8. CONCLUSION The recent progress in IR detector technologies, jointly developed by SOFRADIR and CEA-Leti, allows system performances improvements. The efforts driving to higher pixel density, larger formats, dual band and APD (Avalanche Photo Diodes) technologies are going on contributing to the third IR detectors generation. At the same time, the growing demand for signals processing on chip by subsystem users is leading to develop new digital and logic functions. The pixel current peak controller, the DTI mode and the ADC on chip presented in this paper are the perfect illustration of the emerging need in more and more signals processing on chip. The ADC on chip dedicated to cooled IR detectors applications is the mandatory step to access many opportunities offered by digital world. It was the case for many other industries (uncooled IR detectors, smart sensors, automotive, etc ) in the past. Referring to what is happening in order to further simplify FPA control at system and subsystem level; the prediction to see an exponential development of digital and logic part in cooled FPAs is becoming a reality. The increase of device counts and the increase in number of functionality per chip show the evolution of the importance of ROIC design in IR detectors. As it is presented in this paper, such evolution is requiring not only more aggressive deep sub-micron CMOS technology but also more aggressive power management techniques challenging by this way the ROICs design activity. High performance and high competitive IR detectors will inexorably go through the combination of the IR detectors technologies improvements and of innovative ROIC s design solutions to meet performances and power constraints. 9. ACKNOWLEDGMENTS The authors would like to thank SOFRADIR colleagues from technology and R&D optronic departments for their large support and valuable discussions. This work development would not be possible without the useful contribution from our partner the CEA-Leti. Thanks also to the French DGA and DGE for their support. REFERENCE [1] From visible to infrared, a new detector approach, P. Chorier, P. Tribolet, Gérard Destéfanis [2] F. Guellec, P. Villard, F. Rothan, L. Alacoque, C. Chancel, P. Martin, P. Castelein, P. Maillart, F. Pistone, and P. Costa, "Sigma-delta column-wise A/D conversion for cooled ROIC", Proc. of SPIE - Vol (2007) -- Infrared Technology and Applications XXXIII. [3] S. Kleinfelder, A. Hottes, R.~F.~W. Pease, "Focal plane array readout integrated circuit with per-pixel analog-todigital and digital-to-analog conversion", Proc. of SPIE Vol (2000) -- Infrared Detectors and Focal Plane Arrays VI. [4] Gain and dark current characteristics of planar HgCdTe avalanche photo diodes. G Perrais, O Gravrand, J. Baylet, G. Destefanis and J. Rothman- Communication: The 2006 US workshop on the Physics and Chemistry of II VI materials (Newport USA oct 2006) [5] TV/4 dual band HgCdTe infrared focal plan arrays with a pitch of 25µm and spatiam coherence. J. Baylet, Ph. Ballet and all. The 2005 US workshop on the physical and Chemistry of II VI materials (Boston USA sept 2005) [6] Status of HgCdTe bicolour and dual band infrared focal plan arrays at LETI. G Destefanis, J. Baylet, Ph. Ballet and All. Communication: The 2006 US workshop on the Physics and Chemistry of II VI materials (Newport USA oct 2006) [7] Bicolor and dual band infrared focal plan arrays at DEFIR. G Destefanis, J. Baylet, Ph. Ballet and All. Communication: International SPIE meeting Infrared technology and application XXXII( Orlando USA April 2006) Publication SPIE proceedings (vol ) [8] Demonstration of a 25µm pitch dual band HgCdTe infrared focal plan array with spatial coherence. P. Ballet, P. Castelein, G Destefanis, J. Baylet, Ph. Ballet and All. Communication: International SPIE meeting Optics and Optoelectronics, Bruges Belgium sept Publication SPIE proceedings vol [9] Model based on-chip 13bits ADC design dedicated to uncooled infrared focal plane arrays, B. Dupont, P. Robert, ULIS (France) Proceedings of SPIE Florence September Proc. of SPIE Vol X-12