Lecture 2, Amplifiers 1. Analog building blocks

Transcription

1 Lecture 2, Amplifiers 1 Analog building blocks

2 Outline of today's lecture Further work on the analog building blocks Common-source, common-drain, common-gate Active vs passive load Other "simple" analog building blocks Current mirrors Mismatch And other things related to that ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 45 of 454

3 What did we do until now? Stress on the complexity of analog design. It is not easy and it will take many years before you master. Why analog design? Our world is analog and telecommunication needs analog to interface Complexity is growing as (n)ever. Common-source stage and small signal schematics Operating point vs small-signal schematics and how they "move" around ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 46 of 454

4 Transistor, revisited I D D V DS V SG S G B V BS G B V SB V GS S D V SD I D (a) NMOS (b) PMOS ( I αv 2 eff 1+ V ds V θ ) ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 47 of 454

5 Transistors, small-signal expressions Linearization gives a small-signal model with these properties: Expression Cut-off Linear Saturation g m g mbs κ I D k T /q g m 1 κ κ 2α v ds γ g m 2 V SB +2 ϕ F 2 I D 2 α I v D eff γ g m 2 V SB +2 ϕ F g ds λ I D 2α(v eff v ds ) λ I D ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 48 of 454

6 Transistor gain vs region Using the small-signal parameters gives us the following: Expression Cut-off Linear Saturation A= g m g ds κ q λ k T v ds v eff v ds 2 λ v eff 2 α λ I D What can you spot (where is the gain highest)? 0.75 and k T /q 26 mv ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 49 of 454

7 Poles, bandwidth, gain, etc. Bode plot Approximations Pole vs gain vs unity-gain Hand-calculations, practical tips Settling vs pole Speed ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 50 of 454

8 Amplifier stages, passive load Common-source, common-drain, common-gate V i n M 1 R L R L V out V out V out V i n V bias M 1 R L M 1 V i n (a) NMOS CS (b) NMOS CD (c) NMOS CG ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 51 of 454

9 Amplifier stages, active load V b,2 V in V b,2 V out V out V out V in V b,1 V b,1 C L C L C L V in Why active load? ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 52 of 454

10 Amplifier stages, compiled 1 Expression CS CD CG*) DC gain, A 0 g m g out g m g P g N g m g m g P g N 1 g m g P g N Output impedance, g out g P g N g m g P g N Bandwidth, p 1 g out C L g P+g N C L g m C L g P+g N C L Unity gain, A 0 p 1 g m /C L N/A (why?) g m /C L Source impedance not mentioned, see exercises ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 53 of 454

11 Amplifier stages, compiled 2 Expression CS CD CG*) DC gain, A 0 g m / g out 1/ v eff 1 1/ v eff Output impedance, g out I D 2 I D /v eff I D Bandwidth, p 1 g out /C L I D /C L 2 I D /C L v eff I D /C L v eff Unity gain, A 0 p 1 I D /C L v eff N/A (why?) I D /C L v eff ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 54 of 454

12 Voltage swings Walk around the circuit Check for all the required voltage levels to maintain transistors in their saturation region Use the following relations V GS =V EFF V T, V DS V EFF V DS =V EFF, V EFF = The lower v eff, the... higher swing higher gain I D ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 55 of 454

13 Examples Consider the three amplifiers and check the potentials ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 56 of 454

14 Some other relationships Expression Generic CG/CS CD Slew rate SR I D C L ω u v eff p 1 v eff 2 Noise, input-referred v n 2 ( f ) 4 k T γ g m 2 k T γ v eff I D Noise, total output v 2 out k T γ A 0 k T γ C L λ C L v eff k T γ C L ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 57 of 454

15 Mismatch, or "In reality, nothing is perfect..." Differences in Fabs (wafer-to-wafer, fabrication, date) Wafer locations (chip-to-chip, doping) Transistor (block-by-block, orientation and side effects, doping) Temperatures, Voltages, Currents You cannot assume that one transistor is identical to another Especially not for high-speed, high-accuracy applications ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 58 of 454

16 Mismatch, cont'd The drain current in the saturation region: I D = d I D d d I D d S S d I D V d V eff d I D V eff d V ds = ds = I D I D S S I D I D = S S 2 I d V eff V eff I D I D 2 V eff V eff I d 1 V ds V eff V ds 2 V eff V eff V ds 1 V ds V eff ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 59 of 454

17 Mismatch, cont'd Ignoring the low-impact ones, and assuming that they are decoupled, gives us, with the help of stochastic variables: 2 First-order assumptions I D I D Second-order assumptions = 2 2 V eff 2 V eff 2 A 2 S W L and 2 V eff A 2 VT W L Distance-related, correlations, etc ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 60 of 454

18 Current mirrors Distribute currents Set bias levels "Equal" current through many branches Decouple design parameters Gain is now controlled by current instead ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 61 of 454

19 Current mirrors, cont'd I i n I o u t I i n I o u t I i n I o u t M 3 M 4 M 3 M 4 V bias M 1 M 2 M 1 M 2 M 1 M 2 (a) Simple (b) Cascode (c) Wideswing ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 62 of 454

20 Current mirrors, some maths Swing Input impedance Output impedance ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 63 of 454

21 What did we do today? Went through the other important CMOS building blocks CG, CD, CS, (CI) Current mirrors How to bias a circuit (current mirrors) Pros and cons with different current mirrors Mismatch ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 64 of 454

22 What will we do next time? Amplifiers and differential pairs Why differential? Stability Why stability? Phase margin Compensation ::ANTIK_0025 (P1B) Analog and discrete-time integrated circuits (ATIK) 65 of 454