ECE 598 JS Lecture 13 Power Distribution

Transcription

1 ECE 598 JS Lecture 13 Power Distribution Spring 2012 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois 1

2 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to 100 m, and the thickness of the oxide layer (t ox ) is in the range of 2 to 50 nm. 2

3 NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type substrate MOS devices are smaller than BJTs MOS devices consume less power than BJTs

4 MOS Triode Region - 1 W ID Cox VGS VT VDS L V V V 4 DS GS T C ox t ox ox 3.9 o t ox C ox : gate oxide capacitance : electron mobility L: channel length W: channel width V T : threshold voltage

5 MOS Triode Region - 2 V GS V T V V V DS GS T W 1 I C V V V V L 2 2 D n ox GS T DS DS Charge distribution is nonuniform across channel Less charge induced in proximity of drain

6 MOS Active Region V V V V Saturation occurs at pinch off when DS GS T DSP V GS V T VDS VGS VT (saturation) W I C V V 2L 2 D n ox GS T

7 NMOS IV Characteristics characteristics for a device with k n (W/L) = 1.0 ma/v 2. 7

8 MOS Capacitances Expect capacitance between every two of the four terminals.

9 PMOS Transistor 0 PMOS VGS= VGS=-1.0 VGS=-1.5 VGS=-2.0 VGS= All polarities are reversed from nmos - v GS, v DS and V t are negative - Current i D enters source and leaves through drain - Hole mobility is lower low transconductance - nmos favored over pmos Vds

10 Complementary MOS CMOS Characteristics Combine nmos and pmos transistors pmos size is larger for electrical symmetry

11 CMOS Advantages Virtually, no DC power consumed No DC path between power and ground Excellent noise margins (V OL =0, V OH =V DD ) Inverter has sharp transfer curve Drawbacks Requires more transistors Process is more complicated pmos size larger to achieve electrical symmetry Latch up

12 MOSFET Switch NMOS PMOS Characteristics of MOS Switch MOS approximates switch better than BJT in off state Resistance in on state can vary from 100 to 1 k

13 CMOS Switch CMOS switch is called an inverter

14 CMOS Switch Off State OFF State (V in : low) nmos transistor is off Path from V out to V 1 is through PMOS V out : high

15 CMOS Switch Input Low GSN NMOS V V OFF TN r dsn high r dsp PMOS 1 k W V V ' p DD TP L p r dsp is low

16 CMOS Switch On State ON State (V in : high) pmos transistor is off Path from V out to ground is through nmos V out : low

17 r dsn CMOS Switch Input High ' n DD TN L n NMOS 1 W k V V r dsn is low GSP PMOS V V OFF TP r dsp high

18 CMOS Inverter r dsn 1 k W V V ' N DD T L n r dsp 1 k W V V ' P DD T L p Short switching transient current low power

19 CMOS Inverter VTC 19

20 CMOS Dynamic Power Dissipation In every cycle Q N dissipate ½ CV DD2 of energy Q P dissipate ½ CV DD2 of energy Total energy dissipation is CV DD 2 If inverter is switched at f cycles per second, dynamic 2 power dissipation is: P D fcv DD 20

21 PDN Network A PDN in a system provides the interconnection framework in which gates are allowed to switch states Power supplies are bulky and cannot be connected directly to IC wires and interconnections must be used Current through wires create DC drop and voltage fluctuations PDN must be created to regulate voltage for required current to be supplied over time 21

22 PDN Network The speed at which a circuit operates determines the speed at which charge can be supplied or removed from capacitors A PDN provides the interconnection framework to facilitate this process Power supplies cannot be connected directly to ICs, therefore interconnections (with resistance and inductance) are used PDN must be created to regulate voltage for required current to be supplied over time 22

23 Voltage Fluctuations Voltage fluctuations can cause the following Reduction in voltage across power supply terminals. May prevent devices from switching Increase in voltage across power supply terminalsreliability problems Leakage of the voltage fluctuation into transistors Timing errors, power supply noise, delta I noise, simultaneous switching noise (SSN) 23

24 PDN Network A PDN consists of a power supply, DC DC converters, lots of decoupling capacitors and interconnections Power supply provides high voltage and current to motherboard Voltage is reduced through a DC DC converter Decoupling capacitors are distributed on the motherboard package and IC and act as charge reservoirs 24

25 Mechanism For an IC, the transient current flowing through an inductor gives a voltage drop V=LdI/dt Positive di/dt leads to reduction in supply voltage. Negative di/dt results into an increase in supply voltage reliability problems as several components Supply noise has several components Ultra high frequency noise ~ 100 GHz High frequency noise 100 MHz 1GHz Mid frequency noise 1 10 MHz Low frequency noise KHz 25

26 Target Impedance The ratio of voltage to current must equal the impedance in the network Z T VDD ripple 50% I max V DD : power supply voltage ripple: allowed ripple on power supply I max : maximum current drawn by IC The target impedance is a function of frequency. The goal is to keep it as low as possible. 26

27 Interconnects and PDN Gate A Output voltage from Gate A + V 1 - Low Frequency Wire B N GROUND CONNECTION Differential voltage at receiver V 1 - R + V 1 - Gate C R + - Internal reference generator Gate A Output voltage from Gate A + V 1 - High Frequency GROUND CONNECTION Wire B - N + Equivalent noise source in series with ground connection Differential voltage at receiver V 2 - N - R + V 2 - Gate C R + - Internal reference generator At high frequencies, Wire B is a transmission line and ground connection is no longer the reference voltage 27

28 Rules for Power Distribution Gate A Signal current flowing between gates X and Y Gate C Wire B Ground inductance - Gate X Signal current flowing between gates X and Y induce ground voltage N which interferes with reception at gate C - N + Gate Y Use low-impedance ground connections between gates Provide low-impedance path between power and ground Minimize voltage differences between power lines 28

29 Bypass Capacitors Inductance of this short connection is very low Abbreviated path for charging current Power Only a smoothed current flows in this part of wiring High-frequency current in this path is suppressed GATE A Clock input C 1 C 2 Bypass capacitor power source Reduce voltage drops caused by the inductance of PDN 29

30 IC PDN Core: Primarily made of transistors I/O: Provides communication with other ICs Core and I/O require separate PDN Goal: ensure sufficient charge is supplied to switching CKT so capacitance can be charged to required voltage Charge has to be supplied within a short timeminimize delay need L/R<<RC 30

31 IC on Package 31

32 Motivation and Objectives Provide stable, quiet DC supply voltage Compensate for large AC current draws Compensate for fast transients Current draws of 200A Rate of change of 200 GA/s Voltage supply needs to be maintained within 10% 32

33 Power-Supply Noise - Power-supply-level fluctuations - Delta-I noise - Simultaneous switching noise (SSN) - Ground bounce VOH VOL Ideal Vout Actual Vout Time 33

34 Power Distribution Path 34

35 Power Supply Network Bus Backplane PC Board Package IC Interconnect Power Supply Load On board inductance and on-chip resistance Symmetry between power and ground (return path) Distributed over several levels of interconnections 35

36 Load Current Load is usually periodic with clock Can be in phase and reinforce one another Load are often resistive, varying linearly with supply voltage Load can be high impedance Current Time 36

37 Local & Signal Loads Local loads connect a point in the network to a corresponding point in the ground network Current can be supplied by local bypass capacitor Signal loads connect a point in the power network to a distant point in the ground network Unbalanced signaling Long return current path Bypass capacitors do not help 37

38 Inductive Supply Noise Each section of the circuit is an LC tank - Resonant frequency is LC =(LC) -1/2 - Inductor carries DC current (low pass) - Capacitor supplies AC current (high-pass) Chose size of capacitor to: - supply cycle to cycle AC current with acceptable ripple - handle inductor start/stop transient 38

39 Local Regulation Used to prevent overshoot so voltage cannot exceed nominal value by more than a small amount. Supply overshoot can be reduced via clamping Supply voltage droops can be reduced using shunt regulators Clamps draw little power and are inexpensive Shunt regulators dissipate considerable average power and are expensive 39

40 Local Regulation Using Clamps I X 0 if VL Vn k ( V - V ) if V V s L n L n Clips off top half cycle by directing inductor current into clamp rather than capacitorprevents overshoot. Cannot prevent supply voltage drooping. k s : transconductance of clamp 40

41 Shunt Regulators I max 0, I I k ( V V ) X max 1 s L n k s : transconductance Keeps current constant Regulates voltage Not used on chip Power hungry and expensive Last resort to prevent supply voltage droops 41

42 General Topology for Power Distribution Hierarchy of distribution networks Usually a tree sometimes a loop Upper level inductive with distributed caps On-chip level resistive with distributed caps 42

43 Role & Function of Bypass Capacitors Inserted between power and ground in path between supply and load Supply AC current to load faster than inductor can respond Can be distributed or lumpedintermediate between a transmission line and and an LC circuit In reality includes some resistance and inductance 43

44 Models for Inductive Section of Supply Network Distributed Lumped 44

45 LC Section Transient Response 40 nh & 10nF bypass cap fc=8 GHz 45

46 LC Section Transient Response For 1 st 10 ns cycles, the load draws an average current of 0.12A After 5 th cycle, the load current is shut off to accept step k C i B kq V max t ki t V i ck i av ck t 0 ( I I ) dt I avg t avg ck k i : maximum fraction of Charge transferred each cycle k i =1 for delta function k i =0 for DC typical: 0.25 < k i <0.5 46

47 Natural Frequency - LC tank will resonate at natural frequency Iavg V C V max I I C avg avg sin( t) C L sin( Ct) C L C To keep the ripple within a prescribed V, the capacitor must be sized so that C B 2 Iavg L V 47

48 Frequency Range for Bypass Capacitors Capacitors at low frequencies Actually an RLC circuit Resonance frequencies LC frequency RC frequency Ineffective at either of these frequencies 48

49 Natural Frequency of Bypass Capacitors Load currents at frequencies well below c see an inductive impedance. Load currents at high frequencies see a capacitor. At c, impedance is infinite At c, even small currents will cause oscillations 49

50 Typical Bypass Capacitors C R S L C F RC F LC F LR On-chip MOS 0.35 x 114 mm) On-chip MOS (1.4 x 115 m) 250 ff GHz 1 pf GHz SMT ceramic 1 nf nh 160 MZ SMT ceramic 10 nf 0.1 1nH 50 MHz Ceramic disk 10 nf nh 23 MHz Aluminum electrolytic 10 F 1 10 nh 160 khz 16 MHz Aluminum electrolytic 1000F nh 3 khz 800 khz 50

51 Bypass Capacitor & series Regulator 1A 0A 10 ns 50 ns L= 10 nh What value of C B will keep V L to 5% with - No regulator - Series regulator 3.3V to 2.5V 51

52 Bypass Capacitor & series Regulator 1A 0A 10 ns Q cap I avs 50 ns No regulator V=125 mv I av =200 ma Q cap =6.4 nc C B > 76.8 nf With regulator V=925 mv I av =200 ma Q cap =6.4 nc C B > 7.39 nf P supply =660W 52

53 Bypass Capacitor Network Design Using the parameters of the Table, derive a parallel combination of bypass capacitors that is able to supply the current needs of a load with the periodic triangular waveform sketched below that may start and stop abruptly. Your combined capacitor should hold voltage ripple to within 5% of the supply voltage. Assume that your capacitors are fed from a DC supply voltage of 3.3V through an inductance of 1 H.

54 Bypass Capacitor - Table C R S L C F RC F LC F LR On-chip MOS 0.35 x 114 mm) On-chip MOS (1.4 x 115 m) 250 ff GHz 1 pf GHz SMT ceramic 1 nf nh 160 MZ SMT ceramic 10 nf 0.1 1nH 50 MHz Ceramic disk 10 nf nh 23 MHz Aluminum electrolytic 10 F 1 10 nh 160 khz 16 MHz Aluminum electrolytic 1000F nh 3 khz 800 khz

55 Bypass Capacitor Network Design - Derive parallel combination of bypass capacitors - Hold voltage ripple to within 5% of supply voltage - DC supply of 3.3V - Generator internal inductance 1 H V in AC mode < 165mV 2) V Ldrop + V Cdrop < 165 mv 3) Capacitor must be operational above breakpoints Solution 55

56 I ave 10A1ns 1.67A 6ns Q (1ns0.167 ns)( A) 6.94nC cap 1 st Rank Average current and charge sourced by capacitor: In AC mode the V of the cap should be less than 165 mv, so: Qcap 6.94nC C rank1 42nF V 165mV Drop in series L must be less than 165mV V 165mV Lrank1 16.5pH di / dt 10A 1ns 56

57 1 st Rank - Need breakpoints above 1 GHz to insure true capacitor - From table, choose 60,000 1pF MOS on-chip cap (min:42,000) C 60 nf, L 0 rank1 rank1 R rank , resistance is negligible 57

58 2 nd Rank V Lrank 1 Crank Iave 2 165mV Lrank 2 60nF 586 ph 1.67A 2 Recall: To keep the ripple within a prescribed V, the capacitor must be sized so that 2 2 Iavg V CB L LCB V I avg Cannot connect the first rank up to the supply voltage since supply inductance is 1H and does not satisfy criterion Choose 12 SMT ceramic caps satisfies inductance calculations And doubles 1 st rank cap. C 120 nf, L 83.3pH rank 2 rank 2 R rank

59 3 rd Rank 165mV Lrank 3 120nF 1.17nH 1.67A Since this is less than the inductance of the supply, need to add 3 rd rank of caps Use 11 aluminum electrolytic caps 10nH Crank F, Lrank ph 11 1 R rank A 910mV V max 165 mv 2 This resistance looks high, need to determine the associated voltage drop NO GOOD 59

60 Need to reduce resistance to: 3 rd Rank R rank 3 165mV A Choose 60 aluminum electrolytic caps 10nH Crank F, Lrank ph 60 R rank

61 4 th Rank 165mV Lrank 4 600F 5.86H 1.67A 2 The inductance of the supply voltage satisfies this criterion no need for 4 th rank. 61

62 Power-Supply-Level Fluctuations Total capacitive load associated with an IC increases as minimum feature size shrinks Average current needed to charge capacitance increases Rate of change of current (di/dt) also increases Total chip current may change by large amounts within short periods of time Fluctuation at the power supply level due to self inductance in distribution lines 62

63 Reducing Power-Supply-Level Fluctuations Minimize di/dt noise Decoupling capacitors Multiple power & ground pins Taylored driver turn-on characteristics Decoupling capacitors Large capacitor charges up during steady state Assumes role of power supply during current switching Leads should be small to minimize parasitic inductance Must be placed as close as possible to the chip 63

64 Effects of SSN SSN can affect circuits in 3 ways 1) SSN may increase chip-to-chip delays 2) Affects the operation of the receiving chips 3) May affect gates on the sending chip Current driven off-chip has only one return path: power and ground pins of the chip carrier to minimize effective inductance of the return path and noise, many power/ground pins must be supplied for off-chip drivers On-chip circuitry can close the loop by small inductance on chip lines 64

65 Model for On-Chip Power Distribution 1) Portion of circuits switch 2) V dd -V SS is reduced 3) Non-switching devices come to rescue (through low inductance) 4) Share charge with switching capacitors 5) Power-level collapse is prevented 65

66 Design Criteria for SSN Inductive time constant must be much smaller than its capacitive time constant L R RC Valid for external power distribution lines that carry the current to the chip and for internal lines that distribute it on the chip - Presently satisfied by on-chip lines - Board and package power lines are too high to satisfy criteria 66

67 Design Criteria for SSN Cannot distribute power on the board simply by using the printed circuit wires and connecting them to the power/ground pins of the chip directly. Off chip power distribution must employ methods that reduce the effects of line and pin inductance. To insure reliable circuit operation: L di V dt DD Equivalence of 2 conditions is obtained by setting: di V / R DD dt RC 67

68 Resonance Condition at Power-Supply Lines - Periodic nature of digital circuits can cause resonance - Large fluctuation can build up and cause circuit to fail f chip 2 L 1 mod C chip Lmod Z( j chip ) R C chip chip - f chip should be much larger than the clock frequency - Resonant impedance should be kept small 68

69 Delta-I Noise in CMOS Circuits In a CMOS chip the portion of the circuit that is not switching (R 1, C 1 ) at a given system cycle helps the switching portion of the chip (R 2, C 2 ). C 1 VDD V VDD C1 C2 69

70 Delta-I Noise in ECL Bipolar Circuits Because of diode structure of BJTs, current can only flow in one direction V x DC current of gates (proportional to V x ) help reduce powersupply-level fluctuations R1 R1 V VDD For turn on V V for turn off DD R R R

71 Model for CMOS Power Distribution Network - n decoupling capacitors -L con is due to power connectors at edge of board -C board is intrinsic power and ground capacitance 71

72 Impedance of Power Distribution Network Influenced by Package and Bypass Cap Increase in low-frequency due to resonance frequency of board connector Increase in the high-frequency impedance due to resonance frequency of decoupling capacitor Keep both resonance frequencies away from operating frequency Z o Frequency 72

73 Off-Chip Driver SSN Calculations - Worst case on-chip delta-i noise generated at beginning of clock cycle - Main problem for on-chip drivers is lack of low-inductance return path - Off-chip drivers are the major source of SSN Problem: 32 low-impedance CMOS buffers (R S << Z o ) are switched simultaneously. In addition, the line impedance is 50, rise time is 2 nsec, output swing is 5 V, and the allowed power-supply-level fluctuation is 0.25V. Find the effective inductance. Solution: First, calculate the rate of change of the output voltage from the voltage swing and rise time dv 80% Vswing 80% 5V dt t 2nsec r 2 V / nsec 73

74 Off-Chip Driver SSN Calculations The current driven into the transmission line is I=V/Z o and its rate of change is: di 1 dv 2 V / nsec 0.04 A/ nsec dt Z dt 50 Total current transient for 32 drivers: di dt o TOT N drv Through a 1nH inductance the voltage drop is di 1.28 A/ nsec dt di V L 1.28V dt To guarantee a maximum of 0.25V voltage fluctuation, the effective inductance is L V di / dt 0.2nH

75 On-Chip Power and Ground Distribution Distribution Network for Peripheral Bonding Power and ground are brought onto the chip via bond pads located along the four edges Metal buses provide routing from the edges to the remainder of the chip Local Buses GND VP Bus GND Bus VP Bus GND Bus VP Bus Wiring Tracks VP GND Bus VP Bus GND Bus VP Bus 75

76 Model for On-Chip Power Distribution V P R P R P R V P R P R P R 1 V 1 V 1 V P 1 V 1 V 1 GND I 1 I 2 I 3 I 4 I 5 R P R P R P R P R P R P I N R P Lr P w 2NW P A P LW P 2Nk N/2 N/2 2 ij pk L r P IR pk P P 2 i1 i1 4NkP V ij A R V IR in continuum, J r x J LP /2 pk w pk w dx 0 kp 8kP P P r L 2 P r w N k P A P : resistivity : # of segments : Area : fraction of metal layer devoted to power buses 76

77 Design a power distribution network for a peripherally bonded ASIC. Your chip is 15 mm 15 mm in area and contains 1M gate equivalents. Each gate equivalent drives a 200-fF load (40 ff of gate and 160 ff of wire) and switches on average every third cycle of a 100MHz clock. What is the total power dissipation of your chip? Assuming a peak current to average current ratio of 4:1, what fraction of a metal layer (or how many metal layers) do you need to distribute power so the overall supply fluctuation of a 2.5V supply is 250 mv? dv 1 Iavg C *1 M *200 ff *2.5 V *100 MHz A dt 3 J I / (15 mm) A/ mm avg IR Drop - Example avg 2 2 J 4J A/ mm peak avg 2

78 IR Drop Therefore, the number of metal layers is K p 2 rw L Jpeak V If actual supply fluctuation is between Gnd and Vdd, each layer has less than 125mV fluctuation. Therefore, for each Gnd and Vdd, K p 2 rw L Jpeak V

79 On Chip IR Drop Large Voltage Drop Example: V IR =0.78V local supply down by 1.56V:unacceptable Voltage drop across global buses is dependent only on the fraction of metal layer devoted to each bus Remedy Use area bonded chip so that power need not be distributed from chip edge Use more or thicker metal layers Use on-chip bypass capacitors

80 Symbiotic Bypass Capacitors On-Chip Bypass Capacitors MOS transistor with source and drain tied together About half the capacitors are symbiotic 50K Gate Module Example Load capacitance C ld =100fF 4,000 gates switching simultaneously 46,000 gates with output loads across power supplies 2.3 nf Adequate to average supply current over a cycle

81 On Chip Bypass Capacitors Area Bonding Flip chip More power distribution to next level of packaging Reduce inductance Helps metal migration problem A capacitor satisfies the relation: C Reduces current load to average value B ki t i av ck V Thin oxide MOS capacitor: MOS transistor with source and drain tied together C ox rowl t ox

82 Modeling Power Distribution Networks (PDN) Ground planes power bus and return paths are not ideal and must be represented with parasitic inductors and resistors Resulting network is a two-dimensional lossy transmission line possibly non-uniform Bypass capacitors are needed to alleviate noise Simulation is computationally intensive 82

83 CAD Framework for PDN Design Challenge: Present-day extraction and simulation engines make up a large portion of the computational effort in the PDN flow start Determination of target impedance Impedance calculation of PDN Selection of chip location Circuit Simulator (SPICE) Determination of inductance and resistance from a chip to all node points RLGC Extractor Determination of the number and locations of decoupling capacitors, locations and parasitic values Placement of components and impedance re-calculation Value proposition: Use LIM, FEM/FMM and Macromodel generator to enhance accuracy, increase computational speed and achieve power closure end 83