Physical Design Considerations of One-level RRAM-based Routing Multiplexers
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1 Physical Design Considerations of One-level RRAM-based Ring Multiplexers Xifan Tang, Edouard Giacomin, Giovanni De Micheli and Pierre-Emmanuel Gaillardon March 20 th, 2017 For ISPD 17
2 Resistive Memory (RRAM) technology can offer Low on-resistance: source of high-performance Resistance independent from V DD : source of low-power Challenges in RRAM-based multiplexer design Co-integration of low-voltage V DD and high-voltage V prog V prog for RRAM programming circuits V DD for datapath circuits Eliminate crosstalk current between datapath and programming structures Consider physical design aspects Multiple wells, parasitic capacitances and physical location of 2 Motivation RRAMs
3 Resistive Memory Fabrication 3 Sandwiched structure Compatible with BEoL Between metal layers Two stable resistance states Filamentary conducting High Resistance State (HRS) Low Resistance State (LRS) Adjustable set process Large Iset => Low LRS
4 4T1R Programming Structure 4T(ransistor)1R(RAM) programming structure 1.4x larger in programming current than 2T1R Achieve smaller LRS Set and Reset are controlled by two pairs of programming transistors independently Vset,b P1 Vprog Iset Ireset Vprog P2 Vreset,b 4 datapath,in Vreset, N1 CP datapath, N2 Vset, [1] X. Tang et al., A Study on the Programming Structures for RRAM-Based FPGA Architectures, IEEE TCAS-I, Vol. 63, No. 4, pp , April 2016.
5 Potential of RRAM-based Multiplexers High-performance Small capacitance on critical path Low power RRAM LRS is independent from V DD CMOS MUX: C path = (2 n +1)C trans RRAM MUX: Cpath =2Cprog,trans+N CP 5
6 Naïve 4T1R-based Multiplexer Limitation 1: Programming current contribution from datapath inverters (Red arrows) Regular Well Input inverters P1 P2 in[n-1] N1... N2 A Metal wire group1 C...,well P0,well B,well R0 CP,0 RN-1,well Metal wire group2 N0 CP,N-1,well,well Regular Well Output inverter programming current crosstalk current 6
7 7 Naïve 4T1R-based Multiplexer Limitation 2: Breakdown threats of datapath transistors (highlighted in red) Deep N-well V DD,well (3.0V) >> Regular Well V DD (0.9V) Regular Well Input inverters P1 P2 in[n-1] N1... N2 A Metal wire group1 C programming current...,well P0,well B,well R0 CP,0 RN-1,well N0 CP,N-1,well,well crosstalk current Metal wire group2 Regular Well Output inverter
8 8 Naïve 4T1R-based Multiplexer Limitation 3: Long interconnecting wires between deep N-well and regular well Large parasitic resistances and capacitances Regular Well Input inverters P1 P2 in[n-1] N1... N2 A Metal wire group1 C programming current...,well P0,well B,well R0 CP,0 RN-1,well N0 CP,N-1,well,well crosstalk current Metal wire group2 Regular Well Output inverter
9 9 Improved 4T1R-based Multiplexer Address limitations of naïve design Regular Well Input inverters P1 P2 in[n-1] Cut off programming current from datapath inverters Avoid transistor breakdown Short interconnecting wires N1... N2 A Metal wire group1 C programming current P0...,well,well B,well R0 CP,0 RN-1 N0 CP,N-1,well,well crosstalk current,well Metal wire group2 Regular Well Output inverter Regular Well in[n-1] Metal wire group 1 RA CP,A RB CP,B,well well,well well
10 (a) 10 Improved 4T1R-based Multiplexer Three modes: Operating: V DD,well = V DD, well = Set RRAM: V DD,well = -V prog + 2V DD, well = -V prog +V DD Reset RRAM: V DD,well = V prog, well = V prog -V DD in[n-1] CP,A RA RB CP,B (b) in[n-1] P0 CP,A RA programming current -Vprog+2 -Vprog+2 -Vprog+ -Vprog+ N0 (c) in[n-1] CP,B Vprog Vprog- Vprog Vprog-
11 Improved 4T1R-based Multiplexer Advantage 1: zero programming current from datapath inverters Power-gated input inverters Regular Well Metal wire group 1 RA CP,A RB,well,well well 11 in[n-1] CP,B well
12 Advantage 2: datapath transistors are protected from high programming voltages (a) 12 Improved 4T1R-based Multiplexer Large voltage difference shifts from transistors to RRAMs Allow to use standard transistors in programming structures Higher density and smaller transistor capacitances! in[n-1] CP,A RA RB CP,B (b) in[n-1] P0 CP,A RA programming current -Vprog+2 -Vprog+2 -Vprog+ -Vprog+ N0 (c) in[n-1] CP,B Vprog Vprog- Vprog Vprog-
13 Improved 4T1R-based Multiplexer Advantage 3: only one interconnection between regular and deep N-wells Smaller parasitic capacitances! Regular Well Input inverters 13 P1 P2 in[n-1] N1... N2 A Metal wire group1 C programming current P0...,well,well B,well R0 CP,0 RN-1 N0 CP,N-1,well,well crosstalk current,well Metal wire group2 Regular Well Output inverter Regular Well in[n-1] Metal wire group 1 RA CP,A RB CP,B,well well,well well
14 Improved 4T1R-based Multiplexer Advantage 3: only one interconnection between regular and deep N-wells (Cross-section View) Smaller parasitic capacitances! Well spacing: L (a) MET2 VIA VIA RRAM VIA CON TACT MET1 CON TACT,well Vprog CON TACT well P++ N+ N+ P+ P+ N++ P+ P+ N+ N+ P++ N++ P+ P+ N+ N+ P++ N+ P+ P+ N+ N+ P++ N-Well P-Well P-Well Well spacing: L (b) VIA MET2 x RRAM y MET1 MET1 CON TACT CON TACT,well CON TACT well,well P++ N+ N+ P+ P+ N++ P+ P+ N+ N+ P++ N++ P+ P+ N+ N+ P++ N+ N+ P+ P+ N++ N-Well P-Well 14 P-Well
15 Improved 4T1R-based Multiplexer Share deep N-wells between cascaded multiplexers CMOS logic gates can locate in deep N-wells ina[0] ina[n-1]... M U X 0 A CMOS logic gates inb[0] inb[n-1]... M U X 1 B 15,well ina[0] ina[n-1] MUX0,well A,well,well CMOS logic gates,well,well inb[0] -,well,well,well,well inb[n-1] -,well,well + + B MUX1
16 Physical Location of RRAMs Close to input inverters or put inverters? Well spacing: L a) MET2 VIA VIA RRAM VIA CON TACT MET1 CON TACT,well Vprog CON TACT well P++ N+ N+ P+ P+ N++ P+ P+ N+ N+ P++ N++ P+ P+ N+ N+ P++ N+ P+ P+ N+ N+ P++ N-Well P-Well P-Well Well spacing: L b) VIA MET2 x RRAM y MET1 MET1 CON TACT CON TACT,well CON TACT well,well P++ N+ N+ P+ P+ N++ P+ P+ N+ N+ P++ N++ P+ P+ N+ N+ P++ N+ N+ P+ P+ N++ N-Well P-Well P-Well 16
17 Optimal Location of RRAM RC modelling and Minimize Elmore Delay Depend on technology parameters R inv R LRS C P R C L Depend on design parameters N x opt RRAM should be close to input inverters! 17
18 18 Experimental Methodology Use ASAP 7nm FinFET Process Design Kit W/L=28/20 nm, regular V DD =0.7V Logic transistors: regular Vt Programming transistors: super low Vt RRAM: 10nm feature size Stanford RRAM compact model R HRS =27MΩ, R LRS =1.6kΩ, I set =I reset =500µA, V set =V reset =0.9V, C P =4.5aF HSPICE simulation: delay and power results Lay: area results [1] X. Tang et al., Accurate power analysis for near-v t RRAM-based FPGA, FPL, pp. 1-4, 2015.
19 Experimental Methodology Baseline CMOS multiplexers Input size from 2 to 32 Transmission gates: 3 fins per FinFET N <= 12, one-level structure N > 12, two-level structure RRAM multiplexers Input size from 2 to 32 Sweep number of fins per FinFET from 1 to 3 One-level structure 19 [1] X. Tang et al., Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure, accepted to IEEE TCAS-I, 2016.
20 Transient Analysis RRAMs can set and reset successfully Functionality of multiplexer is correct 20
21 Best Number of Fins Programming transistor sizing technique Trade-off LRS and capacitances of programming transistors Metric: Best Delay Three fins per FinFET is the best choice LRS = ~4.3kΩ (Lowest is 1.6kΩ) Two fins for best PDP (a) Delay (ps) Fin no.=1, V DD =0.5V Fin no.=2, V DD =0.5V Fin no.=3, V DD =0.5V Fin no.=1, V DD =0.6V Fin no.=2, V DD =0.6V Fin no.=3, V DD =0.6V Fin no.=1, V DD =0.7V Fin no.=2, V DD =0.7V Fin no.=3, V DD =0.7V -15% -14% -21% MUX size 21 [1] X. Tang et al., A High-performance Low-power Near-Vt RRAM-based FPGA, ICFPT, pp , 2014.
22 Naïve vs. Improved RRAM-based Multiplexers Improved design is delay efficient RRAM location: on the top of input inverters! 22
23 Programming circuits RRAM-based vs.cmos Multiplexers 1.12µm Inputs inverters Outptut inverter Area reduction Total area = 1.94µm² Programming circuits 1.4x more efficient: input size Total = 16 Area of CMOS MUX = 2.70µm2 b) 1.62µm 1.73µm a) SRAMS Outptut inverter SRAMS First level Second level First level Outptut inverter SRAMS Programming circuits 1.66µm 1.12µm Inputs inverters Outptut inverter Total area = 1.94µm² Total area==2.70µm² 2.70µm² Total area Programming circuits 2 b) 23 Total Area MUX = 2.70µm 2 Total AreaofofCMOS RRAM MUX=1.94µm 1.62µm SRAMS Total Area of RRAM MUX = 1.94µm2 SRAMS Outptut SRAMS Total Area of SRAM MUX=2.70µm2
24 RRAM-based vs.cmos Multiplexers Delay efficiency when V DD is same 24 On average 2x efficiency Smaller capacitances Delay efficiency: CMOS V DD =0.7V while RRAM V DD =0.5V and 0.6V Still 30% delay reduction! RRAM LRS is not impacted by V DD
25 RRAM-based vs.cmos Multiplexers Power efficiency when V DD is same 25 On average 2x efficiency Smaller capacitances Power efficiency: CMOS V DD =0.7V while RRAM V DD =0.5V and 0.6V Up to 5.8 times With any performance loss!
26 Conclusion 26 Naïve 4T1R-based multiplexers have serious limitations Well organization, transistor breakdown, long interconnecting wires Proposed 4T1R-based multiplexers address all these limitations Study optimal location of RRAMs 4T1R-based multiplexers are both highperformance (2x) and low-power (2x) w.r.t. CMOS counterparts Low power achieved with performance loss!
27 Thank you! Q&A 27
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